14141 lines
1004 KiB
Plaintext
14141 lines
1004 KiB
Plaintext
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_mem_ctl :
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module el2_ifu_mem_ctl :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, flip ifu_axi_arready : UInt<1>, flip ifu_axi_rvalid : UInt<1>, flip ifu_axi_rid : UInt<3>, flip ifu_axi_rdata : UInt<64>, flip ifu_axi_rresp : UInt<2>, flip ifu_bus_clk_en : UInt<1>, flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>, flip ic_rd_data : UInt<64>, flip ic_debug_rd_data : UInt<71>, flip ictag_debug_rd_data : UInt<26>, flip ic_eccerr : UInt<2>, flip ic_parerr : UInt<2>, flip ic_rd_hit : UInt<2>, flip ic_tag_perr : UInt<1>, flip iccm_rd_data : UInt<64>, flip iccm_rd_data_ecc : UInt<78>, flip ifu_fetch_val : UInt<2>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, ifu_miss_state_idle : UInt<1>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_axi_awvalid : UInt<1>, ifu_axi_awid : UInt<3>, ifu_axi_awaddr : UInt<32>, ifu_axi_awregion : UInt<4>, ifu_axi_awlen : UInt<8>, ifu_axi_awsize : UInt<3>, ifu_axi_awburst : UInt<2>, ifu_axi_awlock : UInt<1>, ifu_axi_awcache : UInt<4>, ifu_axi_awprot : UInt<3>, ifu_axi_awqos : UInt<4>, ifu_axi_wvalid : UInt<1>, ifu_axi_wdata : UInt<64>, ifu_axi_wstrb : UInt<8>, ifu_axi_wlast : UInt<1>, ifu_axi_bready : UInt<1>, ifu_axi_arvalid : UInt<1>, ifu_axi_arid : UInt<3>, ifu_axi_araddr : UInt<32>, ifu_axi_arregion : UInt<4>, ifu_axi_arlen : UInt<8>, ifu_axi_arsize : UInt<3>, ifu_axi_arburst : UInt<2>, ifu_axi_arlock : UInt<1>, ifu_axi_arcache : UInt<4>, ifu_axi_arprot : UInt<3>, ifu_axi_arqos : UInt<4>, ifu_axi_rready : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, ic_rw_addr : UInt<31>, ic_wr_en : UInt<2>, ic_rd_en : UInt<1>, ic_wr_data : UInt<71>[2], ic_debug_wr_data : UInt<71>, ifu_ic_debug_rd_data : UInt<71>, ic_debug_addr : UInt<10>, ic_debug_rd_en : UInt<1>, ic_debug_wr_en : UInt<1>, ic_debug_tag_array : UInt<1>, ic_debug_way : UInt<2>, ic_tag_valid : UInt<2>, iccm_rw_addr : UInt<15>, iccm_wren : UInt<1>, iccm_rden : UInt<1>, iccm_wr_data : UInt<78>, iccm_wr_size : UInt<3>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, iccm_rd_ecc_single_err : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, ic_error_start : UInt<1>, ifu_async_error_start : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, ic_premux_data : UInt<64>, ic_sel_premux_data : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_ic_debug_rd_data_valid : UInt<1>, iccm_buf_correct_ecc : UInt<1>, iccm_correction_state : UInt<1>, flip scan_mode : UInt<1>, valids : UInt, tagv_mb_in : UInt, test : UInt}
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io.ifu_axi_wvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 135:21]
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io.ifu_axi_wdata <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 136:20]
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io.ifu_axi_awqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 137:20]
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io.ifu_axi_awaddr <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 138:21]
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io.ifu_axi_awprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 139:21]
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io.ifu_axi_awlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 140:20]
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io.ifu_axi_arlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 141:21]
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io.ifu_axi_awregion <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 142:23]
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io.ifu_axi_awid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 143:19]
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io.ifu_axi_awvalid <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 144:22]
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io.ifu_axi_wstrb <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 145:20]
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io.ifu_axi_awcache <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 146:22]
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io.ifu_axi_arqos <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 147:20]
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io.ifu_axi_awlock <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 148:21]
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io.ifu_axi_bready <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 149:21]
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io.ifu_axi_arlen <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 150:20]
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io.ifu_axi_awsize <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 151:21]
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io.ifu_axi_arprot <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 152:21]
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io.ifu_axi_awburst <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 153:22]
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io.ifu_axi_wlast <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 154:20]
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wire iccm_single_ecc_error : UInt<2>
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iccm_single_ecc_error <= UInt<1>("h00")
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wire ifc_fetch_req_f : UInt<1>
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ifc_fetch_req_f <= UInt<1>("h00")
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wire miss_pending : UInt<1>
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miss_pending <= UInt<1>("h00")
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wire scnd_miss_req : UInt<1>
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scnd_miss_req <= UInt<1>("h00")
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wire dma_iccm_req_f : UInt<1>
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dma_iccm_req_f <= UInt<1>("h00")
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wire iccm_correct_ecc : UInt<1>
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iccm_correct_ecc <= UInt<1>("h00")
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wire perr_state : UInt<3>
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perr_state <= UInt<1>("h00")
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wire err_stop_state : UInt<2>
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err_stop_state <= UInt<1>("h00")
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wire err_stop_fetch : UInt<1>
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err_stop_fetch <= UInt<1>("h00")
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wire miss_state : UInt<3>
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miss_state <= UInt<1>("h00")
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wire miss_nxtstate : UInt<3>
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miss_nxtstate <= UInt<1>("h00")
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wire miss_state_en : UInt<1>
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miss_state_en <= UInt<1>("h00")
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wire ifu_bus_rsp_valid : UInt<1>
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ifu_bus_rsp_valid <= UInt<1>("h00")
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wire bus_ifu_bus_clk_en : UInt<1>
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bus_ifu_bus_clk_en <= UInt<1>("h00")
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wire ifu_bus_rsp_ready : UInt<1>
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ifu_bus_rsp_ready <= UInt<1>("h00")
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wire uncacheable_miss_ff : UInt<1>
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uncacheable_miss_ff <= UInt<1>("h00")
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wire ic_act_miss_f : UInt<1>
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ic_act_miss_f <= UInt<1>("h00")
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wire ic_byp_hit_f : UInt<1>
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ic_byp_hit_f <= UInt<1>("h00")
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wire bus_new_data_beat_count : UInt<3>
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bus_new_data_beat_count <= UInt<1>("h00")
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wire bus_ifu_wr_en_ff : UInt<1>
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bus_ifu_wr_en_ff <= UInt<1>("h00")
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wire last_beat : UInt<1>
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last_beat <= UInt<1>("h00")
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wire last_data_recieved_ff : UInt<1>
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last_data_recieved_ff <= UInt<1>("h00")
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wire stream_eol_f : UInt<1>
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stream_eol_f <= UInt<1>("h00")
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wire ic_miss_under_miss_f : UInt<1>
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ic_miss_under_miss_f <= UInt<1>("h00")
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wire ic_ignore_2nd_miss_f : UInt<1>
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ic_ignore_2nd_miss_f <= UInt<1>("h00")
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wire ic_debug_rd_en_ff : UInt<1>
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ic_debug_rd_en_ff <= UInt<1>("h00")
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reg flush_final_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 187:30]
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flush_final_f <= io.exu_flush_final @[el2_ifu_mem_ctl.scala 187:30]
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node _T = or(io.ifc_fetch_req_bf_raw, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 188:53]
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node _T_1 = or(_T, miss_pending) @[el2_ifu_mem_ctl.scala 188:71]
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node _T_2 = or(_T_1, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 188:86]
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node fetch_bf_f_c1_clken = or(_T_2, scnd_miss_req) @[el2_ifu_mem_ctl.scala 188:107]
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node debug_c1_clken = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 189:42]
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node _T_3 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 192:52]
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node _T_4 = bits(dma_iccm_req_f, 0, 0) @[el2_ifu_mem_ctl.scala 192:78]
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node _T_5 = and(_T_3, _T_4) @[el2_ifu_mem_ctl.scala 192:55]
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io.iccm_dma_sb_error <= _T_5 @[el2_ifu_mem_ctl.scala 192:24]
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node _T_6 = or(io.iccm_rd_ecc_single_err, io.ic_error_start) @[el2_ifu_mem_ctl.scala 193:57]
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io.ifu_async_error_start <= _T_6 @[el2_ifu_mem_ctl.scala 193:28]
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node _T_7 = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 194:54]
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node _T_8 = or(iccm_correct_ecc, _T_7) @[el2_ifu_mem_ctl.scala 194:40]
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node _T_9 = eq(err_stop_state, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 194:90]
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node _T_10 = or(_T_8, _T_9) @[el2_ifu_mem_ctl.scala 194:72]
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node _T_11 = or(_T_10, err_stop_fetch) @[el2_ifu_mem_ctl.scala 194:112]
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node _T_12 = or(_T_11, io.dec_tlu_flush_err_wb) @[el2_ifu_mem_ctl.scala 194:129]
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io.ic_dma_active <= _T_12 @[el2_ifu_mem_ctl.scala 194:20]
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node _T_13 = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 196:44]
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node _T_14 = and(_T_13, ifu_bus_rsp_ready) @[el2_ifu_mem_ctl.scala 196:65]
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node _T_15 = andr(bus_new_data_beat_count) @[el2_ifu_mem_ctl.scala 196:112]
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node _T_16 = and(_T_14, _T_15) @[el2_ifu_mem_ctl.scala 196:85]
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node _T_17 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 197:5]
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node _T_18 = and(_T_16, _T_17) @[el2_ifu_mem_ctl.scala 196:118]
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node _T_19 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 197:41]
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node _T_20 = eq(miss_nxtstate, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 197:73]
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node _T_21 = or(_T_19, _T_20) @[el2_ifu_mem_ctl.scala 197:57]
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node _T_22 = and(_T_18, _T_21) @[el2_ifu_mem_ctl.scala 197:26]
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node _T_23 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 197:93]
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node scnd_miss_req_in = and(_T_22, _T_23) @[el2_ifu_mem_ctl.scala 197:91]
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node ifu_bp_hit_taken_q_f = and(io.ifu_bp_hit_taken_f, io.ic_hit_f) @[el2_ifu_mem_ctl.scala 199:52]
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node _T_24 = eq(UInt<3>("h00"), miss_state) @[Conditional.scala 37:30]
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when _T_24 : @[Conditional.scala 40:58]
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node _T_25 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 203:45]
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node _T_26 = and(ic_act_miss_f, _T_25) @[el2_ifu_mem_ctl.scala 203:43]
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node _T_27 = bits(_T_26, 0, 0) @[el2_ifu_mem_ctl.scala 203:66]
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node _T_28 = mux(_T_27, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 203:27]
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miss_nxtstate <= _T_28 @[el2_ifu_mem_ctl.scala 203:21]
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node _T_29 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 204:40]
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node _T_30 = and(ic_act_miss_f, _T_29) @[el2_ifu_mem_ctl.scala 204:38]
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miss_state_en <= _T_30 @[el2_ifu_mem_ctl.scala 204:21]
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skip @[Conditional.scala 40:58]
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else : @[Conditional.scala 39:67]
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node _T_31 = eq(UInt<3>("h01"), miss_state) @[Conditional.scala 37:30]
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when _T_31 : @[Conditional.scala 39:67]
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node _T_32 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 207:113]
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node _T_33 = or(last_data_recieved_ff, _T_32) @[el2_ifu_mem_ctl.scala 207:93]
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node _T_34 = and(ic_byp_hit_f, _T_33) @[el2_ifu_mem_ctl.scala 207:67]
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node _T_35 = and(_T_34, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 207:127]
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node _T_36 = or(io.dec_tlu_force_halt, _T_35) @[el2_ifu_mem_ctl.scala 207:51]
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node _T_37 = bits(_T_36, 0, 0) @[el2_ifu_mem_ctl.scala 207:152]
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node _T_38 = eq(last_data_recieved_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 208:30]
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node _T_39 = and(ic_byp_hit_f, _T_38) @[el2_ifu_mem_ctl.scala 208:27]
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node _T_40 = and(_T_39, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 208:53]
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node _T_41 = bits(_T_40, 0, 0) @[el2_ifu_mem_ctl.scala 208:77]
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node _T_42 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 209:16]
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node _T_43 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 209:32]
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node _T_44 = and(_T_42, _T_43) @[el2_ifu_mem_ctl.scala 209:30]
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node _T_45 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 209:72]
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node _T_46 = and(_T_44, _T_45) @[el2_ifu_mem_ctl.scala 209:52]
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node _T_47 = and(_T_46, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 209:85]
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node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_mem_ctl.scala 209:109]
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node _T_49 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 210:36]
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node _T_50 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 210:51]
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node _T_51 = and(_T_49, _T_50) @[el2_ifu_mem_ctl.scala 210:49]
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node _T_52 = bits(_T_51, 0, 0) @[el2_ifu_mem_ctl.scala 210:73]
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node _T_53 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:35]
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node _T_54 = and(ic_byp_hit_f, _T_53) @[el2_ifu_mem_ctl.scala 211:33]
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node _T_55 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 211:76]
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node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:57]
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node _T_57 = and(_T_54, _T_56) @[el2_ifu_mem_ctl.scala 211:55]
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node _T_58 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:91]
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node _T_59 = and(_T_57, _T_58) @[el2_ifu_mem_ctl.scala 211:89]
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node _T_60 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 211:115]
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node _T_61 = and(_T_59, _T_60) @[el2_ifu_mem_ctl.scala 211:113]
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node _T_62 = bits(_T_61, 0, 0) @[el2_ifu_mem_ctl.scala 211:137]
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node _T_63 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 212:41]
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node _T_64 = and(bus_ifu_wr_en_ff, _T_63) @[el2_ifu_mem_ctl.scala 212:39]
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node _T_65 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 212:82]
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node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 212:63]
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node _T_67 = and(_T_64, _T_66) @[el2_ifu_mem_ctl.scala 212:61]
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node _T_68 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 212:97]
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node _T_69 = and(_T_67, _T_68) @[el2_ifu_mem_ctl.scala 212:95]
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node _T_70 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 212:121]
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node _T_71 = and(_T_69, _T_70) @[el2_ifu_mem_ctl.scala 212:119]
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node _T_72 = bits(_T_71, 0, 0) @[el2_ifu_mem_ctl.scala 212:143]
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node _T_73 = eq(ic_byp_hit_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 213:22]
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node _T_74 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 213:40]
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node _T_75 = and(_T_73, _T_74) @[el2_ifu_mem_ctl.scala 213:37]
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node _T_76 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 213:81]
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node _T_77 = and(_T_75, _T_76) @[el2_ifu_mem_ctl.scala 213:60]
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node _T_78 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 213:102]
|
|
node _T_79 = and(_T_77, _T_78) @[el2_ifu_mem_ctl.scala 213:100]
|
|
node _T_80 = bits(_T_79, 0, 0) @[el2_ifu_mem_ctl.scala 213:124]
|
|
node _T_81 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 214:44]
|
|
node _T_82 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 214:89]
|
|
node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 214:70]
|
|
node _T_84 = and(_T_81, _T_83) @[el2_ifu_mem_ctl.scala 214:68]
|
|
node _T_85 = bits(_T_84, 0, 0) @[el2_ifu_mem_ctl.scala 214:103]
|
|
node _T_86 = mux(_T_85, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 214:22]
|
|
node _T_87 = mux(_T_80, UInt<3>("h00"), _T_86) @[el2_ifu_mem_ctl.scala 213:20]
|
|
node _T_88 = mux(_T_72, UInt<3>("h06"), _T_87) @[el2_ifu_mem_ctl.scala 212:20]
|
|
node _T_89 = mux(_T_62, UInt<3>("h06"), _T_88) @[el2_ifu_mem_ctl.scala 211:18]
|
|
node _T_90 = mux(_T_52, UInt<3>("h00"), _T_89) @[el2_ifu_mem_ctl.scala 210:16]
|
|
node _T_91 = mux(_T_48, UInt<3>("h04"), _T_90) @[el2_ifu_mem_ctl.scala 209:14]
|
|
node _T_92 = mux(_T_41, UInt<3>("h03"), _T_91) @[el2_ifu_mem_ctl.scala 208:12]
|
|
node _T_93 = mux(_T_37, UInt<3>("h00"), _T_92) @[el2_ifu_mem_ctl.scala 207:27]
|
|
miss_nxtstate <= _T_93 @[el2_ifu_mem_ctl.scala 207:21]
|
|
node _T_94 = or(io.dec_tlu_force_halt, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 215:46]
|
|
node _T_95 = or(_T_94, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 215:67]
|
|
node _T_96 = or(_T_95, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 215:82]
|
|
node _T_97 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 215:125]
|
|
node _T_98 = or(_T_96, _T_97) @[el2_ifu_mem_ctl.scala 215:105]
|
|
node _T_99 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 215:160]
|
|
node _T_100 = and(bus_ifu_wr_en_ff, _T_99) @[el2_ifu_mem_ctl.scala 215:158]
|
|
node _T_101 = or(_T_98, _T_100) @[el2_ifu_mem_ctl.scala 215:138]
|
|
miss_state_en <= _T_101 @[el2_ifu_mem_ctl.scala 215:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_102 = eq(UInt<3>("h04"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_102 : @[Conditional.scala 39:67]
|
|
miss_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 218:21]
|
|
node _T_103 = or(io.exu_flush_final, flush_final_f) @[el2_ifu_mem_ctl.scala 219:43]
|
|
node _T_104 = or(_T_103, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 219:59]
|
|
node _T_105 = or(_T_104, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 219:74]
|
|
miss_state_en <= _T_105 @[el2_ifu_mem_ctl.scala 219:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_106 = eq(UInt<3>("h06"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_106 : @[Conditional.scala 39:67]
|
|
node _T_107 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 222:49]
|
|
node _T_108 = or(_T_107, stream_eol_f) @[el2_ifu_mem_ctl.scala 222:72]
|
|
node _T_109 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 222:108]
|
|
node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 222:89]
|
|
node _T_111 = and(_T_108, _T_110) @[el2_ifu_mem_ctl.scala 222:87]
|
|
node _T_112 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 222:124]
|
|
node _T_113 = and(_T_111, _T_112) @[el2_ifu_mem_ctl.scala 222:122]
|
|
node _T_114 = bits(_T_113, 0, 0) @[el2_ifu_mem_ctl.scala 222:148]
|
|
node _T_115 = mux(_T_114, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 222:27]
|
|
miss_nxtstate <= _T_115 @[el2_ifu_mem_ctl.scala 222:21]
|
|
node _T_116 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 223:43]
|
|
node _T_117 = or(_T_116, stream_eol_f) @[el2_ifu_mem_ctl.scala 223:67]
|
|
node _T_118 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 223:105]
|
|
node _T_119 = or(_T_117, _T_118) @[el2_ifu_mem_ctl.scala 223:84]
|
|
node _T_120 = or(_T_119, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 223:118]
|
|
miss_state_en <= _T_120 @[el2_ifu_mem_ctl.scala 223:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_121 = eq(UInt<3>("h03"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_121 : @[Conditional.scala 39:67]
|
|
node _T_122 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 226:69]
|
|
node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 226:50]
|
|
node _T_124 = and(io.exu_flush_final, _T_123) @[el2_ifu_mem_ctl.scala 226:48]
|
|
node _T_125 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 226:84]
|
|
node _T_126 = and(_T_124, _T_125) @[el2_ifu_mem_ctl.scala 226:82]
|
|
node _T_127 = bits(_T_126, 0, 0) @[el2_ifu_mem_ctl.scala 226:108]
|
|
node _T_128 = mux(_T_127, UInt<3>("h02"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 226:27]
|
|
miss_nxtstate <= _T_128 @[el2_ifu_mem_ctl.scala 226:21]
|
|
node _T_129 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 227:63]
|
|
node _T_130 = or(io.exu_flush_final, _T_129) @[el2_ifu_mem_ctl.scala 227:43]
|
|
node _T_131 = or(_T_130, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 227:76]
|
|
miss_state_en <= _T_131 @[el2_ifu_mem_ctl.scala 227:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_132 = eq(UInt<3>("h02"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_132 : @[Conditional.scala 39:67]
|
|
node _T_133 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 230:71]
|
|
node _T_134 = eq(_T_133, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 230:52]
|
|
node _T_135 = and(ic_miss_under_miss_f, _T_134) @[el2_ifu_mem_ctl.scala 230:50]
|
|
node _T_136 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 230:86]
|
|
node _T_137 = and(_T_135, _T_136) @[el2_ifu_mem_ctl.scala 230:84]
|
|
node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_mem_ctl.scala 230:110]
|
|
node _T_139 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 231:56]
|
|
node _T_140 = eq(_T_139, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 231:37]
|
|
node _T_141 = and(ic_ignore_2nd_miss_f, _T_140) @[el2_ifu_mem_ctl.scala 231:35]
|
|
node _T_142 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 231:71]
|
|
node _T_143 = and(_T_141, _T_142) @[el2_ifu_mem_ctl.scala 231:69]
|
|
node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_mem_ctl.scala 231:95]
|
|
node _T_145 = mux(_T_144, UInt<3>("h07"), UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 231:12]
|
|
node _T_146 = mux(_T_138, UInt<3>("h05"), _T_145) @[el2_ifu_mem_ctl.scala 230:27]
|
|
miss_nxtstate <= _T_146 @[el2_ifu_mem_ctl.scala 230:21]
|
|
node _T_147 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 232:42]
|
|
node _T_148 = or(_T_147, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 232:55]
|
|
node _T_149 = or(_T_148, ic_ignore_2nd_miss_f) @[el2_ifu_mem_ctl.scala 232:78]
|
|
node _T_150 = or(_T_149, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 232:101]
|
|
miss_state_en <= _T_150 @[el2_ifu_mem_ctl.scala 232:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_151 = eq(UInt<3>("h05"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_151 : @[Conditional.scala 39:67]
|
|
node _T_152 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 236:31]
|
|
node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_mem_ctl.scala 236:44]
|
|
node _T_154 = mux(_T_153, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 236:12]
|
|
node _T_155 = mux(io.exu_flush_final, _T_154, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 235:62]
|
|
node _T_156 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_155) @[el2_ifu_mem_ctl.scala 235:27]
|
|
miss_nxtstate <= _T_156 @[el2_ifu_mem_ctl.scala 235:21]
|
|
node _T_157 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 237:42]
|
|
node _T_158 = or(_T_157, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 237:55]
|
|
node _T_159 = or(_T_158, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 237:76]
|
|
miss_state_en <= _T_159 @[el2_ifu_mem_ctl.scala 237:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_160 = eq(UInt<3>("h07"), miss_state) @[Conditional.scala 37:30]
|
|
when _T_160 : @[Conditional.scala 39:67]
|
|
node _T_161 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 241:31]
|
|
node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_mem_ctl.scala 241:44]
|
|
node _T_163 = mux(_T_162, UInt<3>("h00"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 241:12]
|
|
node _T_164 = mux(io.exu_flush_final, _T_163, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 240:62]
|
|
node _T_165 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), _T_164) @[el2_ifu_mem_ctl.scala 240:27]
|
|
miss_nxtstate <= _T_165 @[el2_ifu_mem_ctl.scala 240:21]
|
|
node _T_166 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 242:42]
|
|
node _T_167 = or(_T_166, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 242:55]
|
|
node _T_168 = or(_T_167, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 242:76]
|
|
miss_state_en <= _T_168 @[el2_ifu_mem_ctl.scala 242:21]
|
|
skip @[Conditional.scala 39:67]
|
|
node _T_169 = bits(miss_state_en, 0, 0) @[el2_ifu_mem_ctl.scala 245:61]
|
|
reg _T_170 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_169 : @[Reg.scala 28:19]
|
|
_T_170 <= miss_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
miss_state <= _T_170 @[el2_ifu_mem_ctl.scala 245:14]
|
|
wire crit_byp_hit_f : UInt<1>
|
|
crit_byp_hit_f <= UInt<1>("h00")
|
|
wire way_status_mb_scnd_ff : UInt<1>
|
|
way_status_mb_scnd_ff <= UInt<1>("h00")
|
|
wire way_status : UInt<1>
|
|
way_status <= UInt<1>("h00")
|
|
wire tagv_mb_scnd_ff : UInt<2>
|
|
tagv_mb_scnd_ff <= UInt<1>("h00")
|
|
wire uncacheable_miss_scnd_ff : UInt<1>
|
|
uncacheable_miss_scnd_ff <= UInt<1>("h00")
|
|
wire imb_scnd_ff : UInt<31>
|
|
imb_scnd_ff <= UInt<1>("h00")
|
|
wire reset_all_tags : UInt<1>
|
|
reset_all_tags <= UInt<1>("h00")
|
|
wire bus_rd_addr_count : UInt<3>
|
|
bus_rd_addr_count <= UInt<1>("h00")
|
|
wire ifu_bus_rid_ff : UInt<3>
|
|
ifu_bus_rid_ff <= UInt<1>("h00")
|
|
node _T_171 = neq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 255:30]
|
|
miss_pending <= _T_171 @[el2_ifu_mem_ctl.scala 255:16]
|
|
node _T_172 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 256:39]
|
|
node _T_173 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 256:73]
|
|
node _T_174 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 256:95]
|
|
node _T_175 = and(_T_173, _T_174) @[el2_ifu_mem_ctl.scala 256:93]
|
|
node crit_wd_byp_ok_ff = or(_T_172, _T_175) @[el2_ifu_mem_ctl.scala 256:58]
|
|
node _T_176 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 257:57]
|
|
node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:38]
|
|
node _T_178 = and(miss_pending, _T_177) @[el2_ifu_mem_ctl.scala 257:36]
|
|
node _T_179 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 257:86]
|
|
node _T_180 = and(_T_179, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 257:106]
|
|
node _T_181 = eq(_T_180, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 257:72]
|
|
node _T_182 = and(_T_178, _T_181) @[el2_ifu_mem_ctl.scala 257:70]
|
|
node _T_183 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 258:37]
|
|
node _T_184 = and(_T_183, crit_byp_hit_f) @[el2_ifu_mem_ctl.scala 258:57]
|
|
node _T_185 = eq(_T_184, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 258:23]
|
|
node _T_186 = and(_T_182, _T_185) @[el2_ifu_mem_ctl.scala 257:128]
|
|
node _T_187 = or(_T_186, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 258:77]
|
|
node _T_188 = eq(miss_nxtstate, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 259:36]
|
|
node _T_189 = and(miss_pending, _T_188) @[el2_ifu_mem_ctl.scala 259:19]
|
|
node sel_hold_imb = or(_T_187, _T_189) @[el2_ifu_mem_ctl.scala 258:93]
|
|
node _T_190 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 261:40]
|
|
node _T_191 = or(_T_190, ic_miss_under_miss_f) @[el2_ifu_mem_ctl.scala 261:57]
|
|
node _T_192 = eq(flush_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 261:83]
|
|
node sel_hold_imb_scnd = and(_T_191, _T_192) @[el2_ifu_mem_ctl.scala 261:81]
|
|
node _T_193 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 262:46]
|
|
node way_status_mb_scnd_in = mux(_T_193, way_status_mb_scnd_ff, way_status) @[el2_ifu_mem_ctl.scala 262:34]
|
|
node _T_194 = eq(miss_state, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 264:40]
|
|
node _T_195 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 264:96]
|
|
node _T_196 = bits(_T_195, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_197 = mux(_T_196, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_198 = and(_T_197, io.ic_tag_valid) @[el2_ifu_mem_ctl.scala 264:113]
|
|
node tagv_mb_scnd_in = mux(_T_194, tagv_mb_scnd_ff, _T_198) @[el2_ifu_mem_ctl.scala 264:28]
|
|
node _T_199 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 265:56]
|
|
node uncacheable_miss_scnd_in = mux(_T_199, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 265:37]
|
|
reg _T_200 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 266:38]
|
|
_T_200 <= uncacheable_miss_scnd_in @[el2_ifu_mem_ctl.scala 266:38]
|
|
uncacheable_miss_scnd_ff <= _T_200 @[el2_ifu_mem_ctl.scala 266:28]
|
|
node _T_201 = bits(sel_hold_imb_scnd, 0, 0) @[el2_ifu_mem_ctl.scala 267:43]
|
|
node imb_scnd_in = mux(_T_201, imb_scnd_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 267:24]
|
|
reg _T_202 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 268:25]
|
|
_T_202 <= imb_scnd_in @[el2_ifu_mem_ctl.scala 268:25]
|
|
imb_scnd_ff <= _T_202 @[el2_ifu_mem_ctl.scala 268:15]
|
|
reg _T_203 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 269:35]
|
|
_T_203 <= way_status_mb_scnd_in @[el2_ifu_mem_ctl.scala 269:35]
|
|
way_status_mb_scnd_ff <= _T_203 @[el2_ifu_mem_ctl.scala 269:25]
|
|
reg _T_204 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 270:29]
|
|
_T_204 <= tagv_mb_scnd_in @[el2_ifu_mem_ctl.scala 270:29]
|
|
tagv_mb_scnd_ff <= _T_204 @[el2_ifu_mem_ctl.scala 270:19]
|
|
node _T_205 = bits(bus_ifu_wr_en_ff, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_206 = mux(_T_205, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node ic_wr_addr_bits_hi_3 = and(ifu_bus_rid_ff, _T_206) @[el2_ifu_mem_ctl.scala 273:45]
|
|
wire ifc_iccm_access_f : UInt<1>
|
|
ifc_iccm_access_f <= UInt<1>("h00")
|
|
wire ifc_region_acc_fault_final_f : UInt<1>
|
|
ifc_region_acc_fault_final_f <= UInt<1>("h00")
|
|
node _T_207 = eq(ifc_iccm_access_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 276:48]
|
|
node _T_208 = and(ifc_fetch_req_f, _T_207) @[el2_ifu_mem_ctl.scala 276:46]
|
|
node _T_209 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 276:69]
|
|
node fetch_req_icache_f = and(_T_208, _T_209) @[el2_ifu_mem_ctl.scala 276:67]
|
|
node fetch_req_iccm_f = and(ifc_fetch_req_f, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 277:46]
|
|
node _T_210 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 278:45]
|
|
node _T_211 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 278:73]
|
|
node _T_212 = or(_T_210, _T_211) @[el2_ifu_mem_ctl.scala 278:59]
|
|
node _T_213 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 278:105]
|
|
node _T_214 = or(_T_212, _T_213) @[el2_ifu_mem_ctl.scala 278:91]
|
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node ic_iccm_hit_f = and(fetch_req_iccm_f, _T_214) @[el2_ifu_mem_ctl.scala 278:41]
|
|
wire stream_hit_f : UInt<1>
|
|
stream_hit_f <= UInt<1>("h00")
|
|
node _T_215 = or(crit_byp_hit_f, stream_hit_f) @[el2_ifu_mem_ctl.scala 280:35]
|
|
node _T_216 = and(_T_215, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 280:52]
|
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node _T_217 = and(_T_216, miss_pending) @[el2_ifu_mem_ctl.scala 280:73]
|
|
ic_byp_hit_f <= _T_217 @[el2_ifu_mem_ctl.scala 280:16]
|
|
wire sel_mb_addr_ff : UInt<1>
|
|
sel_mb_addr_ff <= UInt<1>("h00")
|
|
wire imb_ff : UInt<31>
|
|
imb_ff <= UInt<1>("h00")
|
|
wire ifu_fetch_addr_int_f : UInt<31>
|
|
ifu_fetch_addr_int_f <= UInt<1>("h00")
|
|
node _T_218 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 284:35]
|
|
node _T_219 = and(_T_218, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 284:39]
|
|
node _T_220 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 284:62]
|
|
node _T_221 = and(_T_219, _T_220) @[el2_ifu_mem_ctl.scala 284:60]
|
|
node _T_222 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 284:81]
|
|
node _T_223 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 284:108]
|
|
node _T_224 = or(_T_222, _T_223) @[el2_ifu_mem_ctl.scala 284:95]
|
|
node _T_225 = and(_T_221, _T_224) @[el2_ifu_mem_ctl.scala 284:78]
|
|
node _T_226 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 284:128]
|
|
node ic_act_hit_f = and(_T_225, _T_226) @[el2_ifu_mem_ctl.scala 284:126]
|
|
node _T_227 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 285:37]
|
|
node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 285:23]
|
|
node _T_229 = or(_T_228, reset_all_tags) @[el2_ifu_mem_ctl.scala 285:41]
|
|
node _T_230 = and(_T_229, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 285:59]
|
|
node _T_231 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 285:82]
|
|
node _T_232 = and(_T_230, _T_231) @[el2_ifu_mem_ctl.scala 285:80]
|
|
node _T_233 = or(_T_232, scnd_miss_req) @[el2_ifu_mem_ctl.scala 285:97]
|
|
node _T_234 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 285:116]
|
|
node _T_235 = and(_T_233, _T_234) @[el2_ifu_mem_ctl.scala 285:114]
|
|
ic_act_miss_f <= _T_235 @[el2_ifu_mem_ctl.scala 285:17]
|
|
node _T_236 = eq(io.ic_rd_hit, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 286:28]
|
|
node _T_237 = or(_T_236, reset_all_tags) @[el2_ifu_mem_ctl.scala 286:42]
|
|
node _T_238 = and(_T_237, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 286:60]
|
|
node _T_239 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 286:94]
|
|
node _T_240 = and(_T_238, _T_239) @[el2_ifu_mem_ctl.scala 286:81]
|
|
node _T_241 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 287:12]
|
|
node _T_242 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 287:63]
|
|
node _T_243 = neq(_T_241, _T_242) @[el2_ifu_mem_ctl.scala 287:39]
|
|
node _T_244 = and(_T_240, _T_243) @[el2_ifu_mem_ctl.scala 286:111]
|
|
node _T_245 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 287:93]
|
|
node _T_246 = and(_T_244, _T_245) @[el2_ifu_mem_ctl.scala 287:91]
|
|
node _T_247 = eq(sel_mb_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 287:116]
|
|
node _T_248 = and(_T_246, _T_247) @[el2_ifu_mem_ctl.scala 287:114]
|
|
node _T_249 = eq(ifc_region_acc_fault_final_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 287:134]
|
|
node _T_250 = and(_T_248, _T_249) @[el2_ifu_mem_ctl.scala 287:132]
|
|
ic_miss_under_miss_f <= _T_250 @[el2_ifu_mem_ctl.scala 286:24]
|
|
node _T_251 = orr(io.ic_rd_hit) @[el2_ifu_mem_ctl.scala 288:42]
|
|
node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 288:28]
|
|
node _T_253 = or(_T_252, reset_all_tags) @[el2_ifu_mem_ctl.scala 288:46]
|
|
node _T_254 = and(_T_253, fetch_req_icache_f) @[el2_ifu_mem_ctl.scala 288:64]
|
|
node _T_255 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 288:99]
|
|
node _T_256 = and(_T_254, _T_255) @[el2_ifu_mem_ctl.scala 288:85]
|
|
node _T_257 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 289:13]
|
|
node _T_258 = bits(ifu_fetch_addr_int_f, 30, 5) @[el2_ifu_mem_ctl.scala 289:62]
|
|
node _T_259 = eq(_T_257, _T_258) @[el2_ifu_mem_ctl.scala 289:39]
|
|
node _T_260 = or(_T_259, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 289:91]
|
|
node _T_261 = and(_T_256, _T_260) @[el2_ifu_mem_ctl.scala 288:117]
|
|
ic_ignore_2nd_miss_f <= _T_261 @[el2_ifu_mem_ctl.scala 288:24]
|
|
node _T_262 = or(ic_act_hit_f, ic_byp_hit_f) @[el2_ifu_mem_ctl.scala 291:31]
|
|
node _T_263 = or(_T_262, ic_iccm_hit_f) @[el2_ifu_mem_ctl.scala 291:46]
|
|
node _T_264 = and(ifc_region_acc_fault_final_f, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 291:94]
|
|
node _T_265 = or(_T_263, _T_264) @[el2_ifu_mem_ctl.scala 291:62]
|
|
io.ic_hit_f <= _T_265 @[el2_ifu_mem_ctl.scala 291:15]
|
|
node _T_266 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 292:47]
|
|
node _T_267 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 292:98]
|
|
node _T_268 = mux(_T_267, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf) @[el2_ifu_mem_ctl.scala 292:84]
|
|
node uncacheable_miss_in = mux(_T_266, uncacheable_miss_scnd_ff, _T_268) @[el2_ifu_mem_ctl.scala 292:32]
|
|
node _T_269 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 293:34]
|
|
node _T_270 = bits(sel_hold_imb, 0, 0) @[el2_ifu_mem_ctl.scala 293:72]
|
|
node _T_271 = mux(_T_270, imb_ff, io.ifc_fetch_addr_bf) @[el2_ifu_mem_ctl.scala 293:58]
|
|
node imb_in = mux(_T_269, imb_scnd_ff, _T_271) @[el2_ifu_mem_ctl.scala 293:19]
|
|
wire ifu_wr_cumulative_err_data : UInt<1>
|
|
ifu_wr_cumulative_err_data <= UInt<1>("h00")
|
|
node _T_272 = bits(imb_ff, 11, 5) @[el2_ifu_mem_ctl.scala 295:38]
|
|
node _T_273 = bits(imb_scnd_ff, 11, 5) @[el2_ifu_mem_ctl.scala 295:93]
|
|
node _T_274 = eq(_T_272, _T_273) @[el2_ifu_mem_ctl.scala 295:79]
|
|
node _T_275 = and(_T_274, scnd_miss_req) @[el2_ifu_mem_ctl.scala 295:135]
|
|
node _T_276 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 295:153]
|
|
node scnd_miss_index_match = and(_T_275, _T_276) @[el2_ifu_mem_ctl.scala 295:151]
|
|
wire way_status_mb_ff : UInt<1>
|
|
way_status_mb_ff <= UInt<1>("h00")
|
|
wire way_status_rep_new : UInt<1>
|
|
way_status_rep_new <= UInt<1>("h00")
|
|
node _T_277 = eq(scnd_miss_index_match, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 298:47]
|
|
node _T_278 = and(scnd_miss_req, _T_277) @[el2_ifu_mem_ctl.scala 298:45]
|
|
node _T_279 = bits(_T_278, 0, 0) @[el2_ifu_mem_ctl.scala 298:71]
|
|
node _T_280 = and(scnd_miss_req, scnd_miss_index_match) @[el2_ifu_mem_ctl.scala 299:26]
|
|
node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_mem_ctl.scala 299:52]
|
|
node _T_282 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 300:26]
|
|
node _T_283 = mux(_T_282, way_status_mb_ff, way_status) @[el2_ifu_mem_ctl.scala 300:12]
|
|
node _T_284 = mux(_T_281, way_status_rep_new, _T_283) @[el2_ifu_mem_ctl.scala 299:10]
|
|
node way_status_mb_in = mux(_T_279, way_status_mb_scnd_ff, _T_284) @[el2_ifu_mem_ctl.scala 298:29]
|
|
wire replace_way_mb_any : UInt<1>[2] @[el2_ifu_mem_ctl.scala 301:32]
|
|
wire tagv_mb_ff : UInt<2>
|
|
tagv_mb_ff <= UInt<1>("h00")
|
|
node _T_285 = bits(scnd_miss_req, 0, 0) @[el2_ifu_mem_ctl.scala 303:38]
|
|
node _T_286 = bits(scnd_miss_index_match, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_287 = mux(_T_286, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_288 = cat(replace_way_mb_any[1], replace_way_mb_any[0]) @[Cat.scala 29:58]
|
|
node _T_289 = and(_T_287, _T_288) @[el2_ifu_mem_ctl.scala 303:110]
|
|
node _T_290 = or(tagv_mb_scnd_ff, _T_289) @[el2_ifu_mem_ctl.scala 303:62]
|
|
node _T_291 = bits(miss_pending, 0, 0) @[el2_ifu_mem_ctl.scala 304:20]
|
|
node _T_292 = eq(reset_all_tags, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 304:80]
|
|
node _T_293 = bits(_T_292, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_294 = mux(_T_293, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_295 = and(io.ic_tag_valid, _T_294) @[el2_ifu_mem_ctl.scala 304:56]
|
|
node _T_296 = mux(_T_291, tagv_mb_ff, _T_295) @[el2_ifu_mem_ctl.scala 304:6]
|
|
node tagv_mb_in = mux(_T_285, _T_290, _T_296) @[el2_ifu_mem_ctl.scala 303:23]
|
|
wire scnd_miss_req_q : UInt<1>
|
|
scnd_miss_req_q <= UInt<1>("h00")
|
|
wire reset_ic_ff : UInt<1>
|
|
reset_ic_ff <= UInt<1>("h00")
|
|
node _T_297 = eq(scnd_miss_req_q, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 307:36]
|
|
node _T_298 = and(miss_pending, _T_297) @[el2_ifu_mem_ctl.scala 307:34]
|
|
node _T_299 = or(reset_all_tags, reset_ic_ff) @[el2_ifu_mem_ctl.scala 307:72]
|
|
node reset_ic_in = and(_T_298, _T_299) @[el2_ifu_mem_ctl.scala 307:53]
|
|
reg _T_300 : UInt, clock @[el2_ifu_mem_ctl.scala 308:25]
|
|
_T_300 <= reset_ic_in @[el2_ifu_mem_ctl.scala 308:25]
|
|
reset_ic_ff <= _T_300 @[el2_ifu_mem_ctl.scala 308:15]
|
|
reg fetch_uncacheable_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 309:37]
|
|
fetch_uncacheable_ff <= io.ifc_fetch_uncacheable_bf @[el2_ifu_mem_ctl.scala 309:37]
|
|
reg _T_301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 310:34]
|
|
_T_301 <= io.ifc_fetch_addr_bf @[el2_ifu_mem_ctl.scala 310:34]
|
|
ifu_fetch_addr_int_f <= _T_301 @[el2_ifu_mem_ctl.scala 310:24]
|
|
node vaddr_f = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 311:37]
|
|
reg _T_302 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 312:33]
|
|
_T_302 <= uncacheable_miss_in @[el2_ifu_mem_ctl.scala 312:33]
|
|
uncacheable_miss_ff <= _T_302 @[el2_ifu_mem_ctl.scala 312:23]
|
|
reg _T_303 : UInt, clock @[el2_ifu_mem_ctl.scala 313:20]
|
|
_T_303 <= imb_in @[el2_ifu_mem_ctl.scala 313:20]
|
|
imb_ff <= _T_303 @[el2_ifu_mem_ctl.scala 313:10]
|
|
wire miss_addr : UInt<26>
|
|
miss_addr <= UInt<1>("h00")
|
|
node _T_304 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 315:26]
|
|
node _T_305 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 315:47]
|
|
node _T_306 = bits(scnd_miss_req_q, 0, 0) @[el2_ifu_mem_ctl.scala 316:25]
|
|
node _T_307 = bits(imb_scnd_ff, 30, 5) @[el2_ifu_mem_ctl.scala 316:44]
|
|
node _T_308 = mux(_T_306, _T_307, miss_addr) @[el2_ifu_mem_ctl.scala 316:8]
|
|
node miss_addr_in = mux(_T_304, _T_305, _T_308) @[el2_ifu_mem_ctl.scala 315:25]
|
|
reg _T_309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 317:23]
|
|
_T_309 <= miss_addr_in @[el2_ifu_mem_ctl.scala 317:23]
|
|
miss_addr <= _T_309 @[el2_ifu_mem_ctl.scala 317:13]
|
|
reg _T_310 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 318:30]
|
|
_T_310 <= way_status_mb_in @[el2_ifu_mem_ctl.scala 318:30]
|
|
way_status_mb_ff <= _T_310 @[el2_ifu_mem_ctl.scala 318:20]
|
|
reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 319:24]
|
|
_T_311 <= tagv_mb_in @[el2_ifu_mem_ctl.scala 319:24]
|
|
tagv_mb_ff <= _T_311 @[el2_ifu_mem_ctl.scala 319:14]
|
|
wire stream_miss_f : UInt<1>
|
|
stream_miss_f <= UInt<1>("h00")
|
|
node _T_312 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 321:68]
|
|
node _T_313 = and(_T_312, flush_final_f) @[el2_ifu_mem_ctl.scala 321:87]
|
|
node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:55]
|
|
node _T_315 = and(io.ifc_fetch_req_bf, _T_314) @[el2_ifu_mem_ctl.scala 321:53]
|
|
node _T_316 = eq(stream_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 321:106]
|
|
node ifc_fetch_req_qual_bf = and(_T_315, _T_316) @[el2_ifu_mem_ctl.scala 321:104]
|
|
reg ifc_fetch_req_f_raw : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 322:36]
|
|
ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf @[el2_ifu_mem_ctl.scala 322:36]
|
|
node _T_317 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 323:44]
|
|
node _T_318 = and(ifc_fetch_req_f_raw, _T_317) @[el2_ifu_mem_ctl.scala 323:42]
|
|
ifc_fetch_req_f <= _T_318 @[el2_ifu_mem_ctl.scala 323:19]
|
|
reg _T_319 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 324:31]
|
|
_T_319 <= io.ifc_iccm_access_bf @[el2_ifu_mem_ctl.scala 324:31]
|
|
ifc_iccm_access_f <= _T_319 @[el2_ifu_mem_ctl.scala 324:21]
|
|
wire ifc_region_acc_fault_final_bf : UInt<1>
|
|
ifc_region_acc_fault_final_bf <= UInt<1>("h00")
|
|
reg _T_320 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 326:42]
|
|
_T_320 <= ifc_region_acc_fault_final_bf @[el2_ifu_mem_ctl.scala 326:42]
|
|
ifc_region_acc_fault_final_f <= _T_320 @[el2_ifu_mem_ctl.scala 326:32]
|
|
reg ifc_region_acc_fault_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 327:39]
|
|
ifc_region_acc_fault_f <= io.ifc_region_acc_fault_bf @[el2_ifu_mem_ctl.scala 327:39]
|
|
node ifu_ic_req_addr_f = cat(miss_addr, bus_rd_addr_count) @[Cat.scala 29:58]
|
|
node _T_321 = eq(miss_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 329:38]
|
|
node _T_322 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 329:68]
|
|
node _T_323 = or(_T_321, _T_322) @[el2_ifu_mem_ctl.scala 329:55]
|
|
node _T_324 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 329:103]
|
|
node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:84]
|
|
node _T_326 = and(_T_323, _T_325) @[el2_ifu_mem_ctl.scala 329:82]
|
|
node _T_327 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 329:119]
|
|
node _T_328 = or(_T_326, _T_327) @[el2_ifu_mem_ctl.scala 329:117]
|
|
io.ifu_ic_mb_empty <= _T_328 @[el2_ifu_mem_ctl.scala 329:22]
|
|
node _T_329 = eq(miss_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 330:40]
|
|
io.ifu_miss_state_idle <= _T_329 @[el2_ifu_mem_ctl.scala 330:26]
|
|
wire write_ic_16_bytes : UInt<1>
|
|
write_ic_16_bytes <= UInt<1>("h00")
|
|
wire reset_tag_valid_for_miss : UInt<1>
|
|
reset_tag_valid_for_miss <= UInt<1>("h00")
|
|
node _T_330 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 333:35]
|
|
node _T_331 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 333:57]
|
|
node _T_332 = and(_T_330, _T_331) @[el2_ifu_mem_ctl.scala 333:55]
|
|
node sel_mb_addr = or(_T_332, reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 333:79]
|
|
node _T_333 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 334:63]
|
|
node _T_334 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 334:119]
|
|
node _T_335 = cat(_T_333, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
|
|
node _T_336 = cat(_T_335, _T_334) @[Cat.scala 29:58]
|
|
node _T_337 = eq(sel_mb_addr, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 335:37]
|
|
node _T_338 = mux(sel_mb_addr, _T_336, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_339 = mux(_T_337, io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_340 = or(_T_338, _T_339) @[Mux.scala 27:72]
|
|
wire ifu_ic_rw_int_addr : UInt<31> @[Mux.scala 27:72]
|
|
ifu_ic_rw_int_addr <= _T_340 @[Mux.scala 27:72]
|
|
wire bus_ifu_wr_en_ff_q : UInt<1>
|
|
bus_ifu_wr_en_ff_q <= UInt<1>("h00")
|
|
node _T_341 = and(miss_pending, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 337:41]
|
|
node _T_342 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 337:63]
|
|
node _T_343 = and(_T_341, _T_342) @[el2_ifu_mem_ctl.scala 337:61]
|
|
node _T_344 = and(_T_343, last_beat) @[el2_ifu_mem_ctl.scala 337:84]
|
|
node sel_mb_status_addr = and(_T_344, bus_ifu_wr_en_ff_q) @[el2_ifu_mem_ctl.scala 337:96]
|
|
node _T_345 = bits(imb_ff, 30, 5) @[el2_ifu_mem_ctl.scala 338:62]
|
|
node _T_346 = bits(imb_ff, 1, 0) @[el2_ifu_mem_ctl.scala 338:116]
|
|
node _T_347 = cat(_T_345, ic_wr_addr_bits_hi_3) @[Cat.scala 29:58]
|
|
node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58]
|
|
node ifu_status_wr_addr = mux(sel_mb_status_addr, _T_348, ifu_fetch_addr_int_f) @[el2_ifu_mem_ctl.scala 338:31]
|
|
io.ic_rw_addr <= ifu_ic_rw_int_addr @[el2_ifu_mem_ctl.scala 339:17]
|
|
reg _T_349 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 340:51]
|
|
_T_349 <= sel_mb_addr @[el2_ifu_mem_ctl.scala 340:51]
|
|
sel_mb_addr_ff <= _T_349 @[el2_ifu_mem_ctl.scala 340:18]
|
|
wire ifu_bus_rdata_ff : UInt<64>
|
|
ifu_bus_rdata_ff <= UInt<1>("h00")
|
|
wire ic_miss_buff_half : UInt<64>
|
|
ic_miss_buff_half <= UInt<1>("h00")
|
|
wire _T_350 : UInt<1>[35] @[el2_lib.scala 363:18]
|
|
wire _T_351 : UInt<1>[35] @[el2_lib.scala 364:18]
|
|
wire _T_352 : UInt<1>[35] @[el2_lib.scala 365:18]
|
|
wire _T_353 : UInt<1>[31] @[el2_lib.scala 366:18]
|
|
wire _T_354 : UInt<1>[31] @[el2_lib.scala 367:18]
|
|
wire _T_355 : UInt<1>[31] @[el2_lib.scala 368:18]
|
|
wire _T_356 : UInt<1>[7] @[el2_lib.scala 369:18]
|
|
node _T_357 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 376:36]
|
|
_T_350[0] <= _T_357 @[el2_lib.scala 376:30]
|
|
node _T_358 = bits(ifu_bus_rdata_ff, 0, 0) @[el2_lib.scala 377:36]
|
|
_T_351[0] <= _T_358 @[el2_lib.scala 377:30]
|
|
node _T_359 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 376:36]
|
|
_T_350[1] <= _T_359 @[el2_lib.scala 376:30]
|
|
node _T_360 = bits(ifu_bus_rdata_ff, 1, 1) @[el2_lib.scala 378:36]
|
|
_T_352[0] <= _T_360 @[el2_lib.scala 378:30]
|
|
node _T_361 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 377:36]
|
|
_T_351[1] <= _T_361 @[el2_lib.scala 377:30]
|
|
node _T_362 = bits(ifu_bus_rdata_ff, 2, 2) @[el2_lib.scala 378:36]
|
|
_T_352[1] <= _T_362 @[el2_lib.scala 378:30]
|
|
node _T_363 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 376:36]
|
|
_T_350[2] <= _T_363 @[el2_lib.scala 376:30]
|
|
node _T_364 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 377:36]
|
|
_T_351[2] <= _T_364 @[el2_lib.scala 377:30]
|
|
node _T_365 = bits(ifu_bus_rdata_ff, 3, 3) @[el2_lib.scala 378:36]
|
|
_T_352[2] <= _T_365 @[el2_lib.scala 378:30]
|
|
node _T_366 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 376:36]
|
|
_T_350[3] <= _T_366 @[el2_lib.scala 376:30]
|
|
node _T_367 = bits(ifu_bus_rdata_ff, 4, 4) @[el2_lib.scala 379:36]
|
|
_T_353[0] <= _T_367 @[el2_lib.scala 379:30]
|
|
node _T_368 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 377:36]
|
|
_T_351[3] <= _T_368 @[el2_lib.scala 377:30]
|
|
node _T_369 = bits(ifu_bus_rdata_ff, 5, 5) @[el2_lib.scala 379:36]
|
|
_T_353[1] <= _T_369 @[el2_lib.scala 379:30]
|
|
node _T_370 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 376:36]
|
|
_T_350[4] <= _T_370 @[el2_lib.scala 376:30]
|
|
node _T_371 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 377:36]
|
|
_T_351[4] <= _T_371 @[el2_lib.scala 377:30]
|
|
node _T_372 = bits(ifu_bus_rdata_ff, 6, 6) @[el2_lib.scala 379:36]
|
|
_T_353[2] <= _T_372 @[el2_lib.scala 379:30]
|
|
node _T_373 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 378:36]
|
|
_T_352[3] <= _T_373 @[el2_lib.scala 378:30]
|
|
node _T_374 = bits(ifu_bus_rdata_ff, 7, 7) @[el2_lib.scala 379:36]
|
|
_T_353[3] <= _T_374 @[el2_lib.scala 379:30]
|
|
node _T_375 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 376:36]
|
|
_T_350[5] <= _T_375 @[el2_lib.scala 376:30]
|
|
node _T_376 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 378:36]
|
|
_T_352[4] <= _T_376 @[el2_lib.scala 378:30]
|
|
node _T_377 = bits(ifu_bus_rdata_ff, 8, 8) @[el2_lib.scala 379:36]
|
|
_T_353[4] <= _T_377 @[el2_lib.scala 379:30]
|
|
node _T_378 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 377:36]
|
|
_T_351[5] <= _T_378 @[el2_lib.scala 377:30]
|
|
node _T_379 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 378:36]
|
|
_T_352[5] <= _T_379 @[el2_lib.scala 378:30]
|
|
node _T_380 = bits(ifu_bus_rdata_ff, 9, 9) @[el2_lib.scala 379:36]
|
|
_T_353[5] <= _T_380 @[el2_lib.scala 379:30]
|
|
node _T_381 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 376:36]
|
|
_T_350[6] <= _T_381 @[el2_lib.scala 376:30]
|
|
node _T_382 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 377:36]
|
|
_T_351[6] <= _T_382 @[el2_lib.scala 377:30]
|
|
node _T_383 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 378:36]
|
|
_T_352[6] <= _T_383 @[el2_lib.scala 378:30]
|
|
node _T_384 = bits(ifu_bus_rdata_ff, 10, 10) @[el2_lib.scala 379:36]
|
|
_T_353[6] <= _T_384 @[el2_lib.scala 379:30]
|
|
node _T_385 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 376:36]
|
|
_T_350[7] <= _T_385 @[el2_lib.scala 376:30]
|
|
node _T_386 = bits(ifu_bus_rdata_ff, 11, 11) @[el2_lib.scala 380:36]
|
|
_T_354[0] <= _T_386 @[el2_lib.scala 380:30]
|
|
node _T_387 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 377:36]
|
|
_T_351[7] <= _T_387 @[el2_lib.scala 377:30]
|
|
node _T_388 = bits(ifu_bus_rdata_ff, 12, 12) @[el2_lib.scala 380:36]
|
|
_T_354[1] <= _T_388 @[el2_lib.scala 380:30]
|
|
node _T_389 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 376:36]
|
|
_T_350[8] <= _T_389 @[el2_lib.scala 376:30]
|
|
node _T_390 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 377:36]
|
|
_T_351[8] <= _T_390 @[el2_lib.scala 377:30]
|
|
node _T_391 = bits(ifu_bus_rdata_ff, 13, 13) @[el2_lib.scala 380:36]
|
|
_T_354[2] <= _T_391 @[el2_lib.scala 380:30]
|
|
node _T_392 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 378:36]
|
|
_T_352[7] <= _T_392 @[el2_lib.scala 378:30]
|
|
node _T_393 = bits(ifu_bus_rdata_ff, 14, 14) @[el2_lib.scala 380:36]
|
|
_T_354[3] <= _T_393 @[el2_lib.scala 380:30]
|
|
node _T_394 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 376:36]
|
|
_T_350[9] <= _T_394 @[el2_lib.scala 376:30]
|
|
node _T_395 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 378:36]
|
|
_T_352[8] <= _T_395 @[el2_lib.scala 378:30]
|
|
node _T_396 = bits(ifu_bus_rdata_ff, 15, 15) @[el2_lib.scala 380:36]
|
|
_T_354[4] <= _T_396 @[el2_lib.scala 380:30]
|
|
node _T_397 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 377:36]
|
|
_T_351[9] <= _T_397 @[el2_lib.scala 377:30]
|
|
node _T_398 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 378:36]
|
|
_T_352[9] <= _T_398 @[el2_lib.scala 378:30]
|
|
node _T_399 = bits(ifu_bus_rdata_ff, 16, 16) @[el2_lib.scala 380:36]
|
|
_T_354[5] <= _T_399 @[el2_lib.scala 380:30]
|
|
node _T_400 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 376:36]
|
|
_T_350[10] <= _T_400 @[el2_lib.scala 376:30]
|
|
node _T_401 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 377:36]
|
|
_T_351[10] <= _T_401 @[el2_lib.scala 377:30]
|
|
node _T_402 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 378:36]
|
|
_T_352[10] <= _T_402 @[el2_lib.scala 378:30]
|
|
node _T_403 = bits(ifu_bus_rdata_ff, 17, 17) @[el2_lib.scala 380:36]
|
|
_T_354[6] <= _T_403 @[el2_lib.scala 380:30]
|
|
node _T_404 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 379:36]
|
|
_T_353[7] <= _T_404 @[el2_lib.scala 379:30]
|
|
node _T_405 = bits(ifu_bus_rdata_ff, 18, 18) @[el2_lib.scala 380:36]
|
|
_T_354[7] <= _T_405 @[el2_lib.scala 380:30]
|
|
node _T_406 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 376:36]
|
|
_T_350[11] <= _T_406 @[el2_lib.scala 376:30]
|
|
node _T_407 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 379:36]
|
|
_T_353[8] <= _T_407 @[el2_lib.scala 379:30]
|
|
node _T_408 = bits(ifu_bus_rdata_ff, 19, 19) @[el2_lib.scala 380:36]
|
|
_T_354[8] <= _T_408 @[el2_lib.scala 380:30]
|
|
node _T_409 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 377:36]
|
|
_T_351[11] <= _T_409 @[el2_lib.scala 377:30]
|
|
node _T_410 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 379:36]
|
|
_T_353[9] <= _T_410 @[el2_lib.scala 379:30]
|
|
node _T_411 = bits(ifu_bus_rdata_ff, 20, 20) @[el2_lib.scala 380:36]
|
|
_T_354[9] <= _T_411 @[el2_lib.scala 380:30]
|
|
node _T_412 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 376:36]
|
|
_T_350[12] <= _T_412 @[el2_lib.scala 376:30]
|
|
node _T_413 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 377:36]
|
|
_T_351[12] <= _T_413 @[el2_lib.scala 377:30]
|
|
node _T_414 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 379:36]
|
|
_T_353[10] <= _T_414 @[el2_lib.scala 379:30]
|
|
node _T_415 = bits(ifu_bus_rdata_ff, 21, 21) @[el2_lib.scala 380:36]
|
|
_T_354[10] <= _T_415 @[el2_lib.scala 380:30]
|
|
node _T_416 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 378:36]
|
|
_T_352[11] <= _T_416 @[el2_lib.scala 378:30]
|
|
node _T_417 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 379:36]
|
|
_T_353[11] <= _T_417 @[el2_lib.scala 379:30]
|
|
node _T_418 = bits(ifu_bus_rdata_ff, 22, 22) @[el2_lib.scala 380:36]
|
|
_T_354[11] <= _T_418 @[el2_lib.scala 380:30]
|
|
node _T_419 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 376:36]
|
|
_T_350[13] <= _T_419 @[el2_lib.scala 376:30]
|
|
node _T_420 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 378:36]
|
|
_T_352[12] <= _T_420 @[el2_lib.scala 378:30]
|
|
node _T_421 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 379:36]
|
|
_T_353[12] <= _T_421 @[el2_lib.scala 379:30]
|
|
node _T_422 = bits(ifu_bus_rdata_ff, 23, 23) @[el2_lib.scala 380:36]
|
|
_T_354[12] <= _T_422 @[el2_lib.scala 380:30]
|
|
node _T_423 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 377:36]
|
|
_T_351[13] <= _T_423 @[el2_lib.scala 377:30]
|
|
node _T_424 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 378:36]
|
|
_T_352[13] <= _T_424 @[el2_lib.scala 378:30]
|
|
node _T_425 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 379:36]
|
|
_T_353[13] <= _T_425 @[el2_lib.scala 379:30]
|
|
node _T_426 = bits(ifu_bus_rdata_ff, 24, 24) @[el2_lib.scala 380:36]
|
|
_T_354[13] <= _T_426 @[el2_lib.scala 380:30]
|
|
node _T_427 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 376:36]
|
|
_T_350[14] <= _T_427 @[el2_lib.scala 376:30]
|
|
node _T_428 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 377:36]
|
|
_T_351[14] <= _T_428 @[el2_lib.scala 377:30]
|
|
node _T_429 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 378:36]
|
|
_T_352[14] <= _T_429 @[el2_lib.scala 378:30]
|
|
node _T_430 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 379:36]
|
|
_T_353[14] <= _T_430 @[el2_lib.scala 379:30]
|
|
node _T_431 = bits(ifu_bus_rdata_ff, 25, 25) @[el2_lib.scala 380:36]
|
|
_T_354[14] <= _T_431 @[el2_lib.scala 380:30]
|
|
node _T_432 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 376:36]
|
|
_T_350[15] <= _T_432 @[el2_lib.scala 376:30]
|
|
node _T_433 = bits(ifu_bus_rdata_ff, 26, 26) @[el2_lib.scala 381:36]
|
|
_T_355[0] <= _T_433 @[el2_lib.scala 381:30]
|
|
node _T_434 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 377:36]
|
|
_T_351[15] <= _T_434 @[el2_lib.scala 377:30]
|
|
node _T_435 = bits(ifu_bus_rdata_ff, 27, 27) @[el2_lib.scala 381:36]
|
|
_T_355[1] <= _T_435 @[el2_lib.scala 381:30]
|
|
node _T_436 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 376:36]
|
|
_T_350[16] <= _T_436 @[el2_lib.scala 376:30]
|
|
node _T_437 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 377:36]
|
|
_T_351[16] <= _T_437 @[el2_lib.scala 377:30]
|
|
node _T_438 = bits(ifu_bus_rdata_ff, 28, 28) @[el2_lib.scala 381:36]
|
|
_T_355[2] <= _T_438 @[el2_lib.scala 381:30]
|
|
node _T_439 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 378:36]
|
|
_T_352[15] <= _T_439 @[el2_lib.scala 378:30]
|
|
node _T_440 = bits(ifu_bus_rdata_ff, 29, 29) @[el2_lib.scala 381:36]
|
|
_T_355[3] <= _T_440 @[el2_lib.scala 381:30]
|
|
node _T_441 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 376:36]
|
|
_T_350[17] <= _T_441 @[el2_lib.scala 376:30]
|
|
node _T_442 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 378:36]
|
|
_T_352[16] <= _T_442 @[el2_lib.scala 378:30]
|
|
node _T_443 = bits(ifu_bus_rdata_ff, 30, 30) @[el2_lib.scala 381:36]
|
|
_T_355[4] <= _T_443 @[el2_lib.scala 381:30]
|
|
node _T_444 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 377:36]
|
|
_T_351[17] <= _T_444 @[el2_lib.scala 377:30]
|
|
node _T_445 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 378:36]
|
|
_T_352[17] <= _T_445 @[el2_lib.scala 378:30]
|
|
node _T_446 = bits(ifu_bus_rdata_ff, 31, 31) @[el2_lib.scala 381:36]
|
|
_T_355[5] <= _T_446 @[el2_lib.scala 381:30]
|
|
node _T_447 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 376:36]
|
|
_T_350[18] <= _T_447 @[el2_lib.scala 376:30]
|
|
node _T_448 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 377:36]
|
|
_T_351[18] <= _T_448 @[el2_lib.scala 377:30]
|
|
node _T_449 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 378:36]
|
|
_T_352[18] <= _T_449 @[el2_lib.scala 378:30]
|
|
node _T_450 = bits(ifu_bus_rdata_ff, 32, 32) @[el2_lib.scala 381:36]
|
|
_T_355[6] <= _T_450 @[el2_lib.scala 381:30]
|
|
node _T_451 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 379:36]
|
|
_T_353[15] <= _T_451 @[el2_lib.scala 379:30]
|
|
node _T_452 = bits(ifu_bus_rdata_ff, 33, 33) @[el2_lib.scala 381:36]
|
|
_T_355[7] <= _T_452 @[el2_lib.scala 381:30]
|
|
node _T_453 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 376:36]
|
|
_T_350[19] <= _T_453 @[el2_lib.scala 376:30]
|
|
node _T_454 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 379:36]
|
|
_T_353[16] <= _T_454 @[el2_lib.scala 379:30]
|
|
node _T_455 = bits(ifu_bus_rdata_ff, 34, 34) @[el2_lib.scala 381:36]
|
|
_T_355[8] <= _T_455 @[el2_lib.scala 381:30]
|
|
node _T_456 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 377:36]
|
|
_T_351[19] <= _T_456 @[el2_lib.scala 377:30]
|
|
node _T_457 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 379:36]
|
|
_T_353[17] <= _T_457 @[el2_lib.scala 379:30]
|
|
node _T_458 = bits(ifu_bus_rdata_ff, 35, 35) @[el2_lib.scala 381:36]
|
|
_T_355[9] <= _T_458 @[el2_lib.scala 381:30]
|
|
node _T_459 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 376:36]
|
|
_T_350[20] <= _T_459 @[el2_lib.scala 376:30]
|
|
node _T_460 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 377:36]
|
|
_T_351[20] <= _T_460 @[el2_lib.scala 377:30]
|
|
node _T_461 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 379:36]
|
|
_T_353[18] <= _T_461 @[el2_lib.scala 379:30]
|
|
node _T_462 = bits(ifu_bus_rdata_ff, 36, 36) @[el2_lib.scala 381:36]
|
|
_T_355[10] <= _T_462 @[el2_lib.scala 381:30]
|
|
node _T_463 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 378:36]
|
|
_T_352[19] <= _T_463 @[el2_lib.scala 378:30]
|
|
node _T_464 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 379:36]
|
|
_T_353[19] <= _T_464 @[el2_lib.scala 379:30]
|
|
node _T_465 = bits(ifu_bus_rdata_ff, 37, 37) @[el2_lib.scala 381:36]
|
|
_T_355[11] <= _T_465 @[el2_lib.scala 381:30]
|
|
node _T_466 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 376:36]
|
|
_T_350[21] <= _T_466 @[el2_lib.scala 376:30]
|
|
node _T_467 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 378:36]
|
|
_T_352[20] <= _T_467 @[el2_lib.scala 378:30]
|
|
node _T_468 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 379:36]
|
|
_T_353[20] <= _T_468 @[el2_lib.scala 379:30]
|
|
node _T_469 = bits(ifu_bus_rdata_ff, 38, 38) @[el2_lib.scala 381:36]
|
|
_T_355[12] <= _T_469 @[el2_lib.scala 381:30]
|
|
node _T_470 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 377:36]
|
|
_T_351[21] <= _T_470 @[el2_lib.scala 377:30]
|
|
node _T_471 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 378:36]
|
|
_T_352[21] <= _T_471 @[el2_lib.scala 378:30]
|
|
node _T_472 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 379:36]
|
|
_T_353[21] <= _T_472 @[el2_lib.scala 379:30]
|
|
node _T_473 = bits(ifu_bus_rdata_ff, 39, 39) @[el2_lib.scala 381:36]
|
|
_T_355[13] <= _T_473 @[el2_lib.scala 381:30]
|
|
node _T_474 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 376:36]
|
|
_T_350[22] <= _T_474 @[el2_lib.scala 376:30]
|
|
node _T_475 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 377:36]
|
|
_T_351[22] <= _T_475 @[el2_lib.scala 377:30]
|
|
node _T_476 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 378:36]
|
|
_T_352[22] <= _T_476 @[el2_lib.scala 378:30]
|
|
node _T_477 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 379:36]
|
|
_T_353[22] <= _T_477 @[el2_lib.scala 379:30]
|
|
node _T_478 = bits(ifu_bus_rdata_ff, 40, 40) @[el2_lib.scala 381:36]
|
|
_T_355[14] <= _T_478 @[el2_lib.scala 381:30]
|
|
node _T_479 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 380:36]
|
|
_T_354[15] <= _T_479 @[el2_lib.scala 380:30]
|
|
node _T_480 = bits(ifu_bus_rdata_ff, 41, 41) @[el2_lib.scala 381:36]
|
|
_T_355[15] <= _T_480 @[el2_lib.scala 381:30]
|
|
node _T_481 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 376:36]
|
|
_T_350[23] <= _T_481 @[el2_lib.scala 376:30]
|
|
node _T_482 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 380:36]
|
|
_T_354[16] <= _T_482 @[el2_lib.scala 380:30]
|
|
node _T_483 = bits(ifu_bus_rdata_ff, 42, 42) @[el2_lib.scala 381:36]
|
|
_T_355[16] <= _T_483 @[el2_lib.scala 381:30]
|
|
node _T_484 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 377:36]
|
|
_T_351[23] <= _T_484 @[el2_lib.scala 377:30]
|
|
node _T_485 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 380:36]
|
|
_T_354[17] <= _T_485 @[el2_lib.scala 380:30]
|
|
node _T_486 = bits(ifu_bus_rdata_ff, 43, 43) @[el2_lib.scala 381:36]
|
|
_T_355[17] <= _T_486 @[el2_lib.scala 381:30]
|
|
node _T_487 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 376:36]
|
|
_T_350[24] <= _T_487 @[el2_lib.scala 376:30]
|
|
node _T_488 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 377:36]
|
|
_T_351[24] <= _T_488 @[el2_lib.scala 377:30]
|
|
node _T_489 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 380:36]
|
|
_T_354[18] <= _T_489 @[el2_lib.scala 380:30]
|
|
node _T_490 = bits(ifu_bus_rdata_ff, 44, 44) @[el2_lib.scala 381:36]
|
|
_T_355[18] <= _T_490 @[el2_lib.scala 381:30]
|
|
node _T_491 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 378:36]
|
|
_T_352[23] <= _T_491 @[el2_lib.scala 378:30]
|
|
node _T_492 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 380:36]
|
|
_T_354[19] <= _T_492 @[el2_lib.scala 380:30]
|
|
node _T_493 = bits(ifu_bus_rdata_ff, 45, 45) @[el2_lib.scala 381:36]
|
|
_T_355[19] <= _T_493 @[el2_lib.scala 381:30]
|
|
node _T_494 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 376:36]
|
|
_T_350[25] <= _T_494 @[el2_lib.scala 376:30]
|
|
node _T_495 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 378:36]
|
|
_T_352[24] <= _T_495 @[el2_lib.scala 378:30]
|
|
node _T_496 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 380:36]
|
|
_T_354[20] <= _T_496 @[el2_lib.scala 380:30]
|
|
node _T_497 = bits(ifu_bus_rdata_ff, 46, 46) @[el2_lib.scala 381:36]
|
|
_T_355[20] <= _T_497 @[el2_lib.scala 381:30]
|
|
node _T_498 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 377:36]
|
|
_T_351[25] <= _T_498 @[el2_lib.scala 377:30]
|
|
node _T_499 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 378:36]
|
|
_T_352[25] <= _T_499 @[el2_lib.scala 378:30]
|
|
node _T_500 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 380:36]
|
|
_T_354[21] <= _T_500 @[el2_lib.scala 380:30]
|
|
node _T_501 = bits(ifu_bus_rdata_ff, 47, 47) @[el2_lib.scala 381:36]
|
|
_T_355[21] <= _T_501 @[el2_lib.scala 381:30]
|
|
node _T_502 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 376:36]
|
|
_T_350[26] <= _T_502 @[el2_lib.scala 376:30]
|
|
node _T_503 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 377:36]
|
|
_T_351[26] <= _T_503 @[el2_lib.scala 377:30]
|
|
node _T_504 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 378:36]
|
|
_T_352[26] <= _T_504 @[el2_lib.scala 378:30]
|
|
node _T_505 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 380:36]
|
|
_T_354[22] <= _T_505 @[el2_lib.scala 380:30]
|
|
node _T_506 = bits(ifu_bus_rdata_ff, 48, 48) @[el2_lib.scala 381:36]
|
|
_T_355[22] <= _T_506 @[el2_lib.scala 381:30]
|
|
node _T_507 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 379:36]
|
|
_T_353[23] <= _T_507 @[el2_lib.scala 379:30]
|
|
node _T_508 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 380:36]
|
|
_T_354[23] <= _T_508 @[el2_lib.scala 380:30]
|
|
node _T_509 = bits(ifu_bus_rdata_ff, 49, 49) @[el2_lib.scala 381:36]
|
|
_T_355[23] <= _T_509 @[el2_lib.scala 381:30]
|
|
node _T_510 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 376:36]
|
|
_T_350[27] <= _T_510 @[el2_lib.scala 376:30]
|
|
node _T_511 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 379:36]
|
|
_T_353[24] <= _T_511 @[el2_lib.scala 379:30]
|
|
node _T_512 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 380:36]
|
|
_T_354[24] <= _T_512 @[el2_lib.scala 380:30]
|
|
node _T_513 = bits(ifu_bus_rdata_ff, 50, 50) @[el2_lib.scala 381:36]
|
|
_T_355[24] <= _T_513 @[el2_lib.scala 381:30]
|
|
node _T_514 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 377:36]
|
|
_T_351[27] <= _T_514 @[el2_lib.scala 377:30]
|
|
node _T_515 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 379:36]
|
|
_T_353[25] <= _T_515 @[el2_lib.scala 379:30]
|
|
node _T_516 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 380:36]
|
|
_T_354[25] <= _T_516 @[el2_lib.scala 380:30]
|
|
node _T_517 = bits(ifu_bus_rdata_ff, 51, 51) @[el2_lib.scala 381:36]
|
|
_T_355[25] <= _T_517 @[el2_lib.scala 381:30]
|
|
node _T_518 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 376:36]
|
|
_T_350[28] <= _T_518 @[el2_lib.scala 376:30]
|
|
node _T_519 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 377:36]
|
|
_T_351[28] <= _T_519 @[el2_lib.scala 377:30]
|
|
node _T_520 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 379:36]
|
|
_T_353[26] <= _T_520 @[el2_lib.scala 379:30]
|
|
node _T_521 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 380:36]
|
|
_T_354[26] <= _T_521 @[el2_lib.scala 380:30]
|
|
node _T_522 = bits(ifu_bus_rdata_ff, 52, 52) @[el2_lib.scala 381:36]
|
|
_T_355[26] <= _T_522 @[el2_lib.scala 381:30]
|
|
node _T_523 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 378:36]
|
|
_T_352[27] <= _T_523 @[el2_lib.scala 378:30]
|
|
node _T_524 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 379:36]
|
|
_T_353[27] <= _T_524 @[el2_lib.scala 379:30]
|
|
node _T_525 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 380:36]
|
|
_T_354[27] <= _T_525 @[el2_lib.scala 380:30]
|
|
node _T_526 = bits(ifu_bus_rdata_ff, 53, 53) @[el2_lib.scala 381:36]
|
|
_T_355[27] <= _T_526 @[el2_lib.scala 381:30]
|
|
node _T_527 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 376:36]
|
|
_T_350[29] <= _T_527 @[el2_lib.scala 376:30]
|
|
node _T_528 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 378:36]
|
|
_T_352[28] <= _T_528 @[el2_lib.scala 378:30]
|
|
node _T_529 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 379:36]
|
|
_T_353[28] <= _T_529 @[el2_lib.scala 379:30]
|
|
node _T_530 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 380:36]
|
|
_T_354[28] <= _T_530 @[el2_lib.scala 380:30]
|
|
node _T_531 = bits(ifu_bus_rdata_ff, 54, 54) @[el2_lib.scala 381:36]
|
|
_T_355[28] <= _T_531 @[el2_lib.scala 381:30]
|
|
node _T_532 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 377:36]
|
|
_T_351[29] <= _T_532 @[el2_lib.scala 377:30]
|
|
node _T_533 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 378:36]
|
|
_T_352[29] <= _T_533 @[el2_lib.scala 378:30]
|
|
node _T_534 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 379:36]
|
|
_T_353[29] <= _T_534 @[el2_lib.scala 379:30]
|
|
node _T_535 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 380:36]
|
|
_T_354[29] <= _T_535 @[el2_lib.scala 380:30]
|
|
node _T_536 = bits(ifu_bus_rdata_ff, 55, 55) @[el2_lib.scala 381:36]
|
|
_T_355[29] <= _T_536 @[el2_lib.scala 381:30]
|
|
node _T_537 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 376:36]
|
|
_T_350[30] <= _T_537 @[el2_lib.scala 376:30]
|
|
node _T_538 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 377:36]
|
|
_T_351[30] <= _T_538 @[el2_lib.scala 377:30]
|
|
node _T_539 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 378:36]
|
|
_T_352[30] <= _T_539 @[el2_lib.scala 378:30]
|
|
node _T_540 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 379:36]
|
|
_T_353[30] <= _T_540 @[el2_lib.scala 379:30]
|
|
node _T_541 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 380:36]
|
|
_T_354[30] <= _T_541 @[el2_lib.scala 380:30]
|
|
node _T_542 = bits(ifu_bus_rdata_ff, 56, 56) @[el2_lib.scala 381:36]
|
|
_T_355[30] <= _T_542 @[el2_lib.scala 381:30]
|
|
node _T_543 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 376:36]
|
|
_T_350[31] <= _T_543 @[el2_lib.scala 376:30]
|
|
node _T_544 = bits(ifu_bus_rdata_ff, 57, 57) @[el2_lib.scala 382:36]
|
|
_T_356[0] <= _T_544 @[el2_lib.scala 382:30]
|
|
node _T_545 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 377:36]
|
|
_T_351[31] <= _T_545 @[el2_lib.scala 377:30]
|
|
node _T_546 = bits(ifu_bus_rdata_ff, 58, 58) @[el2_lib.scala 382:36]
|
|
_T_356[1] <= _T_546 @[el2_lib.scala 382:30]
|
|
node _T_547 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 376:36]
|
|
_T_350[32] <= _T_547 @[el2_lib.scala 376:30]
|
|
node _T_548 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 377:36]
|
|
_T_351[32] <= _T_548 @[el2_lib.scala 377:30]
|
|
node _T_549 = bits(ifu_bus_rdata_ff, 59, 59) @[el2_lib.scala 382:36]
|
|
_T_356[2] <= _T_549 @[el2_lib.scala 382:30]
|
|
node _T_550 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 378:36]
|
|
_T_352[31] <= _T_550 @[el2_lib.scala 378:30]
|
|
node _T_551 = bits(ifu_bus_rdata_ff, 60, 60) @[el2_lib.scala 382:36]
|
|
_T_356[3] <= _T_551 @[el2_lib.scala 382:30]
|
|
node _T_552 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 376:36]
|
|
_T_350[33] <= _T_552 @[el2_lib.scala 376:30]
|
|
node _T_553 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 378:36]
|
|
_T_352[32] <= _T_553 @[el2_lib.scala 378:30]
|
|
node _T_554 = bits(ifu_bus_rdata_ff, 61, 61) @[el2_lib.scala 382:36]
|
|
_T_356[4] <= _T_554 @[el2_lib.scala 382:30]
|
|
node _T_555 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 377:36]
|
|
_T_351[33] <= _T_555 @[el2_lib.scala 377:30]
|
|
node _T_556 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 378:36]
|
|
_T_352[33] <= _T_556 @[el2_lib.scala 378:30]
|
|
node _T_557 = bits(ifu_bus_rdata_ff, 62, 62) @[el2_lib.scala 382:36]
|
|
_T_356[5] <= _T_557 @[el2_lib.scala 382:30]
|
|
node _T_558 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 376:36]
|
|
_T_350[34] <= _T_558 @[el2_lib.scala 376:30]
|
|
node _T_559 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 377:36]
|
|
_T_351[34] <= _T_559 @[el2_lib.scala 377:30]
|
|
node _T_560 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 378:36]
|
|
_T_352[34] <= _T_560 @[el2_lib.scala 378:30]
|
|
node _T_561 = bits(ifu_bus_rdata_ff, 63, 63) @[el2_lib.scala 382:36]
|
|
_T_356[6] <= _T_561 @[el2_lib.scala 382:30]
|
|
node _T_562 = cat(_T_356[2], _T_356[1]) @[el2_lib.scala 384:13]
|
|
node _T_563 = cat(_T_562, _T_356[0]) @[el2_lib.scala 384:13]
|
|
node _T_564 = cat(_T_356[4], _T_356[3]) @[el2_lib.scala 384:13]
|
|
node _T_565 = cat(_T_356[6], _T_356[5]) @[el2_lib.scala 384:13]
|
|
node _T_566 = cat(_T_565, _T_564) @[el2_lib.scala 384:13]
|
|
node _T_567 = cat(_T_566, _T_563) @[el2_lib.scala 384:13]
|
|
node _T_568 = xorr(_T_567) @[el2_lib.scala 384:20]
|
|
node _T_569 = cat(_T_355[2], _T_355[1]) @[el2_lib.scala 384:30]
|
|
node _T_570 = cat(_T_569, _T_355[0]) @[el2_lib.scala 384:30]
|
|
node _T_571 = cat(_T_355[4], _T_355[3]) @[el2_lib.scala 384:30]
|
|
node _T_572 = cat(_T_355[6], _T_355[5]) @[el2_lib.scala 384:30]
|
|
node _T_573 = cat(_T_572, _T_571) @[el2_lib.scala 384:30]
|
|
node _T_574 = cat(_T_573, _T_570) @[el2_lib.scala 384:30]
|
|
node _T_575 = cat(_T_355[8], _T_355[7]) @[el2_lib.scala 384:30]
|
|
node _T_576 = cat(_T_355[10], _T_355[9]) @[el2_lib.scala 384:30]
|
|
node _T_577 = cat(_T_576, _T_575) @[el2_lib.scala 384:30]
|
|
node _T_578 = cat(_T_355[12], _T_355[11]) @[el2_lib.scala 384:30]
|
|
node _T_579 = cat(_T_355[14], _T_355[13]) @[el2_lib.scala 384:30]
|
|
node _T_580 = cat(_T_579, _T_578) @[el2_lib.scala 384:30]
|
|
node _T_581 = cat(_T_580, _T_577) @[el2_lib.scala 384:30]
|
|
node _T_582 = cat(_T_581, _T_574) @[el2_lib.scala 384:30]
|
|
node _T_583 = cat(_T_355[16], _T_355[15]) @[el2_lib.scala 384:30]
|
|
node _T_584 = cat(_T_355[18], _T_355[17]) @[el2_lib.scala 384:30]
|
|
node _T_585 = cat(_T_584, _T_583) @[el2_lib.scala 384:30]
|
|
node _T_586 = cat(_T_355[20], _T_355[19]) @[el2_lib.scala 384:30]
|
|
node _T_587 = cat(_T_355[22], _T_355[21]) @[el2_lib.scala 384:30]
|
|
node _T_588 = cat(_T_587, _T_586) @[el2_lib.scala 384:30]
|
|
node _T_589 = cat(_T_588, _T_585) @[el2_lib.scala 384:30]
|
|
node _T_590 = cat(_T_355[24], _T_355[23]) @[el2_lib.scala 384:30]
|
|
node _T_591 = cat(_T_355[26], _T_355[25]) @[el2_lib.scala 384:30]
|
|
node _T_592 = cat(_T_591, _T_590) @[el2_lib.scala 384:30]
|
|
node _T_593 = cat(_T_355[28], _T_355[27]) @[el2_lib.scala 384:30]
|
|
node _T_594 = cat(_T_355[30], _T_355[29]) @[el2_lib.scala 384:30]
|
|
node _T_595 = cat(_T_594, _T_593) @[el2_lib.scala 384:30]
|
|
node _T_596 = cat(_T_595, _T_592) @[el2_lib.scala 384:30]
|
|
node _T_597 = cat(_T_596, _T_589) @[el2_lib.scala 384:30]
|
|
node _T_598 = cat(_T_597, _T_582) @[el2_lib.scala 384:30]
|
|
node _T_599 = xorr(_T_598) @[el2_lib.scala 384:37]
|
|
node _T_600 = cat(_T_354[2], _T_354[1]) @[el2_lib.scala 384:47]
|
|
node _T_601 = cat(_T_600, _T_354[0]) @[el2_lib.scala 384:47]
|
|
node _T_602 = cat(_T_354[4], _T_354[3]) @[el2_lib.scala 384:47]
|
|
node _T_603 = cat(_T_354[6], _T_354[5]) @[el2_lib.scala 384:47]
|
|
node _T_604 = cat(_T_603, _T_602) @[el2_lib.scala 384:47]
|
|
node _T_605 = cat(_T_604, _T_601) @[el2_lib.scala 384:47]
|
|
node _T_606 = cat(_T_354[8], _T_354[7]) @[el2_lib.scala 384:47]
|
|
node _T_607 = cat(_T_354[10], _T_354[9]) @[el2_lib.scala 384:47]
|
|
node _T_608 = cat(_T_607, _T_606) @[el2_lib.scala 384:47]
|
|
node _T_609 = cat(_T_354[12], _T_354[11]) @[el2_lib.scala 384:47]
|
|
node _T_610 = cat(_T_354[14], _T_354[13]) @[el2_lib.scala 384:47]
|
|
node _T_611 = cat(_T_610, _T_609) @[el2_lib.scala 384:47]
|
|
node _T_612 = cat(_T_611, _T_608) @[el2_lib.scala 384:47]
|
|
node _T_613 = cat(_T_612, _T_605) @[el2_lib.scala 384:47]
|
|
node _T_614 = cat(_T_354[16], _T_354[15]) @[el2_lib.scala 384:47]
|
|
node _T_615 = cat(_T_354[18], _T_354[17]) @[el2_lib.scala 384:47]
|
|
node _T_616 = cat(_T_615, _T_614) @[el2_lib.scala 384:47]
|
|
node _T_617 = cat(_T_354[20], _T_354[19]) @[el2_lib.scala 384:47]
|
|
node _T_618 = cat(_T_354[22], _T_354[21]) @[el2_lib.scala 384:47]
|
|
node _T_619 = cat(_T_618, _T_617) @[el2_lib.scala 384:47]
|
|
node _T_620 = cat(_T_619, _T_616) @[el2_lib.scala 384:47]
|
|
node _T_621 = cat(_T_354[24], _T_354[23]) @[el2_lib.scala 384:47]
|
|
node _T_622 = cat(_T_354[26], _T_354[25]) @[el2_lib.scala 384:47]
|
|
node _T_623 = cat(_T_622, _T_621) @[el2_lib.scala 384:47]
|
|
node _T_624 = cat(_T_354[28], _T_354[27]) @[el2_lib.scala 384:47]
|
|
node _T_625 = cat(_T_354[30], _T_354[29]) @[el2_lib.scala 384:47]
|
|
node _T_626 = cat(_T_625, _T_624) @[el2_lib.scala 384:47]
|
|
node _T_627 = cat(_T_626, _T_623) @[el2_lib.scala 384:47]
|
|
node _T_628 = cat(_T_627, _T_620) @[el2_lib.scala 384:47]
|
|
node _T_629 = cat(_T_628, _T_613) @[el2_lib.scala 384:47]
|
|
node _T_630 = xorr(_T_629) @[el2_lib.scala 384:54]
|
|
node _T_631 = cat(_T_353[2], _T_353[1]) @[el2_lib.scala 384:64]
|
|
node _T_632 = cat(_T_631, _T_353[0]) @[el2_lib.scala 384:64]
|
|
node _T_633 = cat(_T_353[4], _T_353[3]) @[el2_lib.scala 384:64]
|
|
node _T_634 = cat(_T_353[6], _T_353[5]) @[el2_lib.scala 384:64]
|
|
node _T_635 = cat(_T_634, _T_633) @[el2_lib.scala 384:64]
|
|
node _T_636 = cat(_T_635, _T_632) @[el2_lib.scala 384:64]
|
|
node _T_637 = cat(_T_353[8], _T_353[7]) @[el2_lib.scala 384:64]
|
|
node _T_638 = cat(_T_353[10], _T_353[9]) @[el2_lib.scala 384:64]
|
|
node _T_639 = cat(_T_638, _T_637) @[el2_lib.scala 384:64]
|
|
node _T_640 = cat(_T_353[12], _T_353[11]) @[el2_lib.scala 384:64]
|
|
node _T_641 = cat(_T_353[14], _T_353[13]) @[el2_lib.scala 384:64]
|
|
node _T_642 = cat(_T_641, _T_640) @[el2_lib.scala 384:64]
|
|
node _T_643 = cat(_T_642, _T_639) @[el2_lib.scala 384:64]
|
|
node _T_644 = cat(_T_643, _T_636) @[el2_lib.scala 384:64]
|
|
node _T_645 = cat(_T_353[16], _T_353[15]) @[el2_lib.scala 384:64]
|
|
node _T_646 = cat(_T_353[18], _T_353[17]) @[el2_lib.scala 384:64]
|
|
node _T_647 = cat(_T_646, _T_645) @[el2_lib.scala 384:64]
|
|
node _T_648 = cat(_T_353[20], _T_353[19]) @[el2_lib.scala 384:64]
|
|
node _T_649 = cat(_T_353[22], _T_353[21]) @[el2_lib.scala 384:64]
|
|
node _T_650 = cat(_T_649, _T_648) @[el2_lib.scala 384:64]
|
|
node _T_651 = cat(_T_650, _T_647) @[el2_lib.scala 384:64]
|
|
node _T_652 = cat(_T_353[24], _T_353[23]) @[el2_lib.scala 384:64]
|
|
node _T_653 = cat(_T_353[26], _T_353[25]) @[el2_lib.scala 384:64]
|
|
node _T_654 = cat(_T_653, _T_652) @[el2_lib.scala 384:64]
|
|
node _T_655 = cat(_T_353[28], _T_353[27]) @[el2_lib.scala 384:64]
|
|
node _T_656 = cat(_T_353[30], _T_353[29]) @[el2_lib.scala 384:64]
|
|
node _T_657 = cat(_T_656, _T_655) @[el2_lib.scala 384:64]
|
|
node _T_658 = cat(_T_657, _T_654) @[el2_lib.scala 384:64]
|
|
node _T_659 = cat(_T_658, _T_651) @[el2_lib.scala 384:64]
|
|
node _T_660 = cat(_T_659, _T_644) @[el2_lib.scala 384:64]
|
|
node _T_661 = xorr(_T_660) @[el2_lib.scala 384:71]
|
|
node _T_662 = cat(_T_352[1], _T_352[0]) @[el2_lib.scala 384:81]
|
|
node _T_663 = cat(_T_352[3], _T_352[2]) @[el2_lib.scala 384:81]
|
|
node _T_664 = cat(_T_663, _T_662) @[el2_lib.scala 384:81]
|
|
node _T_665 = cat(_T_352[5], _T_352[4]) @[el2_lib.scala 384:81]
|
|
node _T_666 = cat(_T_352[7], _T_352[6]) @[el2_lib.scala 384:81]
|
|
node _T_667 = cat(_T_666, _T_665) @[el2_lib.scala 384:81]
|
|
node _T_668 = cat(_T_667, _T_664) @[el2_lib.scala 384:81]
|
|
node _T_669 = cat(_T_352[9], _T_352[8]) @[el2_lib.scala 384:81]
|
|
node _T_670 = cat(_T_352[11], _T_352[10]) @[el2_lib.scala 384:81]
|
|
node _T_671 = cat(_T_670, _T_669) @[el2_lib.scala 384:81]
|
|
node _T_672 = cat(_T_352[13], _T_352[12]) @[el2_lib.scala 384:81]
|
|
node _T_673 = cat(_T_352[16], _T_352[15]) @[el2_lib.scala 384:81]
|
|
node _T_674 = cat(_T_673, _T_352[14]) @[el2_lib.scala 384:81]
|
|
node _T_675 = cat(_T_674, _T_672) @[el2_lib.scala 384:81]
|
|
node _T_676 = cat(_T_675, _T_671) @[el2_lib.scala 384:81]
|
|
node _T_677 = cat(_T_676, _T_668) @[el2_lib.scala 384:81]
|
|
node _T_678 = cat(_T_352[18], _T_352[17]) @[el2_lib.scala 384:81]
|
|
node _T_679 = cat(_T_352[20], _T_352[19]) @[el2_lib.scala 384:81]
|
|
node _T_680 = cat(_T_679, _T_678) @[el2_lib.scala 384:81]
|
|
node _T_681 = cat(_T_352[22], _T_352[21]) @[el2_lib.scala 384:81]
|
|
node _T_682 = cat(_T_352[25], _T_352[24]) @[el2_lib.scala 384:81]
|
|
node _T_683 = cat(_T_682, _T_352[23]) @[el2_lib.scala 384:81]
|
|
node _T_684 = cat(_T_683, _T_681) @[el2_lib.scala 384:81]
|
|
node _T_685 = cat(_T_684, _T_680) @[el2_lib.scala 384:81]
|
|
node _T_686 = cat(_T_352[27], _T_352[26]) @[el2_lib.scala 384:81]
|
|
node _T_687 = cat(_T_352[29], _T_352[28]) @[el2_lib.scala 384:81]
|
|
node _T_688 = cat(_T_687, _T_686) @[el2_lib.scala 384:81]
|
|
node _T_689 = cat(_T_352[31], _T_352[30]) @[el2_lib.scala 384:81]
|
|
node _T_690 = cat(_T_352[34], _T_352[33]) @[el2_lib.scala 384:81]
|
|
node _T_691 = cat(_T_690, _T_352[32]) @[el2_lib.scala 384:81]
|
|
node _T_692 = cat(_T_691, _T_689) @[el2_lib.scala 384:81]
|
|
node _T_693 = cat(_T_692, _T_688) @[el2_lib.scala 384:81]
|
|
node _T_694 = cat(_T_693, _T_685) @[el2_lib.scala 384:81]
|
|
node _T_695 = cat(_T_694, _T_677) @[el2_lib.scala 384:81]
|
|
node _T_696 = xorr(_T_695) @[el2_lib.scala 384:88]
|
|
node _T_697 = cat(_T_351[1], _T_351[0]) @[el2_lib.scala 384:98]
|
|
node _T_698 = cat(_T_351[3], _T_351[2]) @[el2_lib.scala 384:98]
|
|
node _T_699 = cat(_T_698, _T_697) @[el2_lib.scala 384:98]
|
|
node _T_700 = cat(_T_351[5], _T_351[4]) @[el2_lib.scala 384:98]
|
|
node _T_701 = cat(_T_351[7], _T_351[6]) @[el2_lib.scala 384:98]
|
|
node _T_702 = cat(_T_701, _T_700) @[el2_lib.scala 384:98]
|
|
node _T_703 = cat(_T_702, _T_699) @[el2_lib.scala 384:98]
|
|
node _T_704 = cat(_T_351[9], _T_351[8]) @[el2_lib.scala 384:98]
|
|
node _T_705 = cat(_T_351[11], _T_351[10]) @[el2_lib.scala 384:98]
|
|
node _T_706 = cat(_T_705, _T_704) @[el2_lib.scala 384:98]
|
|
node _T_707 = cat(_T_351[13], _T_351[12]) @[el2_lib.scala 384:98]
|
|
node _T_708 = cat(_T_351[16], _T_351[15]) @[el2_lib.scala 384:98]
|
|
node _T_709 = cat(_T_708, _T_351[14]) @[el2_lib.scala 384:98]
|
|
node _T_710 = cat(_T_709, _T_707) @[el2_lib.scala 384:98]
|
|
node _T_711 = cat(_T_710, _T_706) @[el2_lib.scala 384:98]
|
|
node _T_712 = cat(_T_711, _T_703) @[el2_lib.scala 384:98]
|
|
node _T_713 = cat(_T_351[18], _T_351[17]) @[el2_lib.scala 384:98]
|
|
node _T_714 = cat(_T_351[20], _T_351[19]) @[el2_lib.scala 384:98]
|
|
node _T_715 = cat(_T_714, _T_713) @[el2_lib.scala 384:98]
|
|
node _T_716 = cat(_T_351[22], _T_351[21]) @[el2_lib.scala 384:98]
|
|
node _T_717 = cat(_T_351[25], _T_351[24]) @[el2_lib.scala 384:98]
|
|
node _T_718 = cat(_T_717, _T_351[23]) @[el2_lib.scala 384:98]
|
|
node _T_719 = cat(_T_718, _T_716) @[el2_lib.scala 384:98]
|
|
node _T_720 = cat(_T_719, _T_715) @[el2_lib.scala 384:98]
|
|
node _T_721 = cat(_T_351[27], _T_351[26]) @[el2_lib.scala 384:98]
|
|
node _T_722 = cat(_T_351[29], _T_351[28]) @[el2_lib.scala 384:98]
|
|
node _T_723 = cat(_T_722, _T_721) @[el2_lib.scala 384:98]
|
|
node _T_724 = cat(_T_351[31], _T_351[30]) @[el2_lib.scala 384:98]
|
|
node _T_725 = cat(_T_351[34], _T_351[33]) @[el2_lib.scala 384:98]
|
|
node _T_726 = cat(_T_725, _T_351[32]) @[el2_lib.scala 384:98]
|
|
node _T_727 = cat(_T_726, _T_724) @[el2_lib.scala 384:98]
|
|
node _T_728 = cat(_T_727, _T_723) @[el2_lib.scala 384:98]
|
|
node _T_729 = cat(_T_728, _T_720) @[el2_lib.scala 384:98]
|
|
node _T_730 = cat(_T_729, _T_712) @[el2_lib.scala 384:98]
|
|
node _T_731 = xorr(_T_730) @[el2_lib.scala 384:105]
|
|
node _T_732 = cat(_T_350[1], _T_350[0]) @[el2_lib.scala 384:115]
|
|
node _T_733 = cat(_T_350[3], _T_350[2]) @[el2_lib.scala 384:115]
|
|
node _T_734 = cat(_T_733, _T_732) @[el2_lib.scala 384:115]
|
|
node _T_735 = cat(_T_350[5], _T_350[4]) @[el2_lib.scala 384:115]
|
|
node _T_736 = cat(_T_350[7], _T_350[6]) @[el2_lib.scala 384:115]
|
|
node _T_737 = cat(_T_736, _T_735) @[el2_lib.scala 384:115]
|
|
node _T_738 = cat(_T_737, _T_734) @[el2_lib.scala 384:115]
|
|
node _T_739 = cat(_T_350[9], _T_350[8]) @[el2_lib.scala 384:115]
|
|
node _T_740 = cat(_T_350[11], _T_350[10]) @[el2_lib.scala 384:115]
|
|
node _T_741 = cat(_T_740, _T_739) @[el2_lib.scala 384:115]
|
|
node _T_742 = cat(_T_350[13], _T_350[12]) @[el2_lib.scala 384:115]
|
|
node _T_743 = cat(_T_350[16], _T_350[15]) @[el2_lib.scala 384:115]
|
|
node _T_744 = cat(_T_743, _T_350[14]) @[el2_lib.scala 384:115]
|
|
node _T_745 = cat(_T_744, _T_742) @[el2_lib.scala 384:115]
|
|
node _T_746 = cat(_T_745, _T_741) @[el2_lib.scala 384:115]
|
|
node _T_747 = cat(_T_746, _T_738) @[el2_lib.scala 384:115]
|
|
node _T_748 = cat(_T_350[18], _T_350[17]) @[el2_lib.scala 384:115]
|
|
node _T_749 = cat(_T_350[20], _T_350[19]) @[el2_lib.scala 384:115]
|
|
node _T_750 = cat(_T_749, _T_748) @[el2_lib.scala 384:115]
|
|
node _T_751 = cat(_T_350[22], _T_350[21]) @[el2_lib.scala 384:115]
|
|
node _T_752 = cat(_T_350[25], _T_350[24]) @[el2_lib.scala 384:115]
|
|
node _T_753 = cat(_T_752, _T_350[23]) @[el2_lib.scala 384:115]
|
|
node _T_754 = cat(_T_753, _T_751) @[el2_lib.scala 384:115]
|
|
node _T_755 = cat(_T_754, _T_750) @[el2_lib.scala 384:115]
|
|
node _T_756 = cat(_T_350[27], _T_350[26]) @[el2_lib.scala 384:115]
|
|
node _T_757 = cat(_T_350[29], _T_350[28]) @[el2_lib.scala 384:115]
|
|
node _T_758 = cat(_T_757, _T_756) @[el2_lib.scala 384:115]
|
|
node _T_759 = cat(_T_350[31], _T_350[30]) @[el2_lib.scala 384:115]
|
|
node _T_760 = cat(_T_350[34], _T_350[33]) @[el2_lib.scala 384:115]
|
|
node _T_761 = cat(_T_760, _T_350[32]) @[el2_lib.scala 384:115]
|
|
node _T_762 = cat(_T_761, _T_759) @[el2_lib.scala 384:115]
|
|
node _T_763 = cat(_T_762, _T_758) @[el2_lib.scala 384:115]
|
|
node _T_764 = cat(_T_763, _T_755) @[el2_lib.scala 384:115]
|
|
node _T_765 = cat(_T_764, _T_747) @[el2_lib.scala 384:115]
|
|
node _T_766 = xorr(_T_765) @[el2_lib.scala 384:122]
|
|
node _T_767 = cat(_T_696, _T_731) @[Cat.scala 29:58]
|
|
node _T_768 = cat(_T_767, _T_766) @[Cat.scala 29:58]
|
|
node _T_769 = cat(_T_630, _T_661) @[Cat.scala 29:58]
|
|
node _T_770 = cat(_T_568, _T_599) @[Cat.scala 29:58]
|
|
node _T_771 = cat(_T_770, _T_769) @[Cat.scala 29:58]
|
|
node ic_wr_ecc = cat(_T_771, _T_768) @[Cat.scala 29:58]
|
|
wire _T_772 : UInt<1>[35] @[el2_lib.scala 363:18]
|
|
wire _T_773 : UInt<1>[35] @[el2_lib.scala 364:18]
|
|
wire _T_774 : UInt<1>[35] @[el2_lib.scala 365:18]
|
|
wire _T_775 : UInt<1>[31] @[el2_lib.scala 366:18]
|
|
wire _T_776 : UInt<1>[31] @[el2_lib.scala 367:18]
|
|
wire _T_777 : UInt<1>[31] @[el2_lib.scala 368:18]
|
|
wire _T_778 : UInt<1>[7] @[el2_lib.scala 369:18]
|
|
node _T_779 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 376:36]
|
|
_T_772[0] <= _T_779 @[el2_lib.scala 376:30]
|
|
node _T_780 = bits(ic_miss_buff_half, 0, 0) @[el2_lib.scala 377:36]
|
|
_T_773[0] <= _T_780 @[el2_lib.scala 377:30]
|
|
node _T_781 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 376:36]
|
|
_T_772[1] <= _T_781 @[el2_lib.scala 376:30]
|
|
node _T_782 = bits(ic_miss_buff_half, 1, 1) @[el2_lib.scala 378:36]
|
|
_T_774[0] <= _T_782 @[el2_lib.scala 378:30]
|
|
node _T_783 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 377:36]
|
|
_T_773[1] <= _T_783 @[el2_lib.scala 377:30]
|
|
node _T_784 = bits(ic_miss_buff_half, 2, 2) @[el2_lib.scala 378:36]
|
|
_T_774[1] <= _T_784 @[el2_lib.scala 378:30]
|
|
node _T_785 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 376:36]
|
|
_T_772[2] <= _T_785 @[el2_lib.scala 376:30]
|
|
node _T_786 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 377:36]
|
|
_T_773[2] <= _T_786 @[el2_lib.scala 377:30]
|
|
node _T_787 = bits(ic_miss_buff_half, 3, 3) @[el2_lib.scala 378:36]
|
|
_T_774[2] <= _T_787 @[el2_lib.scala 378:30]
|
|
node _T_788 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 376:36]
|
|
_T_772[3] <= _T_788 @[el2_lib.scala 376:30]
|
|
node _T_789 = bits(ic_miss_buff_half, 4, 4) @[el2_lib.scala 379:36]
|
|
_T_775[0] <= _T_789 @[el2_lib.scala 379:30]
|
|
node _T_790 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 377:36]
|
|
_T_773[3] <= _T_790 @[el2_lib.scala 377:30]
|
|
node _T_791 = bits(ic_miss_buff_half, 5, 5) @[el2_lib.scala 379:36]
|
|
_T_775[1] <= _T_791 @[el2_lib.scala 379:30]
|
|
node _T_792 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 376:36]
|
|
_T_772[4] <= _T_792 @[el2_lib.scala 376:30]
|
|
node _T_793 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 377:36]
|
|
_T_773[4] <= _T_793 @[el2_lib.scala 377:30]
|
|
node _T_794 = bits(ic_miss_buff_half, 6, 6) @[el2_lib.scala 379:36]
|
|
_T_775[2] <= _T_794 @[el2_lib.scala 379:30]
|
|
node _T_795 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 378:36]
|
|
_T_774[3] <= _T_795 @[el2_lib.scala 378:30]
|
|
node _T_796 = bits(ic_miss_buff_half, 7, 7) @[el2_lib.scala 379:36]
|
|
_T_775[3] <= _T_796 @[el2_lib.scala 379:30]
|
|
node _T_797 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 376:36]
|
|
_T_772[5] <= _T_797 @[el2_lib.scala 376:30]
|
|
node _T_798 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 378:36]
|
|
_T_774[4] <= _T_798 @[el2_lib.scala 378:30]
|
|
node _T_799 = bits(ic_miss_buff_half, 8, 8) @[el2_lib.scala 379:36]
|
|
_T_775[4] <= _T_799 @[el2_lib.scala 379:30]
|
|
node _T_800 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 377:36]
|
|
_T_773[5] <= _T_800 @[el2_lib.scala 377:30]
|
|
node _T_801 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 378:36]
|
|
_T_774[5] <= _T_801 @[el2_lib.scala 378:30]
|
|
node _T_802 = bits(ic_miss_buff_half, 9, 9) @[el2_lib.scala 379:36]
|
|
_T_775[5] <= _T_802 @[el2_lib.scala 379:30]
|
|
node _T_803 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 376:36]
|
|
_T_772[6] <= _T_803 @[el2_lib.scala 376:30]
|
|
node _T_804 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 377:36]
|
|
_T_773[6] <= _T_804 @[el2_lib.scala 377:30]
|
|
node _T_805 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 378:36]
|
|
_T_774[6] <= _T_805 @[el2_lib.scala 378:30]
|
|
node _T_806 = bits(ic_miss_buff_half, 10, 10) @[el2_lib.scala 379:36]
|
|
_T_775[6] <= _T_806 @[el2_lib.scala 379:30]
|
|
node _T_807 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 376:36]
|
|
_T_772[7] <= _T_807 @[el2_lib.scala 376:30]
|
|
node _T_808 = bits(ic_miss_buff_half, 11, 11) @[el2_lib.scala 380:36]
|
|
_T_776[0] <= _T_808 @[el2_lib.scala 380:30]
|
|
node _T_809 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 377:36]
|
|
_T_773[7] <= _T_809 @[el2_lib.scala 377:30]
|
|
node _T_810 = bits(ic_miss_buff_half, 12, 12) @[el2_lib.scala 380:36]
|
|
_T_776[1] <= _T_810 @[el2_lib.scala 380:30]
|
|
node _T_811 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 376:36]
|
|
_T_772[8] <= _T_811 @[el2_lib.scala 376:30]
|
|
node _T_812 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 377:36]
|
|
_T_773[8] <= _T_812 @[el2_lib.scala 377:30]
|
|
node _T_813 = bits(ic_miss_buff_half, 13, 13) @[el2_lib.scala 380:36]
|
|
_T_776[2] <= _T_813 @[el2_lib.scala 380:30]
|
|
node _T_814 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 378:36]
|
|
_T_774[7] <= _T_814 @[el2_lib.scala 378:30]
|
|
node _T_815 = bits(ic_miss_buff_half, 14, 14) @[el2_lib.scala 380:36]
|
|
_T_776[3] <= _T_815 @[el2_lib.scala 380:30]
|
|
node _T_816 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 376:36]
|
|
_T_772[9] <= _T_816 @[el2_lib.scala 376:30]
|
|
node _T_817 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 378:36]
|
|
_T_774[8] <= _T_817 @[el2_lib.scala 378:30]
|
|
node _T_818 = bits(ic_miss_buff_half, 15, 15) @[el2_lib.scala 380:36]
|
|
_T_776[4] <= _T_818 @[el2_lib.scala 380:30]
|
|
node _T_819 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 377:36]
|
|
_T_773[9] <= _T_819 @[el2_lib.scala 377:30]
|
|
node _T_820 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 378:36]
|
|
_T_774[9] <= _T_820 @[el2_lib.scala 378:30]
|
|
node _T_821 = bits(ic_miss_buff_half, 16, 16) @[el2_lib.scala 380:36]
|
|
_T_776[5] <= _T_821 @[el2_lib.scala 380:30]
|
|
node _T_822 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 376:36]
|
|
_T_772[10] <= _T_822 @[el2_lib.scala 376:30]
|
|
node _T_823 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 377:36]
|
|
_T_773[10] <= _T_823 @[el2_lib.scala 377:30]
|
|
node _T_824 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 378:36]
|
|
_T_774[10] <= _T_824 @[el2_lib.scala 378:30]
|
|
node _T_825 = bits(ic_miss_buff_half, 17, 17) @[el2_lib.scala 380:36]
|
|
_T_776[6] <= _T_825 @[el2_lib.scala 380:30]
|
|
node _T_826 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 379:36]
|
|
_T_775[7] <= _T_826 @[el2_lib.scala 379:30]
|
|
node _T_827 = bits(ic_miss_buff_half, 18, 18) @[el2_lib.scala 380:36]
|
|
_T_776[7] <= _T_827 @[el2_lib.scala 380:30]
|
|
node _T_828 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 376:36]
|
|
_T_772[11] <= _T_828 @[el2_lib.scala 376:30]
|
|
node _T_829 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 379:36]
|
|
_T_775[8] <= _T_829 @[el2_lib.scala 379:30]
|
|
node _T_830 = bits(ic_miss_buff_half, 19, 19) @[el2_lib.scala 380:36]
|
|
_T_776[8] <= _T_830 @[el2_lib.scala 380:30]
|
|
node _T_831 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 377:36]
|
|
_T_773[11] <= _T_831 @[el2_lib.scala 377:30]
|
|
node _T_832 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 379:36]
|
|
_T_775[9] <= _T_832 @[el2_lib.scala 379:30]
|
|
node _T_833 = bits(ic_miss_buff_half, 20, 20) @[el2_lib.scala 380:36]
|
|
_T_776[9] <= _T_833 @[el2_lib.scala 380:30]
|
|
node _T_834 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 376:36]
|
|
_T_772[12] <= _T_834 @[el2_lib.scala 376:30]
|
|
node _T_835 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 377:36]
|
|
_T_773[12] <= _T_835 @[el2_lib.scala 377:30]
|
|
node _T_836 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 379:36]
|
|
_T_775[10] <= _T_836 @[el2_lib.scala 379:30]
|
|
node _T_837 = bits(ic_miss_buff_half, 21, 21) @[el2_lib.scala 380:36]
|
|
_T_776[10] <= _T_837 @[el2_lib.scala 380:30]
|
|
node _T_838 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 378:36]
|
|
_T_774[11] <= _T_838 @[el2_lib.scala 378:30]
|
|
node _T_839 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 379:36]
|
|
_T_775[11] <= _T_839 @[el2_lib.scala 379:30]
|
|
node _T_840 = bits(ic_miss_buff_half, 22, 22) @[el2_lib.scala 380:36]
|
|
_T_776[11] <= _T_840 @[el2_lib.scala 380:30]
|
|
node _T_841 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 376:36]
|
|
_T_772[13] <= _T_841 @[el2_lib.scala 376:30]
|
|
node _T_842 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 378:36]
|
|
_T_774[12] <= _T_842 @[el2_lib.scala 378:30]
|
|
node _T_843 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 379:36]
|
|
_T_775[12] <= _T_843 @[el2_lib.scala 379:30]
|
|
node _T_844 = bits(ic_miss_buff_half, 23, 23) @[el2_lib.scala 380:36]
|
|
_T_776[12] <= _T_844 @[el2_lib.scala 380:30]
|
|
node _T_845 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 377:36]
|
|
_T_773[13] <= _T_845 @[el2_lib.scala 377:30]
|
|
node _T_846 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 378:36]
|
|
_T_774[13] <= _T_846 @[el2_lib.scala 378:30]
|
|
node _T_847 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 379:36]
|
|
_T_775[13] <= _T_847 @[el2_lib.scala 379:30]
|
|
node _T_848 = bits(ic_miss_buff_half, 24, 24) @[el2_lib.scala 380:36]
|
|
_T_776[13] <= _T_848 @[el2_lib.scala 380:30]
|
|
node _T_849 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 376:36]
|
|
_T_772[14] <= _T_849 @[el2_lib.scala 376:30]
|
|
node _T_850 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 377:36]
|
|
_T_773[14] <= _T_850 @[el2_lib.scala 377:30]
|
|
node _T_851 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 378:36]
|
|
_T_774[14] <= _T_851 @[el2_lib.scala 378:30]
|
|
node _T_852 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 379:36]
|
|
_T_775[14] <= _T_852 @[el2_lib.scala 379:30]
|
|
node _T_853 = bits(ic_miss_buff_half, 25, 25) @[el2_lib.scala 380:36]
|
|
_T_776[14] <= _T_853 @[el2_lib.scala 380:30]
|
|
node _T_854 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 376:36]
|
|
_T_772[15] <= _T_854 @[el2_lib.scala 376:30]
|
|
node _T_855 = bits(ic_miss_buff_half, 26, 26) @[el2_lib.scala 381:36]
|
|
_T_777[0] <= _T_855 @[el2_lib.scala 381:30]
|
|
node _T_856 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 377:36]
|
|
_T_773[15] <= _T_856 @[el2_lib.scala 377:30]
|
|
node _T_857 = bits(ic_miss_buff_half, 27, 27) @[el2_lib.scala 381:36]
|
|
_T_777[1] <= _T_857 @[el2_lib.scala 381:30]
|
|
node _T_858 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 376:36]
|
|
_T_772[16] <= _T_858 @[el2_lib.scala 376:30]
|
|
node _T_859 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 377:36]
|
|
_T_773[16] <= _T_859 @[el2_lib.scala 377:30]
|
|
node _T_860 = bits(ic_miss_buff_half, 28, 28) @[el2_lib.scala 381:36]
|
|
_T_777[2] <= _T_860 @[el2_lib.scala 381:30]
|
|
node _T_861 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 378:36]
|
|
_T_774[15] <= _T_861 @[el2_lib.scala 378:30]
|
|
node _T_862 = bits(ic_miss_buff_half, 29, 29) @[el2_lib.scala 381:36]
|
|
_T_777[3] <= _T_862 @[el2_lib.scala 381:30]
|
|
node _T_863 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 376:36]
|
|
_T_772[17] <= _T_863 @[el2_lib.scala 376:30]
|
|
node _T_864 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 378:36]
|
|
_T_774[16] <= _T_864 @[el2_lib.scala 378:30]
|
|
node _T_865 = bits(ic_miss_buff_half, 30, 30) @[el2_lib.scala 381:36]
|
|
_T_777[4] <= _T_865 @[el2_lib.scala 381:30]
|
|
node _T_866 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 377:36]
|
|
_T_773[17] <= _T_866 @[el2_lib.scala 377:30]
|
|
node _T_867 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 378:36]
|
|
_T_774[17] <= _T_867 @[el2_lib.scala 378:30]
|
|
node _T_868 = bits(ic_miss_buff_half, 31, 31) @[el2_lib.scala 381:36]
|
|
_T_777[5] <= _T_868 @[el2_lib.scala 381:30]
|
|
node _T_869 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 376:36]
|
|
_T_772[18] <= _T_869 @[el2_lib.scala 376:30]
|
|
node _T_870 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 377:36]
|
|
_T_773[18] <= _T_870 @[el2_lib.scala 377:30]
|
|
node _T_871 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 378:36]
|
|
_T_774[18] <= _T_871 @[el2_lib.scala 378:30]
|
|
node _T_872 = bits(ic_miss_buff_half, 32, 32) @[el2_lib.scala 381:36]
|
|
_T_777[6] <= _T_872 @[el2_lib.scala 381:30]
|
|
node _T_873 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 379:36]
|
|
_T_775[15] <= _T_873 @[el2_lib.scala 379:30]
|
|
node _T_874 = bits(ic_miss_buff_half, 33, 33) @[el2_lib.scala 381:36]
|
|
_T_777[7] <= _T_874 @[el2_lib.scala 381:30]
|
|
node _T_875 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 376:36]
|
|
_T_772[19] <= _T_875 @[el2_lib.scala 376:30]
|
|
node _T_876 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 379:36]
|
|
_T_775[16] <= _T_876 @[el2_lib.scala 379:30]
|
|
node _T_877 = bits(ic_miss_buff_half, 34, 34) @[el2_lib.scala 381:36]
|
|
_T_777[8] <= _T_877 @[el2_lib.scala 381:30]
|
|
node _T_878 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 377:36]
|
|
_T_773[19] <= _T_878 @[el2_lib.scala 377:30]
|
|
node _T_879 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 379:36]
|
|
_T_775[17] <= _T_879 @[el2_lib.scala 379:30]
|
|
node _T_880 = bits(ic_miss_buff_half, 35, 35) @[el2_lib.scala 381:36]
|
|
_T_777[9] <= _T_880 @[el2_lib.scala 381:30]
|
|
node _T_881 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 376:36]
|
|
_T_772[20] <= _T_881 @[el2_lib.scala 376:30]
|
|
node _T_882 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 377:36]
|
|
_T_773[20] <= _T_882 @[el2_lib.scala 377:30]
|
|
node _T_883 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 379:36]
|
|
_T_775[18] <= _T_883 @[el2_lib.scala 379:30]
|
|
node _T_884 = bits(ic_miss_buff_half, 36, 36) @[el2_lib.scala 381:36]
|
|
_T_777[10] <= _T_884 @[el2_lib.scala 381:30]
|
|
node _T_885 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 378:36]
|
|
_T_774[19] <= _T_885 @[el2_lib.scala 378:30]
|
|
node _T_886 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 379:36]
|
|
_T_775[19] <= _T_886 @[el2_lib.scala 379:30]
|
|
node _T_887 = bits(ic_miss_buff_half, 37, 37) @[el2_lib.scala 381:36]
|
|
_T_777[11] <= _T_887 @[el2_lib.scala 381:30]
|
|
node _T_888 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 376:36]
|
|
_T_772[21] <= _T_888 @[el2_lib.scala 376:30]
|
|
node _T_889 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 378:36]
|
|
_T_774[20] <= _T_889 @[el2_lib.scala 378:30]
|
|
node _T_890 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 379:36]
|
|
_T_775[20] <= _T_890 @[el2_lib.scala 379:30]
|
|
node _T_891 = bits(ic_miss_buff_half, 38, 38) @[el2_lib.scala 381:36]
|
|
_T_777[12] <= _T_891 @[el2_lib.scala 381:30]
|
|
node _T_892 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 377:36]
|
|
_T_773[21] <= _T_892 @[el2_lib.scala 377:30]
|
|
node _T_893 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 378:36]
|
|
_T_774[21] <= _T_893 @[el2_lib.scala 378:30]
|
|
node _T_894 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 379:36]
|
|
_T_775[21] <= _T_894 @[el2_lib.scala 379:30]
|
|
node _T_895 = bits(ic_miss_buff_half, 39, 39) @[el2_lib.scala 381:36]
|
|
_T_777[13] <= _T_895 @[el2_lib.scala 381:30]
|
|
node _T_896 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 376:36]
|
|
_T_772[22] <= _T_896 @[el2_lib.scala 376:30]
|
|
node _T_897 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 377:36]
|
|
_T_773[22] <= _T_897 @[el2_lib.scala 377:30]
|
|
node _T_898 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 378:36]
|
|
_T_774[22] <= _T_898 @[el2_lib.scala 378:30]
|
|
node _T_899 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 379:36]
|
|
_T_775[22] <= _T_899 @[el2_lib.scala 379:30]
|
|
node _T_900 = bits(ic_miss_buff_half, 40, 40) @[el2_lib.scala 381:36]
|
|
_T_777[14] <= _T_900 @[el2_lib.scala 381:30]
|
|
node _T_901 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 380:36]
|
|
_T_776[15] <= _T_901 @[el2_lib.scala 380:30]
|
|
node _T_902 = bits(ic_miss_buff_half, 41, 41) @[el2_lib.scala 381:36]
|
|
_T_777[15] <= _T_902 @[el2_lib.scala 381:30]
|
|
node _T_903 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 376:36]
|
|
_T_772[23] <= _T_903 @[el2_lib.scala 376:30]
|
|
node _T_904 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 380:36]
|
|
_T_776[16] <= _T_904 @[el2_lib.scala 380:30]
|
|
node _T_905 = bits(ic_miss_buff_half, 42, 42) @[el2_lib.scala 381:36]
|
|
_T_777[16] <= _T_905 @[el2_lib.scala 381:30]
|
|
node _T_906 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 377:36]
|
|
_T_773[23] <= _T_906 @[el2_lib.scala 377:30]
|
|
node _T_907 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 380:36]
|
|
_T_776[17] <= _T_907 @[el2_lib.scala 380:30]
|
|
node _T_908 = bits(ic_miss_buff_half, 43, 43) @[el2_lib.scala 381:36]
|
|
_T_777[17] <= _T_908 @[el2_lib.scala 381:30]
|
|
node _T_909 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 376:36]
|
|
_T_772[24] <= _T_909 @[el2_lib.scala 376:30]
|
|
node _T_910 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 377:36]
|
|
_T_773[24] <= _T_910 @[el2_lib.scala 377:30]
|
|
node _T_911 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 380:36]
|
|
_T_776[18] <= _T_911 @[el2_lib.scala 380:30]
|
|
node _T_912 = bits(ic_miss_buff_half, 44, 44) @[el2_lib.scala 381:36]
|
|
_T_777[18] <= _T_912 @[el2_lib.scala 381:30]
|
|
node _T_913 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 378:36]
|
|
_T_774[23] <= _T_913 @[el2_lib.scala 378:30]
|
|
node _T_914 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 380:36]
|
|
_T_776[19] <= _T_914 @[el2_lib.scala 380:30]
|
|
node _T_915 = bits(ic_miss_buff_half, 45, 45) @[el2_lib.scala 381:36]
|
|
_T_777[19] <= _T_915 @[el2_lib.scala 381:30]
|
|
node _T_916 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 376:36]
|
|
_T_772[25] <= _T_916 @[el2_lib.scala 376:30]
|
|
node _T_917 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 378:36]
|
|
_T_774[24] <= _T_917 @[el2_lib.scala 378:30]
|
|
node _T_918 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 380:36]
|
|
_T_776[20] <= _T_918 @[el2_lib.scala 380:30]
|
|
node _T_919 = bits(ic_miss_buff_half, 46, 46) @[el2_lib.scala 381:36]
|
|
_T_777[20] <= _T_919 @[el2_lib.scala 381:30]
|
|
node _T_920 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 377:36]
|
|
_T_773[25] <= _T_920 @[el2_lib.scala 377:30]
|
|
node _T_921 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 378:36]
|
|
_T_774[25] <= _T_921 @[el2_lib.scala 378:30]
|
|
node _T_922 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 380:36]
|
|
_T_776[21] <= _T_922 @[el2_lib.scala 380:30]
|
|
node _T_923 = bits(ic_miss_buff_half, 47, 47) @[el2_lib.scala 381:36]
|
|
_T_777[21] <= _T_923 @[el2_lib.scala 381:30]
|
|
node _T_924 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 376:36]
|
|
_T_772[26] <= _T_924 @[el2_lib.scala 376:30]
|
|
node _T_925 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 377:36]
|
|
_T_773[26] <= _T_925 @[el2_lib.scala 377:30]
|
|
node _T_926 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 378:36]
|
|
_T_774[26] <= _T_926 @[el2_lib.scala 378:30]
|
|
node _T_927 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 380:36]
|
|
_T_776[22] <= _T_927 @[el2_lib.scala 380:30]
|
|
node _T_928 = bits(ic_miss_buff_half, 48, 48) @[el2_lib.scala 381:36]
|
|
_T_777[22] <= _T_928 @[el2_lib.scala 381:30]
|
|
node _T_929 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 379:36]
|
|
_T_775[23] <= _T_929 @[el2_lib.scala 379:30]
|
|
node _T_930 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 380:36]
|
|
_T_776[23] <= _T_930 @[el2_lib.scala 380:30]
|
|
node _T_931 = bits(ic_miss_buff_half, 49, 49) @[el2_lib.scala 381:36]
|
|
_T_777[23] <= _T_931 @[el2_lib.scala 381:30]
|
|
node _T_932 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 376:36]
|
|
_T_772[27] <= _T_932 @[el2_lib.scala 376:30]
|
|
node _T_933 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 379:36]
|
|
_T_775[24] <= _T_933 @[el2_lib.scala 379:30]
|
|
node _T_934 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 380:36]
|
|
_T_776[24] <= _T_934 @[el2_lib.scala 380:30]
|
|
node _T_935 = bits(ic_miss_buff_half, 50, 50) @[el2_lib.scala 381:36]
|
|
_T_777[24] <= _T_935 @[el2_lib.scala 381:30]
|
|
node _T_936 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 377:36]
|
|
_T_773[27] <= _T_936 @[el2_lib.scala 377:30]
|
|
node _T_937 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 379:36]
|
|
_T_775[25] <= _T_937 @[el2_lib.scala 379:30]
|
|
node _T_938 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 380:36]
|
|
_T_776[25] <= _T_938 @[el2_lib.scala 380:30]
|
|
node _T_939 = bits(ic_miss_buff_half, 51, 51) @[el2_lib.scala 381:36]
|
|
_T_777[25] <= _T_939 @[el2_lib.scala 381:30]
|
|
node _T_940 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 376:36]
|
|
_T_772[28] <= _T_940 @[el2_lib.scala 376:30]
|
|
node _T_941 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 377:36]
|
|
_T_773[28] <= _T_941 @[el2_lib.scala 377:30]
|
|
node _T_942 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 379:36]
|
|
_T_775[26] <= _T_942 @[el2_lib.scala 379:30]
|
|
node _T_943 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 380:36]
|
|
_T_776[26] <= _T_943 @[el2_lib.scala 380:30]
|
|
node _T_944 = bits(ic_miss_buff_half, 52, 52) @[el2_lib.scala 381:36]
|
|
_T_777[26] <= _T_944 @[el2_lib.scala 381:30]
|
|
node _T_945 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 378:36]
|
|
_T_774[27] <= _T_945 @[el2_lib.scala 378:30]
|
|
node _T_946 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 379:36]
|
|
_T_775[27] <= _T_946 @[el2_lib.scala 379:30]
|
|
node _T_947 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 380:36]
|
|
_T_776[27] <= _T_947 @[el2_lib.scala 380:30]
|
|
node _T_948 = bits(ic_miss_buff_half, 53, 53) @[el2_lib.scala 381:36]
|
|
_T_777[27] <= _T_948 @[el2_lib.scala 381:30]
|
|
node _T_949 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 376:36]
|
|
_T_772[29] <= _T_949 @[el2_lib.scala 376:30]
|
|
node _T_950 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 378:36]
|
|
_T_774[28] <= _T_950 @[el2_lib.scala 378:30]
|
|
node _T_951 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 379:36]
|
|
_T_775[28] <= _T_951 @[el2_lib.scala 379:30]
|
|
node _T_952 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 380:36]
|
|
_T_776[28] <= _T_952 @[el2_lib.scala 380:30]
|
|
node _T_953 = bits(ic_miss_buff_half, 54, 54) @[el2_lib.scala 381:36]
|
|
_T_777[28] <= _T_953 @[el2_lib.scala 381:30]
|
|
node _T_954 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 377:36]
|
|
_T_773[29] <= _T_954 @[el2_lib.scala 377:30]
|
|
node _T_955 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 378:36]
|
|
_T_774[29] <= _T_955 @[el2_lib.scala 378:30]
|
|
node _T_956 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 379:36]
|
|
_T_775[29] <= _T_956 @[el2_lib.scala 379:30]
|
|
node _T_957 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 380:36]
|
|
_T_776[29] <= _T_957 @[el2_lib.scala 380:30]
|
|
node _T_958 = bits(ic_miss_buff_half, 55, 55) @[el2_lib.scala 381:36]
|
|
_T_777[29] <= _T_958 @[el2_lib.scala 381:30]
|
|
node _T_959 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 376:36]
|
|
_T_772[30] <= _T_959 @[el2_lib.scala 376:30]
|
|
node _T_960 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 377:36]
|
|
_T_773[30] <= _T_960 @[el2_lib.scala 377:30]
|
|
node _T_961 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 378:36]
|
|
_T_774[30] <= _T_961 @[el2_lib.scala 378:30]
|
|
node _T_962 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 379:36]
|
|
_T_775[30] <= _T_962 @[el2_lib.scala 379:30]
|
|
node _T_963 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 380:36]
|
|
_T_776[30] <= _T_963 @[el2_lib.scala 380:30]
|
|
node _T_964 = bits(ic_miss_buff_half, 56, 56) @[el2_lib.scala 381:36]
|
|
_T_777[30] <= _T_964 @[el2_lib.scala 381:30]
|
|
node _T_965 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 376:36]
|
|
_T_772[31] <= _T_965 @[el2_lib.scala 376:30]
|
|
node _T_966 = bits(ic_miss_buff_half, 57, 57) @[el2_lib.scala 382:36]
|
|
_T_778[0] <= _T_966 @[el2_lib.scala 382:30]
|
|
node _T_967 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 377:36]
|
|
_T_773[31] <= _T_967 @[el2_lib.scala 377:30]
|
|
node _T_968 = bits(ic_miss_buff_half, 58, 58) @[el2_lib.scala 382:36]
|
|
_T_778[1] <= _T_968 @[el2_lib.scala 382:30]
|
|
node _T_969 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 376:36]
|
|
_T_772[32] <= _T_969 @[el2_lib.scala 376:30]
|
|
node _T_970 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 377:36]
|
|
_T_773[32] <= _T_970 @[el2_lib.scala 377:30]
|
|
node _T_971 = bits(ic_miss_buff_half, 59, 59) @[el2_lib.scala 382:36]
|
|
_T_778[2] <= _T_971 @[el2_lib.scala 382:30]
|
|
node _T_972 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 378:36]
|
|
_T_774[31] <= _T_972 @[el2_lib.scala 378:30]
|
|
node _T_973 = bits(ic_miss_buff_half, 60, 60) @[el2_lib.scala 382:36]
|
|
_T_778[3] <= _T_973 @[el2_lib.scala 382:30]
|
|
node _T_974 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 376:36]
|
|
_T_772[33] <= _T_974 @[el2_lib.scala 376:30]
|
|
node _T_975 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 378:36]
|
|
_T_774[32] <= _T_975 @[el2_lib.scala 378:30]
|
|
node _T_976 = bits(ic_miss_buff_half, 61, 61) @[el2_lib.scala 382:36]
|
|
_T_778[4] <= _T_976 @[el2_lib.scala 382:30]
|
|
node _T_977 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 377:36]
|
|
_T_773[33] <= _T_977 @[el2_lib.scala 377:30]
|
|
node _T_978 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 378:36]
|
|
_T_774[33] <= _T_978 @[el2_lib.scala 378:30]
|
|
node _T_979 = bits(ic_miss_buff_half, 62, 62) @[el2_lib.scala 382:36]
|
|
_T_778[5] <= _T_979 @[el2_lib.scala 382:30]
|
|
node _T_980 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 376:36]
|
|
_T_772[34] <= _T_980 @[el2_lib.scala 376:30]
|
|
node _T_981 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 377:36]
|
|
_T_773[34] <= _T_981 @[el2_lib.scala 377:30]
|
|
node _T_982 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 378:36]
|
|
_T_774[34] <= _T_982 @[el2_lib.scala 378:30]
|
|
node _T_983 = bits(ic_miss_buff_half, 63, 63) @[el2_lib.scala 382:36]
|
|
_T_778[6] <= _T_983 @[el2_lib.scala 382:30]
|
|
node _T_984 = cat(_T_778[2], _T_778[1]) @[el2_lib.scala 384:13]
|
|
node _T_985 = cat(_T_984, _T_778[0]) @[el2_lib.scala 384:13]
|
|
node _T_986 = cat(_T_778[4], _T_778[3]) @[el2_lib.scala 384:13]
|
|
node _T_987 = cat(_T_778[6], _T_778[5]) @[el2_lib.scala 384:13]
|
|
node _T_988 = cat(_T_987, _T_986) @[el2_lib.scala 384:13]
|
|
node _T_989 = cat(_T_988, _T_985) @[el2_lib.scala 384:13]
|
|
node _T_990 = xorr(_T_989) @[el2_lib.scala 384:20]
|
|
node _T_991 = cat(_T_777[2], _T_777[1]) @[el2_lib.scala 384:30]
|
|
node _T_992 = cat(_T_991, _T_777[0]) @[el2_lib.scala 384:30]
|
|
node _T_993 = cat(_T_777[4], _T_777[3]) @[el2_lib.scala 384:30]
|
|
node _T_994 = cat(_T_777[6], _T_777[5]) @[el2_lib.scala 384:30]
|
|
node _T_995 = cat(_T_994, _T_993) @[el2_lib.scala 384:30]
|
|
node _T_996 = cat(_T_995, _T_992) @[el2_lib.scala 384:30]
|
|
node _T_997 = cat(_T_777[8], _T_777[7]) @[el2_lib.scala 384:30]
|
|
node _T_998 = cat(_T_777[10], _T_777[9]) @[el2_lib.scala 384:30]
|
|
node _T_999 = cat(_T_998, _T_997) @[el2_lib.scala 384:30]
|
|
node _T_1000 = cat(_T_777[12], _T_777[11]) @[el2_lib.scala 384:30]
|
|
node _T_1001 = cat(_T_777[14], _T_777[13]) @[el2_lib.scala 384:30]
|
|
node _T_1002 = cat(_T_1001, _T_1000) @[el2_lib.scala 384:30]
|
|
node _T_1003 = cat(_T_1002, _T_999) @[el2_lib.scala 384:30]
|
|
node _T_1004 = cat(_T_1003, _T_996) @[el2_lib.scala 384:30]
|
|
node _T_1005 = cat(_T_777[16], _T_777[15]) @[el2_lib.scala 384:30]
|
|
node _T_1006 = cat(_T_777[18], _T_777[17]) @[el2_lib.scala 384:30]
|
|
node _T_1007 = cat(_T_1006, _T_1005) @[el2_lib.scala 384:30]
|
|
node _T_1008 = cat(_T_777[20], _T_777[19]) @[el2_lib.scala 384:30]
|
|
node _T_1009 = cat(_T_777[22], _T_777[21]) @[el2_lib.scala 384:30]
|
|
node _T_1010 = cat(_T_1009, _T_1008) @[el2_lib.scala 384:30]
|
|
node _T_1011 = cat(_T_1010, _T_1007) @[el2_lib.scala 384:30]
|
|
node _T_1012 = cat(_T_777[24], _T_777[23]) @[el2_lib.scala 384:30]
|
|
node _T_1013 = cat(_T_777[26], _T_777[25]) @[el2_lib.scala 384:30]
|
|
node _T_1014 = cat(_T_1013, _T_1012) @[el2_lib.scala 384:30]
|
|
node _T_1015 = cat(_T_777[28], _T_777[27]) @[el2_lib.scala 384:30]
|
|
node _T_1016 = cat(_T_777[30], _T_777[29]) @[el2_lib.scala 384:30]
|
|
node _T_1017 = cat(_T_1016, _T_1015) @[el2_lib.scala 384:30]
|
|
node _T_1018 = cat(_T_1017, _T_1014) @[el2_lib.scala 384:30]
|
|
node _T_1019 = cat(_T_1018, _T_1011) @[el2_lib.scala 384:30]
|
|
node _T_1020 = cat(_T_1019, _T_1004) @[el2_lib.scala 384:30]
|
|
node _T_1021 = xorr(_T_1020) @[el2_lib.scala 384:37]
|
|
node _T_1022 = cat(_T_776[2], _T_776[1]) @[el2_lib.scala 384:47]
|
|
node _T_1023 = cat(_T_1022, _T_776[0]) @[el2_lib.scala 384:47]
|
|
node _T_1024 = cat(_T_776[4], _T_776[3]) @[el2_lib.scala 384:47]
|
|
node _T_1025 = cat(_T_776[6], _T_776[5]) @[el2_lib.scala 384:47]
|
|
node _T_1026 = cat(_T_1025, _T_1024) @[el2_lib.scala 384:47]
|
|
node _T_1027 = cat(_T_1026, _T_1023) @[el2_lib.scala 384:47]
|
|
node _T_1028 = cat(_T_776[8], _T_776[7]) @[el2_lib.scala 384:47]
|
|
node _T_1029 = cat(_T_776[10], _T_776[9]) @[el2_lib.scala 384:47]
|
|
node _T_1030 = cat(_T_1029, _T_1028) @[el2_lib.scala 384:47]
|
|
node _T_1031 = cat(_T_776[12], _T_776[11]) @[el2_lib.scala 384:47]
|
|
node _T_1032 = cat(_T_776[14], _T_776[13]) @[el2_lib.scala 384:47]
|
|
node _T_1033 = cat(_T_1032, _T_1031) @[el2_lib.scala 384:47]
|
|
node _T_1034 = cat(_T_1033, _T_1030) @[el2_lib.scala 384:47]
|
|
node _T_1035 = cat(_T_1034, _T_1027) @[el2_lib.scala 384:47]
|
|
node _T_1036 = cat(_T_776[16], _T_776[15]) @[el2_lib.scala 384:47]
|
|
node _T_1037 = cat(_T_776[18], _T_776[17]) @[el2_lib.scala 384:47]
|
|
node _T_1038 = cat(_T_1037, _T_1036) @[el2_lib.scala 384:47]
|
|
node _T_1039 = cat(_T_776[20], _T_776[19]) @[el2_lib.scala 384:47]
|
|
node _T_1040 = cat(_T_776[22], _T_776[21]) @[el2_lib.scala 384:47]
|
|
node _T_1041 = cat(_T_1040, _T_1039) @[el2_lib.scala 384:47]
|
|
node _T_1042 = cat(_T_1041, _T_1038) @[el2_lib.scala 384:47]
|
|
node _T_1043 = cat(_T_776[24], _T_776[23]) @[el2_lib.scala 384:47]
|
|
node _T_1044 = cat(_T_776[26], _T_776[25]) @[el2_lib.scala 384:47]
|
|
node _T_1045 = cat(_T_1044, _T_1043) @[el2_lib.scala 384:47]
|
|
node _T_1046 = cat(_T_776[28], _T_776[27]) @[el2_lib.scala 384:47]
|
|
node _T_1047 = cat(_T_776[30], _T_776[29]) @[el2_lib.scala 384:47]
|
|
node _T_1048 = cat(_T_1047, _T_1046) @[el2_lib.scala 384:47]
|
|
node _T_1049 = cat(_T_1048, _T_1045) @[el2_lib.scala 384:47]
|
|
node _T_1050 = cat(_T_1049, _T_1042) @[el2_lib.scala 384:47]
|
|
node _T_1051 = cat(_T_1050, _T_1035) @[el2_lib.scala 384:47]
|
|
node _T_1052 = xorr(_T_1051) @[el2_lib.scala 384:54]
|
|
node _T_1053 = cat(_T_775[2], _T_775[1]) @[el2_lib.scala 384:64]
|
|
node _T_1054 = cat(_T_1053, _T_775[0]) @[el2_lib.scala 384:64]
|
|
node _T_1055 = cat(_T_775[4], _T_775[3]) @[el2_lib.scala 384:64]
|
|
node _T_1056 = cat(_T_775[6], _T_775[5]) @[el2_lib.scala 384:64]
|
|
node _T_1057 = cat(_T_1056, _T_1055) @[el2_lib.scala 384:64]
|
|
node _T_1058 = cat(_T_1057, _T_1054) @[el2_lib.scala 384:64]
|
|
node _T_1059 = cat(_T_775[8], _T_775[7]) @[el2_lib.scala 384:64]
|
|
node _T_1060 = cat(_T_775[10], _T_775[9]) @[el2_lib.scala 384:64]
|
|
node _T_1061 = cat(_T_1060, _T_1059) @[el2_lib.scala 384:64]
|
|
node _T_1062 = cat(_T_775[12], _T_775[11]) @[el2_lib.scala 384:64]
|
|
node _T_1063 = cat(_T_775[14], _T_775[13]) @[el2_lib.scala 384:64]
|
|
node _T_1064 = cat(_T_1063, _T_1062) @[el2_lib.scala 384:64]
|
|
node _T_1065 = cat(_T_1064, _T_1061) @[el2_lib.scala 384:64]
|
|
node _T_1066 = cat(_T_1065, _T_1058) @[el2_lib.scala 384:64]
|
|
node _T_1067 = cat(_T_775[16], _T_775[15]) @[el2_lib.scala 384:64]
|
|
node _T_1068 = cat(_T_775[18], _T_775[17]) @[el2_lib.scala 384:64]
|
|
node _T_1069 = cat(_T_1068, _T_1067) @[el2_lib.scala 384:64]
|
|
node _T_1070 = cat(_T_775[20], _T_775[19]) @[el2_lib.scala 384:64]
|
|
node _T_1071 = cat(_T_775[22], _T_775[21]) @[el2_lib.scala 384:64]
|
|
node _T_1072 = cat(_T_1071, _T_1070) @[el2_lib.scala 384:64]
|
|
node _T_1073 = cat(_T_1072, _T_1069) @[el2_lib.scala 384:64]
|
|
node _T_1074 = cat(_T_775[24], _T_775[23]) @[el2_lib.scala 384:64]
|
|
node _T_1075 = cat(_T_775[26], _T_775[25]) @[el2_lib.scala 384:64]
|
|
node _T_1076 = cat(_T_1075, _T_1074) @[el2_lib.scala 384:64]
|
|
node _T_1077 = cat(_T_775[28], _T_775[27]) @[el2_lib.scala 384:64]
|
|
node _T_1078 = cat(_T_775[30], _T_775[29]) @[el2_lib.scala 384:64]
|
|
node _T_1079 = cat(_T_1078, _T_1077) @[el2_lib.scala 384:64]
|
|
node _T_1080 = cat(_T_1079, _T_1076) @[el2_lib.scala 384:64]
|
|
node _T_1081 = cat(_T_1080, _T_1073) @[el2_lib.scala 384:64]
|
|
node _T_1082 = cat(_T_1081, _T_1066) @[el2_lib.scala 384:64]
|
|
node _T_1083 = xorr(_T_1082) @[el2_lib.scala 384:71]
|
|
node _T_1084 = cat(_T_774[1], _T_774[0]) @[el2_lib.scala 384:81]
|
|
node _T_1085 = cat(_T_774[3], _T_774[2]) @[el2_lib.scala 384:81]
|
|
node _T_1086 = cat(_T_1085, _T_1084) @[el2_lib.scala 384:81]
|
|
node _T_1087 = cat(_T_774[5], _T_774[4]) @[el2_lib.scala 384:81]
|
|
node _T_1088 = cat(_T_774[7], _T_774[6]) @[el2_lib.scala 384:81]
|
|
node _T_1089 = cat(_T_1088, _T_1087) @[el2_lib.scala 384:81]
|
|
node _T_1090 = cat(_T_1089, _T_1086) @[el2_lib.scala 384:81]
|
|
node _T_1091 = cat(_T_774[9], _T_774[8]) @[el2_lib.scala 384:81]
|
|
node _T_1092 = cat(_T_774[11], _T_774[10]) @[el2_lib.scala 384:81]
|
|
node _T_1093 = cat(_T_1092, _T_1091) @[el2_lib.scala 384:81]
|
|
node _T_1094 = cat(_T_774[13], _T_774[12]) @[el2_lib.scala 384:81]
|
|
node _T_1095 = cat(_T_774[16], _T_774[15]) @[el2_lib.scala 384:81]
|
|
node _T_1096 = cat(_T_1095, _T_774[14]) @[el2_lib.scala 384:81]
|
|
node _T_1097 = cat(_T_1096, _T_1094) @[el2_lib.scala 384:81]
|
|
node _T_1098 = cat(_T_1097, _T_1093) @[el2_lib.scala 384:81]
|
|
node _T_1099 = cat(_T_1098, _T_1090) @[el2_lib.scala 384:81]
|
|
node _T_1100 = cat(_T_774[18], _T_774[17]) @[el2_lib.scala 384:81]
|
|
node _T_1101 = cat(_T_774[20], _T_774[19]) @[el2_lib.scala 384:81]
|
|
node _T_1102 = cat(_T_1101, _T_1100) @[el2_lib.scala 384:81]
|
|
node _T_1103 = cat(_T_774[22], _T_774[21]) @[el2_lib.scala 384:81]
|
|
node _T_1104 = cat(_T_774[25], _T_774[24]) @[el2_lib.scala 384:81]
|
|
node _T_1105 = cat(_T_1104, _T_774[23]) @[el2_lib.scala 384:81]
|
|
node _T_1106 = cat(_T_1105, _T_1103) @[el2_lib.scala 384:81]
|
|
node _T_1107 = cat(_T_1106, _T_1102) @[el2_lib.scala 384:81]
|
|
node _T_1108 = cat(_T_774[27], _T_774[26]) @[el2_lib.scala 384:81]
|
|
node _T_1109 = cat(_T_774[29], _T_774[28]) @[el2_lib.scala 384:81]
|
|
node _T_1110 = cat(_T_1109, _T_1108) @[el2_lib.scala 384:81]
|
|
node _T_1111 = cat(_T_774[31], _T_774[30]) @[el2_lib.scala 384:81]
|
|
node _T_1112 = cat(_T_774[34], _T_774[33]) @[el2_lib.scala 384:81]
|
|
node _T_1113 = cat(_T_1112, _T_774[32]) @[el2_lib.scala 384:81]
|
|
node _T_1114 = cat(_T_1113, _T_1111) @[el2_lib.scala 384:81]
|
|
node _T_1115 = cat(_T_1114, _T_1110) @[el2_lib.scala 384:81]
|
|
node _T_1116 = cat(_T_1115, _T_1107) @[el2_lib.scala 384:81]
|
|
node _T_1117 = cat(_T_1116, _T_1099) @[el2_lib.scala 384:81]
|
|
node _T_1118 = xorr(_T_1117) @[el2_lib.scala 384:88]
|
|
node _T_1119 = cat(_T_773[1], _T_773[0]) @[el2_lib.scala 384:98]
|
|
node _T_1120 = cat(_T_773[3], _T_773[2]) @[el2_lib.scala 384:98]
|
|
node _T_1121 = cat(_T_1120, _T_1119) @[el2_lib.scala 384:98]
|
|
node _T_1122 = cat(_T_773[5], _T_773[4]) @[el2_lib.scala 384:98]
|
|
node _T_1123 = cat(_T_773[7], _T_773[6]) @[el2_lib.scala 384:98]
|
|
node _T_1124 = cat(_T_1123, _T_1122) @[el2_lib.scala 384:98]
|
|
node _T_1125 = cat(_T_1124, _T_1121) @[el2_lib.scala 384:98]
|
|
node _T_1126 = cat(_T_773[9], _T_773[8]) @[el2_lib.scala 384:98]
|
|
node _T_1127 = cat(_T_773[11], _T_773[10]) @[el2_lib.scala 384:98]
|
|
node _T_1128 = cat(_T_1127, _T_1126) @[el2_lib.scala 384:98]
|
|
node _T_1129 = cat(_T_773[13], _T_773[12]) @[el2_lib.scala 384:98]
|
|
node _T_1130 = cat(_T_773[16], _T_773[15]) @[el2_lib.scala 384:98]
|
|
node _T_1131 = cat(_T_1130, _T_773[14]) @[el2_lib.scala 384:98]
|
|
node _T_1132 = cat(_T_1131, _T_1129) @[el2_lib.scala 384:98]
|
|
node _T_1133 = cat(_T_1132, _T_1128) @[el2_lib.scala 384:98]
|
|
node _T_1134 = cat(_T_1133, _T_1125) @[el2_lib.scala 384:98]
|
|
node _T_1135 = cat(_T_773[18], _T_773[17]) @[el2_lib.scala 384:98]
|
|
node _T_1136 = cat(_T_773[20], _T_773[19]) @[el2_lib.scala 384:98]
|
|
node _T_1137 = cat(_T_1136, _T_1135) @[el2_lib.scala 384:98]
|
|
node _T_1138 = cat(_T_773[22], _T_773[21]) @[el2_lib.scala 384:98]
|
|
node _T_1139 = cat(_T_773[25], _T_773[24]) @[el2_lib.scala 384:98]
|
|
node _T_1140 = cat(_T_1139, _T_773[23]) @[el2_lib.scala 384:98]
|
|
node _T_1141 = cat(_T_1140, _T_1138) @[el2_lib.scala 384:98]
|
|
node _T_1142 = cat(_T_1141, _T_1137) @[el2_lib.scala 384:98]
|
|
node _T_1143 = cat(_T_773[27], _T_773[26]) @[el2_lib.scala 384:98]
|
|
node _T_1144 = cat(_T_773[29], _T_773[28]) @[el2_lib.scala 384:98]
|
|
node _T_1145 = cat(_T_1144, _T_1143) @[el2_lib.scala 384:98]
|
|
node _T_1146 = cat(_T_773[31], _T_773[30]) @[el2_lib.scala 384:98]
|
|
node _T_1147 = cat(_T_773[34], _T_773[33]) @[el2_lib.scala 384:98]
|
|
node _T_1148 = cat(_T_1147, _T_773[32]) @[el2_lib.scala 384:98]
|
|
node _T_1149 = cat(_T_1148, _T_1146) @[el2_lib.scala 384:98]
|
|
node _T_1150 = cat(_T_1149, _T_1145) @[el2_lib.scala 384:98]
|
|
node _T_1151 = cat(_T_1150, _T_1142) @[el2_lib.scala 384:98]
|
|
node _T_1152 = cat(_T_1151, _T_1134) @[el2_lib.scala 384:98]
|
|
node _T_1153 = xorr(_T_1152) @[el2_lib.scala 384:105]
|
|
node _T_1154 = cat(_T_772[1], _T_772[0]) @[el2_lib.scala 384:115]
|
|
node _T_1155 = cat(_T_772[3], _T_772[2]) @[el2_lib.scala 384:115]
|
|
node _T_1156 = cat(_T_1155, _T_1154) @[el2_lib.scala 384:115]
|
|
node _T_1157 = cat(_T_772[5], _T_772[4]) @[el2_lib.scala 384:115]
|
|
node _T_1158 = cat(_T_772[7], _T_772[6]) @[el2_lib.scala 384:115]
|
|
node _T_1159 = cat(_T_1158, _T_1157) @[el2_lib.scala 384:115]
|
|
node _T_1160 = cat(_T_1159, _T_1156) @[el2_lib.scala 384:115]
|
|
node _T_1161 = cat(_T_772[9], _T_772[8]) @[el2_lib.scala 384:115]
|
|
node _T_1162 = cat(_T_772[11], _T_772[10]) @[el2_lib.scala 384:115]
|
|
node _T_1163 = cat(_T_1162, _T_1161) @[el2_lib.scala 384:115]
|
|
node _T_1164 = cat(_T_772[13], _T_772[12]) @[el2_lib.scala 384:115]
|
|
node _T_1165 = cat(_T_772[16], _T_772[15]) @[el2_lib.scala 384:115]
|
|
node _T_1166 = cat(_T_1165, _T_772[14]) @[el2_lib.scala 384:115]
|
|
node _T_1167 = cat(_T_1166, _T_1164) @[el2_lib.scala 384:115]
|
|
node _T_1168 = cat(_T_1167, _T_1163) @[el2_lib.scala 384:115]
|
|
node _T_1169 = cat(_T_1168, _T_1160) @[el2_lib.scala 384:115]
|
|
node _T_1170 = cat(_T_772[18], _T_772[17]) @[el2_lib.scala 384:115]
|
|
node _T_1171 = cat(_T_772[20], _T_772[19]) @[el2_lib.scala 384:115]
|
|
node _T_1172 = cat(_T_1171, _T_1170) @[el2_lib.scala 384:115]
|
|
node _T_1173 = cat(_T_772[22], _T_772[21]) @[el2_lib.scala 384:115]
|
|
node _T_1174 = cat(_T_772[25], _T_772[24]) @[el2_lib.scala 384:115]
|
|
node _T_1175 = cat(_T_1174, _T_772[23]) @[el2_lib.scala 384:115]
|
|
node _T_1176 = cat(_T_1175, _T_1173) @[el2_lib.scala 384:115]
|
|
node _T_1177 = cat(_T_1176, _T_1172) @[el2_lib.scala 384:115]
|
|
node _T_1178 = cat(_T_772[27], _T_772[26]) @[el2_lib.scala 384:115]
|
|
node _T_1179 = cat(_T_772[29], _T_772[28]) @[el2_lib.scala 384:115]
|
|
node _T_1180 = cat(_T_1179, _T_1178) @[el2_lib.scala 384:115]
|
|
node _T_1181 = cat(_T_772[31], _T_772[30]) @[el2_lib.scala 384:115]
|
|
node _T_1182 = cat(_T_772[34], _T_772[33]) @[el2_lib.scala 384:115]
|
|
node _T_1183 = cat(_T_1182, _T_772[32]) @[el2_lib.scala 384:115]
|
|
node _T_1184 = cat(_T_1183, _T_1181) @[el2_lib.scala 384:115]
|
|
node _T_1185 = cat(_T_1184, _T_1180) @[el2_lib.scala 384:115]
|
|
node _T_1186 = cat(_T_1185, _T_1177) @[el2_lib.scala 384:115]
|
|
node _T_1187 = cat(_T_1186, _T_1169) @[el2_lib.scala 384:115]
|
|
node _T_1188 = xorr(_T_1187) @[el2_lib.scala 384:122]
|
|
node _T_1189 = cat(_T_1118, _T_1153) @[Cat.scala 29:58]
|
|
node _T_1190 = cat(_T_1189, _T_1188) @[Cat.scala 29:58]
|
|
node _T_1191 = cat(_T_1052, _T_1083) @[Cat.scala 29:58]
|
|
node _T_1192 = cat(_T_990, _T_1021) @[Cat.scala 29:58]
|
|
node _T_1193 = cat(_T_1192, _T_1191) @[Cat.scala 29:58]
|
|
node ic_miss_buff_ecc = cat(_T_1193, _T_1190) @[Cat.scala 29:58]
|
|
wire ic_wr_16bytes_data : UInt<142>
|
|
ic_wr_16bytes_data <= UInt<1>("h00")
|
|
node _T_1194 = bits(ic_wr_16bytes_data, 70, 0) @[el2_ifu_mem_ctl.scala 346:72]
|
|
node _T_1195 = bits(ic_wr_16bytes_data, 141, 71) @[el2_ifu_mem_ctl.scala 346:72]
|
|
io.ic_wr_data[0] <= _T_1194 @[el2_ifu_mem_ctl.scala 346:17]
|
|
io.ic_wr_data[1] <= _T_1195 @[el2_ifu_mem_ctl.scala 346:17]
|
|
io.ic_debug_wr_data <= io.dec_tlu_ic_diag_pkt.icache_wrdata @[el2_ifu_mem_ctl.scala 347:23]
|
|
wire ic_rd_parity_final_err : UInt<1>
|
|
ic_rd_parity_final_err <= UInt<1>("h00")
|
|
node _T_1196 = orr(io.ic_eccerr) @[el2_ifu_mem_ctl.scala 349:56]
|
|
node _T_1197 = and(_T_1196, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 349:83]
|
|
node _T_1198 = or(_T_1197, ic_rd_parity_final_err) @[el2_ifu_mem_ctl.scala 349:99]
|
|
io.ic_error_start <= _T_1198 @[el2_ifu_mem_ctl.scala 349:21]
|
|
wire ic_debug_tag_val_rd_out : UInt<1>
|
|
ic_debug_tag_val_rd_out <= UInt<1>("h00")
|
|
wire ic_debug_ict_array_sel_ff : UInt<1>
|
|
ic_debug_ict_array_sel_ff <= UInt<1>("h00")
|
|
node _T_1199 = bits(ic_debug_ict_array_sel_ff, 0, 0) @[el2_ifu_mem_ctl.scala 352:63]
|
|
node _T_1200 = bits(io.ictag_debug_rd_data, 25, 21) @[el2_ifu_mem_ctl.scala 352:121]
|
|
node _T_1201 = bits(io.ictag_debug_rd_data, 20, 0) @[el2_ifu_mem_ctl.scala 352:161]
|
|
node _T_1202 = cat(UInt<3>("h00"), ic_debug_tag_val_rd_out) @[Cat.scala 29:58]
|
|
node _T_1203 = cat(UInt<1>("h00"), way_status) @[Cat.scala 29:58]
|
|
node _T_1204 = cat(_T_1203, _T_1202) @[Cat.scala 29:58]
|
|
node _T_1205 = cat(UInt<32>("h00"), _T_1201) @[Cat.scala 29:58]
|
|
node _T_1206 = cat(UInt<2>("h00"), _T_1200) @[Cat.scala 29:58]
|
|
node _T_1207 = cat(_T_1206, _T_1205) @[Cat.scala 29:58]
|
|
node _T_1208 = cat(_T_1207, _T_1204) @[Cat.scala 29:58]
|
|
node ifu_ic_debug_rd_data_in = mux(_T_1199, _T_1208, io.ic_debug_rd_data) @[el2_ifu_mem_ctl.scala 352:36]
|
|
reg _T_1209 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when ic_debug_rd_en_ff : @[Reg.scala 28:19]
|
|
_T_1209 <= ifu_ic_debug_rd_data_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
io.ifu_ic_debug_rd_data <= _T_1209 @[el2_ifu_mem_ctl.scala 355:27]
|
|
node _T_1210 = bits(ifu_bus_rdata_ff, 15, 0) @[el2_ifu_mem_ctl.scala 356:74]
|
|
node _T_1211 = xorr(_T_1210) @[el2_lib.scala 208:13]
|
|
node _T_1212 = bits(ifu_bus_rdata_ff, 31, 16) @[el2_ifu_mem_ctl.scala 356:74]
|
|
node _T_1213 = xorr(_T_1212) @[el2_lib.scala 208:13]
|
|
node _T_1214 = bits(ifu_bus_rdata_ff, 47, 32) @[el2_ifu_mem_ctl.scala 356:74]
|
|
node _T_1215 = xorr(_T_1214) @[el2_lib.scala 208:13]
|
|
node _T_1216 = bits(ifu_bus_rdata_ff, 63, 48) @[el2_ifu_mem_ctl.scala 356:74]
|
|
node _T_1217 = xorr(_T_1216) @[el2_lib.scala 208:13]
|
|
node _T_1218 = cat(_T_1217, _T_1215) @[Cat.scala 29:58]
|
|
node _T_1219 = cat(_T_1218, _T_1213) @[Cat.scala 29:58]
|
|
node ic_wr_parity = cat(_T_1219, _T_1211) @[Cat.scala 29:58]
|
|
node _T_1220 = bits(ic_miss_buff_half, 15, 0) @[el2_ifu_mem_ctl.scala 357:82]
|
|
node _T_1221 = xorr(_T_1220) @[el2_lib.scala 208:13]
|
|
node _T_1222 = bits(ic_miss_buff_half, 31, 16) @[el2_ifu_mem_ctl.scala 357:82]
|
|
node _T_1223 = xorr(_T_1222) @[el2_lib.scala 208:13]
|
|
node _T_1224 = bits(ic_miss_buff_half, 47, 32) @[el2_ifu_mem_ctl.scala 357:82]
|
|
node _T_1225 = xorr(_T_1224) @[el2_lib.scala 208:13]
|
|
node _T_1226 = bits(ic_miss_buff_half, 63, 48) @[el2_ifu_mem_ctl.scala 357:82]
|
|
node _T_1227 = xorr(_T_1226) @[el2_lib.scala 208:13]
|
|
node _T_1228 = cat(_T_1227, _T_1225) @[Cat.scala 29:58]
|
|
node _T_1229 = cat(_T_1228, _T_1223) @[Cat.scala 29:58]
|
|
node ic_miss_buff_parity = cat(_T_1229, _T_1221) @[Cat.scala 29:58]
|
|
node _T_1230 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 359:43]
|
|
node _T_1231 = bits(_T_1230, 0, 0) @[el2_ifu_mem_ctl.scala 359:47]
|
|
node _T_1232 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58]
|
|
node _T_1233 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58]
|
|
node _T_1234 = cat(_T_1233, _T_1232) @[Cat.scala 29:58]
|
|
node _T_1235 = cat(ic_wr_ecc, ifu_bus_rdata_ff) @[Cat.scala 29:58]
|
|
node _T_1236 = cat(ic_miss_buff_ecc, ic_miss_buff_half) @[Cat.scala 29:58]
|
|
node _T_1237 = cat(_T_1236, _T_1235) @[Cat.scala 29:58]
|
|
node _T_1238 = mux(_T_1231, _T_1234, _T_1237) @[el2_ifu_mem_ctl.scala 359:28]
|
|
ic_wr_16bytes_data <= _T_1238 @[el2_ifu_mem_ctl.scala 359:22]
|
|
wire bus_ifu_wr_data_error_ff : UInt<1>
|
|
bus_ifu_wr_data_error_ff <= UInt<1>("h00")
|
|
wire ifu_wr_data_comb_err_ff : UInt<1>
|
|
ifu_wr_data_comb_err_ff <= UInt<1>("h00")
|
|
wire reset_beat_cnt : UInt<1>
|
|
reset_beat_cnt <= UInt<1>("h00")
|
|
node _T_1239 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 366:53]
|
|
node _T_1240 = eq(reset_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 366:82]
|
|
node ifu_wr_cumulative_err = and(_T_1239, _T_1240) @[el2_ifu_mem_ctl.scala 366:80]
|
|
node _T_1241 = or(bus_ifu_wr_data_error_ff, ifu_wr_data_comb_err_ff) @[el2_ifu_mem_ctl.scala 367:55]
|
|
ifu_wr_cumulative_err_data <= _T_1241 @[el2_ifu_mem_ctl.scala 367:30]
|
|
reg _T_1242 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 368:61]
|
|
_T_1242 <= ifu_wr_cumulative_err @[el2_ifu_mem_ctl.scala 368:61]
|
|
ifu_wr_data_comb_err_ff <= _T_1242 @[el2_ifu_mem_ctl.scala 368:27]
|
|
wire ic_crit_wd_rdy : UInt<1>
|
|
ic_crit_wd_rdy <= UInt<1>("h00")
|
|
wire ifu_byp_data_err_new : UInt<1>
|
|
ifu_byp_data_err_new <= UInt<1>("h00")
|
|
node _T_1243 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 371:51]
|
|
node _T_1244 = or(ic_crit_wd_rdy, _T_1243) @[el2_ifu_mem_ctl.scala 371:38]
|
|
node _T_1245 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 371:77]
|
|
node _T_1246 = or(_T_1244, _T_1245) @[el2_ifu_mem_ctl.scala 371:64]
|
|
node _T_1247 = eq(ifu_byp_data_err_new, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 371:98]
|
|
node sel_byp_data = and(_T_1246, _T_1247) @[el2_ifu_mem_ctl.scala 371:96]
|
|
node _T_1248 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 372:51]
|
|
node _T_1249 = or(ic_crit_wd_rdy, _T_1248) @[el2_ifu_mem_ctl.scala 372:38]
|
|
node _T_1250 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 372:77]
|
|
node _T_1251 = or(_T_1249, _T_1250) @[el2_ifu_mem_ctl.scala 372:64]
|
|
node _T_1252 = eq(_T_1251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 372:21]
|
|
node _T_1253 = eq(fetch_req_iccm_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 372:98]
|
|
node sel_ic_data = and(_T_1252, _T_1253) @[el2_ifu_mem_ctl.scala 372:96]
|
|
wire ic_byp_data_only_new : UInt<80>
|
|
ic_byp_data_only_new <= UInt<1>("h00")
|
|
node _T_1254 = or(fetch_req_iccm_f, sel_ic_data) @[el2_ifu_mem_ctl.scala 376:81]
|
|
node _T_1255 = or(sel_byp_data, _T_1254) @[el2_ifu_mem_ctl.scala 376:47]
|
|
node _T_1256 = bits(_T_1255, 0, 0) @[el2_ifu_mem_ctl.scala 376:140]
|
|
node _T_1257 = bits(fetch_req_iccm_f, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1258 = mux(_T_1257, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1259 = and(_T_1258, io.iccm_rd_data) @[el2_ifu_mem_ctl.scala 378:64]
|
|
node _T_1260 = bits(sel_byp_data, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_1261 = mux(_T_1260, UInt<64>("h0ffffffffffffffff"), UInt<64>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1262 = and(_T_1261, ic_byp_data_only_new) @[el2_ifu_mem_ctl.scala 378:109]
|
|
node ic_premux_data = or(_T_1259, _T_1262) @[el2_ifu_mem_ctl.scala 378:83]
|
|
node ic_sel_premux_data = or(fetch_req_iccm_f, sel_byp_data) @[el2_ifu_mem_ctl.scala 380:58]
|
|
io.ic_premux_data <= ic_premux_data @[el2_ifu_mem_ctl.scala 381:21]
|
|
io.ic_sel_premux_data <= ic_sel_premux_data @[el2_ifu_mem_ctl.scala 382:25]
|
|
node ifc_bus_acc_fault_f = and(ic_byp_hit_f, ifu_byp_data_err_new) @[el2_ifu_mem_ctl.scala 383:42]
|
|
io.ic_data_f <= io.ic_rd_data @[el2_ifu_mem_ctl.scala 384:16]
|
|
node _T_1263 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 385:40]
|
|
node fetch_req_f_qual = and(io.ic_hit_f, _T_1263) @[el2_ifu_mem_ctl.scala 385:38]
|
|
wire ifc_region_acc_fault_memory_f : UInt<1>
|
|
ifc_region_acc_fault_memory_f <= UInt<1>("h00")
|
|
node _T_1264 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 387:57]
|
|
node _T_1265 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 387:82]
|
|
node _T_1266 = and(_T_1264, _T_1265) @[el2_ifu_mem_ctl.scala 387:80]
|
|
io.ic_access_fault_f <= _T_1266 @[el2_ifu_mem_ctl.scala 387:24]
|
|
node _T_1267 = bits(io.iccm_rd_ecc_double_err, 0, 0) @[el2_ifu_mem_ctl.scala 388:62]
|
|
node _T_1268 = bits(ifc_region_acc_fault_f, 0, 0) @[el2_ifu_mem_ctl.scala 389:32]
|
|
node _T_1269 = bits(ifc_region_acc_fault_memory_f, 0, 0) @[el2_ifu_mem_ctl.scala 390:47]
|
|
node _T_1270 = mux(_T_1269, UInt<2>("h03"), UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 390:10]
|
|
node _T_1271 = mux(_T_1268, UInt<2>("h02"), _T_1270) @[el2_ifu_mem_ctl.scala 389:8]
|
|
node _T_1272 = mux(_T_1267, UInt<1>("h01"), _T_1271) @[el2_ifu_mem_ctl.scala 388:35]
|
|
io.ic_access_fault_type_f <= _T_1272 @[el2_ifu_mem_ctl.scala 388:29]
|
|
node _T_1273 = and(fetch_req_f_qual, io.ifu_bp_inst_mask_f) @[el2_ifu_mem_ctl.scala 391:45]
|
|
node _T_1274 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1275 = eq(vaddr_f, _T_1274) @[el2_ifu_mem_ctl.scala 391:80]
|
|
node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 391:71]
|
|
node _T_1277 = and(_T_1273, _T_1276) @[el2_ifu_mem_ctl.scala 391:69]
|
|
node _T_1278 = neq(err_stop_state, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 391:131]
|
|
node _T_1279 = and(_T_1277, _T_1278) @[el2_ifu_mem_ctl.scala 391:114]
|
|
node _T_1280 = cat(_T_1279, fetch_req_f_qual) @[Cat.scala 29:58]
|
|
io.ic_fetch_val_f <= _T_1280 @[el2_ifu_mem_ctl.scala 391:21]
|
|
node _T_1281 = bits(io.ic_data_f, 1, 0) @[el2_ifu_mem_ctl.scala 392:36]
|
|
node two_byte_instr = neq(_T_1281, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 392:42]
|
|
wire ic_miss_buff_data_in : UInt<64>
|
|
ic_miss_buff_data_in <= UInt<1>("h00")
|
|
wire ifu_bus_rsp_tag : UInt<3>
|
|
ifu_bus_rsp_tag <= UInt<1>("h00")
|
|
wire bus_ifu_wr_en : UInt<1>
|
|
bus_ifu_wr_en <= UInt<1>("h00")
|
|
node _T_1282 = eq(ifu_bus_rsp_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 398:91]
|
|
node write_fill_data_0 = and(bus_ifu_wr_en, _T_1282) @[el2_ifu_mem_ctl.scala 398:73]
|
|
node _T_1283 = eq(ifu_bus_rsp_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 398:91]
|
|
node write_fill_data_1 = and(bus_ifu_wr_en, _T_1283) @[el2_ifu_mem_ctl.scala 398:73]
|
|
node _T_1284 = eq(ifu_bus_rsp_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 398:91]
|
|
node write_fill_data_2 = and(bus_ifu_wr_en, _T_1284) @[el2_ifu_mem_ctl.scala 398:73]
|
|
node _T_1285 = eq(ifu_bus_rsp_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 398:91]
|
|
node write_fill_data_3 = and(bus_ifu_wr_en, _T_1285) @[el2_ifu_mem_ctl.scala 398:73]
|
|
node _T_1286 = eq(ifu_bus_rsp_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 398:91]
|
|
node write_fill_data_4 = and(bus_ifu_wr_en, _T_1286) @[el2_ifu_mem_ctl.scala 398:73]
|
|
node _T_1287 = eq(ifu_bus_rsp_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 398:91]
|
|
node write_fill_data_5 = and(bus_ifu_wr_en, _T_1287) @[el2_ifu_mem_ctl.scala 398:73]
|
|
node _T_1288 = eq(ifu_bus_rsp_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 398:91]
|
|
node write_fill_data_6 = and(bus_ifu_wr_en, _T_1288) @[el2_ifu_mem_ctl.scala 398:73]
|
|
node _T_1289 = eq(ifu_bus_rsp_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 398:91]
|
|
node write_fill_data_7 = and(bus_ifu_wr_en, _T_1289) @[el2_ifu_mem_ctl.scala 398:73]
|
|
wire ic_miss_buff_data : UInt<32>[16] @[el2_ifu_mem_ctl.scala 399:31]
|
|
node _T_1290 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 401:59]
|
|
node _T_1291 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 401:97]
|
|
reg _T_1292 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1291 : @[Reg.scala 28:19]
|
|
_T_1292 <= _T_1290 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[0] <= _T_1292 @[el2_ifu_mem_ctl.scala 401:26]
|
|
node _T_1293 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 402:61]
|
|
node _T_1294 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 402:100]
|
|
reg _T_1295 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1294 : @[Reg.scala 28:19]
|
|
_T_1295 <= _T_1293 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[1] <= _T_1295 @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1296 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 401:59]
|
|
node _T_1297 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 401:97]
|
|
reg _T_1298 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1297 : @[Reg.scala 28:19]
|
|
_T_1298 <= _T_1296 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[2] <= _T_1298 @[el2_ifu_mem_ctl.scala 401:26]
|
|
node _T_1299 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 402:61]
|
|
node _T_1300 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 402:100]
|
|
reg _T_1301 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1300 : @[Reg.scala 28:19]
|
|
_T_1301 <= _T_1299 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[3] <= _T_1301 @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1302 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 401:59]
|
|
node _T_1303 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 401:97]
|
|
reg _T_1304 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1303 : @[Reg.scala 28:19]
|
|
_T_1304 <= _T_1302 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[4] <= _T_1304 @[el2_ifu_mem_ctl.scala 401:26]
|
|
node _T_1305 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 402:61]
|
|
node _T_1306 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 402:100]
|
|
reg _T_1307 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1306 : @[Reg.scala 28:19]
|
|
_T_1307 <= _T_1305 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[5] <= _T_1307 @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1308 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 401:59]
|
|
node _T_1309 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 401:97]
|
|
reg _T_1310 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1309 : @[Reg.scala 28:19]
|
|
_T_1310 <= _T_1308 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[6] <= _T_1310 @[el2_ifu_mem_ctl.scala 401:26]
|
|
node _T_1311 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 402:61]
|
|
node _T_1312 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 402:100]
|
|
reg _T_1313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1312 : @[Reg.scala 28:19]
|
|
_T_1313 <= _T_1311 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[7] <= _T_1313 @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1314 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 401:59]
|
|
node _T_1315 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 401:97]
|
|
reg _T_1316 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1315 : @[Reg.scala 28:19]
|
|
_T_1316 <= _T_1314 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[8] <= _T_1316 @[el2_ifu_mem_ctl.scala 401:26]
|
|
node _T_1317 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 402:61]
|
|
node _T_1318 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 402:100]
|
|
reg _T_1319 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1318 : @[Reg.scala 28:19]
|
|
_T_1319 <= _T_1317 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[9] <= _T_1319 @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1320 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 401:59]
|
|
node _T_1321 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 401:97]
|
|
reg _T_1322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1321 : @[Reg.scala 28:19]
|
|
_T_1322 <= _T_1320 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[10] <= _T_1322 @[el2_ifu_mem_ctl.scala 401:26]
|
|
node _T_1323 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 402:61]
|
|
node _T_1324 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 402:100]
|
|
reg _T_1325 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1324 : @[Reg.scala 28:19]
|
|
_T_1325 <= _T_1323 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[11] <= _T_1325 @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1326 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 401:59]
|
|
node _T_1327 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 401:97]
|
|
reg _T_1328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1327 : @[Reg.scala 28:19]
|
|
_T_1328 <= _T_1326 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[12] <= _T_1328 @[el2_ifu_mem_ctl.scala 401:26]
|
|
node _T_1329 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 402:61]
|
|
node _T_1330 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 402:100]
|
|
reg _T_1331 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1330 : @[Reg.scala 28:19]
|
|
_T_1331 <= _T_1329 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[13] <= _T_1331 @[el2_ifu_mem_ctl.scala 402:28]
|
|
node _T_1332 = bits(ic_miss_buff_data_in, 31, 0) @[el2_ifu_mem_ctl.scala 401:59]
|
|
node _T_1333 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 401:97]
|
|
reg _T_1334 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1333 : @[Reg.scala 28:19]
|
|
_T_1334 <= _T_1332 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[14] <= _T_1334 @[el2_ifu_mem_ctl.scala 401:26]
|
|
node _T_1335 = bits(ic_miss_buff_data_in, 63, 32) @[el2_ifu_mem_ctl.scala 402:61]
|
|
node _T_1336 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 402:100]
|
|
reg _T_1337 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_1336 : @[Reg.scala 28:19]
|
|
_T_1337 <= _T_1335 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_miss_buff_data[15] <= _T_1337 @[el2_ifu_mem_ctl.scala 402:28]
|
|
wire ic_miss_buff_data_valid : UInt<8>
|
|
ic_miss_buff_data_valid <= UInt<1>("h00")
|
|
node _T_1338 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 404:113]
|
|
node _T_1339 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 404:118]
|
|
node _T_1340 = and(_T_1338, _T_1339) @[el2_ifu_mem_ctl.scala 404:116]
|
|
node ic_miss_buff_data_valid_in_0 = or(write_fill_data_0, _T_1340) @[el2_ifu_mem_ctl.scala 404:88]
|
|
node _T_1341 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 404:113]
|
|
node _T_1342 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 404:118]
|
|
node _T_1343 = and(_T_1341, _T_1342) @[el2_ifu_mem_ctl.scala 404:116]
|
|
node ic_miss_buff_data_valid_in_1 = or(write_fill_data_1, _T_1343) @[el2_ifu_mem_ctl.scala 404:88]
|
|
node _T_1344 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 404:113]
|
|
node _T_1345 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 404:118]
|
|
node _T_1346 = and(_T_1344, _T_1345) @[el2_ifu_mem_ctl.scala 404:116]
|
|
node ic_miss_buff_data_valid_in_2 = or(write_fill_data_2, _T_1346) @[el2_ifu_mem_ctl.scala 404:88]
|
|
node _T_1347 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 404:113]
|
|
node _T_1348 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 404:118]
|
|
node _T_1349 = and(_T_1347, _T_1348) @[el2_ifu_mem_ctl.scala 404:116]
|
|
node ic_miss_buff_data_valid_in_3 = or(write_fill_data_3, _T_1349) @[el2_ifu_mem_ctl.scala 404:88]
|
|
node _T_1350 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 404:113]
|
|
node _T_1351 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 404:118]
|
|
node _T_1352 = and(_T_1350, _T_1351) @[el2_ifu_mem_ctl.scala 404:116]
|
|
node ic_miss_buff_data_valid_in_4 = or(write_fill_data_4, _T_1352) @[el2_ifu_mem_ctl.scala 404:88]
|
|
node _T_1353 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 404:113]
|
|
node _T_1354 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 404:118]
|
|
node _T_1355 = and(_T_1353, _T_1354) @[el2_ifu_mem_ctl.scala 404:116]
|
|
node ic_miss_buff_data_valid_in_5 = or(write_fill_data_5, _T_1355) @[el2_ifu_mem_ctl.scala 404:88]
|
|
node _T_1356 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 404:113]
|
|
node _T_1357 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 404:118]
|
|
node _T_1358 = and(_T_1356, _T_1357) @[el2_ifu_mem_ctl.scala 404:116]
|
|
node ic_miss_buff_data_valid_in_6 = or(write_fill_data_6, _T_1358) @[el2_ifu_mem_ctl.scala 404:88]
|
|
node _T_1359 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 404:113]
|
|
node _T_1360 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 404:118]
|
|
node _T_1361 = and(_T_1359, _T_1360) @[el2_ifu_mem_ctl.scala 404:116]
|
|
node ic_miss_buff_data_valid_in_7 = or(write_fill_data_7, _T_1361) @[el2_ifu_mem_ctl.scala 404:88]
|
|
node _T_1362 = cat(ic_miss_buff_data_valid_in_7, ic_miss_buff_data_valid_in_6) @[Cat.scala 29:58]
|
|
node _T_1363 = cat(_T_1362, ic_miss_buff_data_valid_in_5) @[Cat.scala 29:58]
|
|
node _T_1364 = cat(_T_1363, ic_miss_buff_data_valid_in_4) @[Cat.scala 29:58]
|
|
node _T_1365 = cat(_T_1364, ic_miss_buff_data_valid_in_3) @[Cat.scala 29:58]
|
|
node _T_1366 = cat(_T_1365, ic_miss_buff_data_valid_in_2) @[Cat.scala 29:58]
|
|
node _T_1367 = cat(_T_1366, ic_miss_buff_data_valid_in_1) @[Cat.scala 29:58]
|
|
node _T_1368 = cat(_T_1367, ic_miss_buff_data_valid_in_0) @[Cat.scala 29:58]
|
|
reg _T_1369 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 405:60]
|
|
_T_1369 <= _T_1368 @[el2_ifu_mem_ctl.scala 405:60]
|
|
ic_miss_buff_data_valid <= _T_1369 @[el2_ifu_mem_ctl.scala 405:27]
|
|
wire bus_ifu_wr_data_error : UInt<1>
|
|
bus_ifu_wr_data_error <= UInt<1>("h00")
|
|
wire ic_miss_buff_data_error : UInt<8>
|
|
ic_miss_buff_data_error <= UInt<1>("h00")
|
|
node _T_1370 = bits(write_fill_data_0, 0, 0) @[el2_ifu_mem_ctl.scala 408:92]
|
|
node _T_1371 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 409:28]
|
|
node _T_1372 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:34]
|
|
node _T_1373 = and(_T_1371, _T_1372) @[el2_ifu_mem_ctl.scala 409:32]
|
|
node ic_miss_buff_data_error_in_0 = mux(_T_1370, bus_ifu_wr_data_error, _T_1373) @[el2_ifu_mem_ctl.scala 408:72]
|
|
node _T_1374 = bits(write_fill_data_1, 0, 0) @[el2_ifu_mem_ctl.scala 408:92]
|
|
node _T_1375 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 409:28]
|
|
node _T_1376 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:34]
|
|
node _T_1377 = and(_T_1375, _T_1376) @[el2_ifu_mem_ctl.scala 409:32]
|
|
node ic_miss_buff_data_error_in_1 = mux(_T_1374, bus_ifu_wr_data_error, _T_1377) @[el2_ifu_mem_ctl.scala 408:72]
|
|
node _T_1378 = bits(write_fill_data_2, 0, 0) @[el2_ifu_mem_ctl.scala 408:92]
|
|
node _T_1379 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 409:28]
|
|
node _T_1380 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:34]
|
|
node _T_1381 = and(_T_1379, _T_1380) @[el2_ifu_mem_ctl.scala 409:32]
|
|
node ic_miss_buff_data_error_in_2 = mux(_T_1378, bus_ifu_wr_data_error, _T_1381) @[el2_ifu_mem_ctl.scala 408:72]
|
|
node _T_1382 = bits(write_fill_data_3, 0, 0) @[el2_ifu_mem_ctl.scala 408:92]
|
|
node _T_1383 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 409:28]
|
|
node _T_1384 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:34]
|
|
node _T_1385 = and(_T_1383, _T_1384) @[el2_ifu_mem_ctl.scala 409:32]
|
|
node ic_miss_buff_data_error_in_3 = mux(_T_1382, bus_ifu_wr_data_error, _T_1385) @[el2_ifu_mem_ctl.scala 408:72]
|
|
node _T_1386 = bits(write_fill_data_4, 0, 0) @[el2_ifu_mem_ctl.scala 408:92]
|
|
node _T_1387 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 409:28]
|
|
node _T_1388 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:34]
|
|
node _T_1389 = and(_T_1387, _T_1388) @[el2_ifu_mem_ctl.scala 409:32]
|
|
node ic_miss_buff_data_error_in_4 = mux(_T_1386, bus_ifu_wr_data_error, _T_1389) @[el2_ifu_mem_ctl.scala 408:72]
|
|
node _T_1390 = bits(write_fill_data_5, 0, 0) @[el2_ifu_mem_ctl.scala 408:92]
|
|
node _T_1391 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 409:28]
|
|
node _T_1392 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:34]
|
|
node _T_1393 = and(_T_1391, _T_1392) @[el2_ifu_mem_ctl.scala 409:32]
|
|
node ic_miss_buff_data_error_in_5 = mux(_T_1390, bus_ifu_wr_data_error, _T_1393) @[el2_ifu_mem_ctl.scala 408:72]
|
|
node _T_1394 = bits(write_fill_data_6, 0, 0) @[el2_ifu_mem_ctl.scala 408:92]
|
|
node _T_1395 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 409:28]
|
|
node _T_1396 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:34]
|
|
node _T_1397 = and(_T_1395, _T_1396) @[el2_ifu_mem_ctl.scala 409:32]
|
|
node ic_miss_buff_data_error_in_6 = mux(_T_1394, bus_ifu_wr_data_error, _T_1397) @[el2_ifu_mem_ctl.scala 408:72]
|
|
node _T_1398 = bits(write_fill_data_7, 0, 0) @[el2_ifu_mem_ctl.scala 408:92]
|
|
node _T_1399 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 409:28]
|
|
node _T_1400 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 409:34]
|
|
node _T_1401 = and(_T_1399, _T_1400) @[el2_ifu_mem_ctl.scala 409:32]
|
|
node ic_miss_buff_data_error_in_7 = mux(_T_1398, bus_ifu_wr_data_error, _T_1401) @[el2_ifu_mem_ctl.scala 408:72]
|
|
node _T_1402 = cat(ic_miss_buff_data_error_in_7, ic_miss_buff_data_error_in_6) @[Cat.scala 29:58]
|
|
node _T_1403 = cat(_T_1402, ic_miss_buff_data_error_in_5) @[Cat.scala 29:58]
|
|
node _T_1404 = cat(_T_1403, ic_miss_buff_data_error_in_4) @[Cat.scala 29:58]
|
|
node _T_1405 = cat(_T_1404, ic_miss_buff_data_error_in_3) @[Cat.scala 29:58]
|
|
node _T_1406 = cat(_T_1405, ic_miss_buff_data_error_in_2) @[Cat.scala 29:58]
|
|
node _T_1407 = cat(_T_1406, ic_miss_buff_data_error_in_1) @[Cat.scala 29:58]
|
|
node _T_1408 = cat(_T_1407, ic_miss_buff_data_error_in_0) @[Cat.scala 29:58]
|
|
reg _T_1409 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 410:60]
|
|
_T_1409 <= _T_1408 @[el2_ifu_mem_ctl.scala 410:60]
|
|
ic_miss_buff_data_error <= _T_1409 @[el2_ifu_mem_ctl.scala 410:27]
|
|
node bypass_index = bits(imb_ff, 4, 0) @[el2_ifu_mem_ctl.scala 413:28]
|
|
node _T_1410 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 414:42]
|
|
node _T_1411 = add(_T_1410, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 414:70]
|
|
node bypass_index_5_3_inc = tail(_T_1411, 1) @[el2_ifu_mem_ctl.scala 414:70]
|
|
node _T_1412 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:87]
|
|
node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 415:114]
|
|
node _T_1414 = bits(_T_1413, 0, 0) @[el2_ifu_mem_ctl.scala 415:122]
|
|
node _T_1415 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:87]
|
|
node _T_1416 = eq(_T_1415, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 415:114]
|
|
node _T_1417 = bits(_T_1416, 0, 0) @[el2_ifu_mem_ctl.scala 415:122]
|
|
node _T_1418 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:87]
|
|
node _T_1419 = eq(_T_1418, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 415:114]
|
|
node _T_1420 = bits(_T_1419, 0, 0) @[el2_ifu_mem_ctl.scala 415:122]
|
|
node _T_1421 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:87]
|
|
node _T_1422 = eq(_T_1421, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 415:114]
|
|
node _T_1423 = bits(_T_1422, 0, 0) @[el2_ifu_mem_ctl.scala 415:122]
|
|
node _T_1424 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:87]
|
|
node _T_1425 = eq(_T_1424, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 415:114]
|
|
node _T_1426 = bits(_T_1425, 0, 0) @[el2_ifu_mem_ctl.scala 415:122]
|
|
node _T_1427 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:87]
|
|
node _T_1428 = eq(_T_1427, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 415:114]
|
|
node _T_1429 = bits(_T_1428, 0, 0) @[el2_ifu_mem_ctl.scala 415:122]
|
|
node _T_1430 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:87]
|
|
node _T_1431 = eq(_T_1430, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 415:114]
|
|
node _T_1432 = bits(_T_1431, 0, 0) @[el2_ifu_mem_ctl.scala 415:122]
|
|
node _T_1433 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 415:87]
|
|
node _T_1434 = eq(_T_1433, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 415:114]
|
|
node _T_1435 = bits(_T_1434, 0, 0) @[el2_ifu_mem_ctl.scala 415:122]
|
|
node _T_1436 = mux(_T_1414, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1437 = mux(_T_1417, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1438 = mux(_T_1420, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1439 = mux(_T_1423, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1440 = mux(_T_1426, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1441 = mux(_T_1429, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1442 = mux(_T_1432, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1443 = mux(_T_1435, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1444 = or(_T_1436, _T_1437) @[Mux.scala 27:72]
|
|
node _T_1445 = or(_T_1444, _T_1438) @[Mux.scala 27:72]
|
|
node _T_1446 = or(_T_1445, _T_1439) @[Mux.scala 27:72]
|
|
node _T_1447 = or(_T_1446, _T_1440) @[Mux.scala 27:72]
|
|
node _T_1448 = or(_T_1447, _T_1441) @[Mux.scala 27:72]
|
|
node _T_1449 = or(_T_1448, _T_1442) @[Mux.scala 27:72]
|
|
node _T_1450 = or(_T_1449, _T_1443) @[Mux.scala 27:72]
|
|
wire bypass_valid_value_check : UInt<1> @[Mux.scala 27:72]
|
|
bypass_valid_value_check <= _T_1450 @[Mux.scala 27:72]
|
|
node _T_1451 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 416:71]
|
|
node _T_1452 = eq(_T_1451, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 416:58]
|
|
node _T_1453 = and(bypass_valid_value_check, _T_1452) @[el2_ifu_mem_ctl.scala 416:56]
|
|
node _T_1454 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 416:90]
|
|
node _T_1455 = eq(_T_1454, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 416:77]
|
|
node _T_1456 = and(_T_1453, _T_1455) @[el2_ifu_mem_ctl.scala 416:75]
|
|
node _T_1457 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 417:71]
|
|
node _T_1458 = eq(_T_1457, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 417:58]
|
|
node _T_1459 = and(bypass_valid_value_check, _T_1458) @[el2_ifu_mem_ctl.scala 417:56]
|
|
node _T_1460 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 417:89]
|
|
node _T_1461 = and(_T_1459, _T_1460) @[el2_ifu_mem_ctl.scala 417:75]
|
|
node _T_1462 = or(_T_1456, _T_1461) @[el2_ifu_mem_ctl.scala 416:95]
|
|
node _T_1463 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 418:70]
|
|
node _T_1464 = and(bypass_valid_value_check, _T_1463) @[el2_ifu_mem_ctl.scala 418:56]
|
|
node _T_1465 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 418:89]
|
|
node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 418:76]
|
|
node _T_1467 = and(_T_1464, _T_1466) @[el2_ifu_mem_ctl.scala 418:74]
|
|
node _T_1468 = or(_T_1462, _T_1467) @[el2_ifu_mem_ctl.scala 417:94]
|
|
node _T_1469 = bits(bypass_index, 1, 1) @[el2_ifu_mem_ctl.scala 419:47]
|
|
node _T_1470 = and(bypass_valid_value_check, _T_1469) @[el2_ifu_mem_ctl.scala 419:33]
|
|
node _T_1471 = bits(bypass_index, 0, 0) @[el2_ifu_mem_ctl.scala 419:65]
|
|
node _T_1472 = and(_T_1470, _T_1471) @[el2_ifu_mem_ctl.scala 419:51]
|
|
node _T_1473 = eq(bypass_index_5_3_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 419:132]
|
|
node _T_1474 = bits(_T_1473, 0, 0) @[el2_ifu_mem_ctl.scala 419:140]
|
|
node _T_1475 = eq(bypass_index_5_3_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 419:132]
|
|
node _T_1476 = bits(_T_1475, 0, 0) @[el2_ifu_mem_ctl.scala 419:140]
|
|
node _T_1477 = eq(bypass_index_5_3_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 419:132]
|
|
node _T_1478 = bits(_T_1477, 0, 0) @[el2_ifu_mem_ctl.scala 419:140]
|
|
node _T_1479 = eq(bypass_index_5_3_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 419:132]
|
|
node _T_1480 = bits(_T_1479, 0, 0) @[el2_ifu_mem_ctl.scala 419:140]
|
|
node _T_1481 = eq(bypass_index_5_3_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 419:132]
|
|
node _T_1482 = bits(_T_1481, 0, 0) @[el2_ifu_mem_ctl.scala 419:140]
|
|
node _T_1483 = eq(bypass_index_5_3_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 419:132]
|
|
node _T_1484 = bits(_T_1483, 0, 0) @[el2_ifu_mem_ctl.scala 419:140]
|
|
node _T_1485 = eq(bypass_index_5_3_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 419:132]
|
|
node _T_1486 = bits(_T_1485, 0, 0) @[el2_ifu_mem_ctl.scala 419:140]
|
|
node _T_1487 = eq(bypass_index_5_3_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 419:132]
|
|
node _T_1488 = bits(_T_1487, 0, 0) @[el2_ifu_mem_ctl.scala 419:140]
|
|
node _T_1489 = mux(_T_1474, ic_miss_buff_data_valid_in_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1490 = mux(_T_1476, ic_miss_buff_data_valid_in_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1491 = mux(_T_1478, ic_miss_buff_data_valid_in_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1492 = mux(_T_1480, ic_miss_buff_data_valid_in_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1493 = mux(_T_1482, ic_miss_buff_data_valid_in_4, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1494 = mux(_T_1484, ic_miss_buff_data_valid_in_5, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1495 = mux(_T_1486, ic_miss_buff_data_valid_in_6, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1496 = mux(_T_1488, ic_miss_buff_data_valid_in_7, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1497 = or(_T_1489, _T_1490) @[Mux.scala 27:72]
|
|
node _T_1498 = or(_T_1497, _T_1491) @[Mux.scala 27:72]
|
|
node _T_1499 = or(_T_1498, _T_1492) @[Mux.scala 27:72]
|
|
node _T_1500 = or(_T_1499, _T_1493) @[Mux.scala 27:72]
|
|
node _T_1501 = or(_T_1500, _T_1494) @[Mux.scala 27:72]
|
|
node _T_1502 = or(_T_1501, _T_1495) @[Mux.scala 27:72]
|
|
node _T_1503 = or(_T_1502, _T_1496) @[Mux.scala 27:72]
|
|
wire _T_1504 : UInt<1> @[Mux.scala 27:72]
|
|
_T_1504 <= _T_1503 @[Mux.scala 27:72]
|
|
node _T_1505 = and(_T_1472, _T_1504) @[el2_ifu_mem_ctl.scala 419:69]
|
|
node _T_1506 = or(_T_1468, _T_1505) @[el2_ifu_mem_ctl.scala 418:94]
|
|
node _T_1507 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 420:70]
|
|
node _T_1508 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_1509 = eq(_T_1507, _T_1508) @[el2_ifu_mem_ctl.scala 420:95]
|
|
node _T_1510 = and(bypass_valid_value_check, _T_1509) @[el2_ifu_mem_ctl.scala 420:56]
|
|
node bypass_data_ready_in = or(_T_1506, _T_1510) @[el2_ifu_mem_ctl.scala 419:181]
|
|
wire ic_crit_wd_rdy_new_ff : UInt<1>
|
|
ic_crit_wd_rdy_new_ff <= UInt<1>("h00")
|
|
node _T_1511 = and(bypass_data_ready_in, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 424:53]
|
|
node _T_1512 = and(_T_1511, uncacheable_miss_ff) @[el2_ifu_mem_ctl.scala 424:73]
|
|
node _T_1513 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 424:98]
|
|
node _T_1514 = and(_T_1512, _T_1513) @[el2_ifu_mem_ctl.scala 424:96]
|
|
node _T_1515 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 424:120]
|
|
node _T_1516 = and(_T_1514, _T_1515) @[el2_ifu_mem_ctl.scala 424:118]
|
|
node _T_1517 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 425:75]
|
|
node _T_1518 = and(crit_wd_byp_ok_ff, _T_1517) @[el2_ifu_mem_ctl.scala 425:73]
|
|
node _T_1519 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 425:98]
|
|
node _T_1520 = and(_T_1518, _T_1519) @[el2_ifu_mem_ctl.scala 425:96]
|
|
node _T_1521 = eq(ifu_bp_hit_taken_q_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 425:120]
|
|
node _T_1522 = and(_T_1520, _T_1521) @[el2_ifu_mem_ctl.scala 425:118]
|
|
node _T_1523 = or(_T_1516, _T_1522) @[el2_ifu_mem_ctl.scala 424:143]
|
|
node _T_1524 = and(ic_crit_wd_rdy_new_ff, crit_wd_byp_ok_ff) @[el2_ifu_mem_ctl.scala 426:54]
|
|
node _T_1525 = eq(fetch_req_icache_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 426:76]
|
|
node _T_1526 = and(_T_1524, _T_1525) @[el2_ifu_mem_ctl.scala 426:74]
|
|
node _T_1527 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 426:98]
|
|
node _T_1528 = and(_T_1526, _T_1527) @[el2_ifu_mem_ctl.scala 426:96]
|
|
node ic_crit_wd_rdy_new_in = or(_T_1523, _T_1528) @[el2_ifu_mem_ctl.scala 425:143]
|
|
reg _T_1529 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 427:58]
|
|
_T_1529 <= ic_crit_wd_rdy_new_in @[el2_ifu_mem_ctl.scala 427:58]
|
|
ic_crit_wd_rdy_new_ff <= _T_1529 @[el2_ifu_mem_ctl.scala 427:25]
|
|
node byp_fetch_index = bits(ifu_fetch_addr_int_f, 4, 0) @[el2_ifu_mem_ctl.scala 428:45]
|
|
node _T_1530 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 429:51]
|
|
node byp_fetch_index_0 = cat(_T_1530, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_1531 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 430:51]
|
|
node byp_fetch_index_1 = cat(_T_1531, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1532 = bits(ifu_fetch_addr_int_f, 4, 2) @[el2_ifu_mem_ctl.scala 431:49]
|
|
node _T_1533 = add(_T_1532, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 431:75]
|
|
node byp_fetch_index_inc = tail(_T_1533, 1) @[el2_ifu_mem_ctl.scala 431:75]
|
|
node byp_fetch_index_inc_0 = cat(byp_fetch_index_inc, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node byp_fetch_index_inc_1 = cat(byp_fetch_index_inc, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_1534 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 434:93]
|
|
node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 434:118]
|
|
node _T_1536 = bits(_T_1535, 0, 0) @[el2_ifu_mem_ctl.scala 434:126]
|
|
node _T_1537 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 434:157]
|
|
node _T_1538 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 434:93]
|
|
node _T_1539 = eq(_T_1538, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 434:118]
|
|
node _T_1540 = bits(_T_1539, 0, 0) @[el2_ifu_mem_ctl.scala 434:126]
|
|
node _T_1541 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 434:157]
|
|
node _T_1542 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 434:93]
|
|
node _T_1543 = eq(_T_1542, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 434:118]
|
|
node _T_1544 = bits(_T_1543, 0, 0) @[el2_ifu_mem_ctl.scala 434:126]
|
|
node _T_1545 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 434:157]
|
|
node _T_1546 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 434:93]
|
|
node _T_1547 = eq(_T_1546, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 434:118]
|
|
node _T_1548 = bits(_T_1547, 0, 0) @[el2_ifu_mem_ctl.scala 434:126]
|
|
node _T_1549 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 434:157]
|
|
node _T_1550 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 434:93]
|
|
node _T_1551 = eq(_T_1550, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 434:118]
|
|
node _T_1552 = bits(_T_1551, 0, 0) @[el2_ifu_mem_ctl.scala 434:126]
|
|
node _T_1553 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 434:157]
|
|
node _T_1554 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 434:93]
|
|
node _T_1555 = eq(_T_1554, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 434:118]
|
|
node _T_1556 = bits(_T_1555, 0, 0) @[el2_ifu_mem_ctl.scala 434:126]
|
|
node _T_1557 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 434:157]
|
|
node _T_1558 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 434:93]
|
|
node _T_1559 = eq(_T_1558, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 434:118]
|
|
node _T_1560 = bits(_T_1559, 0, 0) @[el2_ifu_mem_ctl.scala 434:126]
|
|
node _T_1561 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 434:157]
|
|
node _T_1562 = bits(bypass_index, 4, 2) @[el2_ifu_mem_ctl.scala 434:93]
|
|
node _T_1563 = eq(_T_1562, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 434:118]
|
|
node _T_1564 = bits(_T_1563, 0, 0) @[el2_ifu_mem_ctl.scala 434:126]
|
|
node _T_1565 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 434:157]
|
|
node _T_1566 = mux(_T_1536, _T_1537, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1567 = mux(_T_1540, _T_1541, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1568 = mux(_T_1544, _T_1545, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1569 = mux(_T_1548, _T_1549, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1570 = mux(_T_1552, _T_1553, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1571 = mux(_T_1556, _T_1557, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1572 = mux(_T_1560, _T_1561, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1573 = mux(_T_1564, _T_1565, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1574 = or(_T_1566, _T_1567) @[Mux.scala 27:72]
|
|
node _T_1575 = or(_T_1574, _T_1568) @[Mux.scala 27:72]
|
|
node _T_1576 = or(_T_1575, _T_1569) @[Mux.scala 27:72]
|
|
node _T_1577 = or(_T_1576, _T_1570) @[Mux.scala 27:72]
|
|
node _T_1578 = or(_T_1577, _T_1571) @[Mux.scala 27:72]
|
|
node _T_1579 = or(_T_1578, _T_1572) @[Mux.scala 27:72]
|
|
node _T_1580 = or(_T_1579, _T_1573) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_error_bypass <= _T_1580 @[Mux.scala 27:72]
|
|
node _T_1581 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 435:104]
|
|
node _T_1582 = bits(_T_1581, 0, 0) @[el2_ifu_mem_ctl.scala 435:112]
|
|
node _T_1583 = bits(ic_miss_buff_data_error, 0, 0) @[el2_ifu_mem_ctl.scala 435:143]
|
|
node _T_1584 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 435:104]
|
|
node _T_1585 = bits(_T_1584, 0, 0) @[el2_ifu_mem_ctl.scala 435:112]
|
|
node _T_1586 = bits(ic_miss_buff_data_error, 1, 1) @[el2_ifu_mem_ctl.scala 435:143]
|
|
node _T_1587 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 435:104]
|
|
node _T_1588 = bits(_T_1587, 0, 0) @[el2_ifu_mem_ctl.scala 435:112]
|
|
node _T_1589 = bits(ic_miss_buff_data_error, 2, 2) @[el2_ifu_mem_ctl.scala 435:143]
|
|
node _T_1590 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 435:104]
|
|
node _T_1591 = bits(_T_1590, 0, 0) @[el2_ifu_mem_ctl.scala 435:112]
|
|
node _T_1592 = bits(ic_miss_buff_data_error, 3, 3) @[el2_ifu_mem_ctl.scala 435:143]
|
|
node _T_1593 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 435:104]
|
|
node _T_1594 = bits(_T_1593, 0, 0) @[el2_ifu_mem_ctl.scala 435:112]
|
|
node _T_1595 = bits(ic_miss_buff_data_error, 4, 4) @[el2_ifu_mem_ctl.scala 435:143]
|
|
node _T_1596 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 435:104]
|
|
node _T_1597 = bits(_T_1596, 0, 0) @[el2_ifu_mem_ctl.scala 435:112]
|
|
node _T_1598 = bits(ic_miss_buff_data_error, 5, 5) @[el2_ifu_mem_ctl.scala 435:143]
|
|
node _T_1599 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 435:104]
|
|
node _T_1600 = bits(_T_1599, 0, 0) @[el2_ifu_mem_ctl.scala 435:112]
|
|
node _T_1601 = bits(ic_miss_buff_data_error, 6, 6) @[el2_ifu_mem_ctl.scala 435:143]
|
|
node _T_1602 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 435:104]
|
|
node _T_1603 = bits(_T_1602, 0, 0) @[el2_ifu_mem_ctl.scala 435:112]
|
|
node _T_1604 = bits(ic_miss_buff_data_error, 7, 7) @[el2_ifu_mem_ctl.scala 435:143]
|
|
node _T_1605 = mux(_T_1582, _T_1583, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1606 = mux(_T_1585, _T_1586, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1607 = mux(_T_1588, _T_1589, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1608 = mux(_T_1591, _T_1592, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1609 = mux(_T_1594, _T_1595, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1610 = mux(_T_1597, _T_1598, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1611 = mux(_T_1600, _T_1601, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1612 = mux(_T_1603, _T_1604, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1613 = or(_T_1605, _T_1606) @[Mux.scala 27:72]
|
|
node _T_1614 = or(_T_1613, _T_1607) @[Mux.scala 27:72]
|
|
node _T_1615 = or(_T_1614, _T_1608) @[Mux.scala 27:72]
|
|
node _T_1616 = or(_T_1615, _T_1609) @[Mux.scala 27:72]
|
|
node _T_1617 = or(_T_1616, _T_1610) @[Mux.scala 27:72]
|
|
node _T_1618 = or(_T_1617, _T_1611) @[Mux.scala 27:72]
|
|
node _T_1619 = or(_T_1618, _T_1612) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_error_bypass_inc : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_error_bypass_inc <= _T_1619 @[Mux.scala 27:72]
|
|
node _T_1620 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 438:28]
|
|
node _T_1621 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 438:52]
|
|
node _T_1622 = and(_T_1620, _T_1621) @[el2_ifu_mem_ctl.scala 438:31]
|
|
when _T_1622 : @[el2_ifu_mem_ctl.scala 438:56]
|
|
ifu_byp_data_err_new <= ic_miss_buff_data_error_bypass @[el2_ifu_mem_ctl.scala 439:26]
|
|
skip @[el2_ifu_mem_ctl.scala 438:56]
|
|
else : @[el2_ifu_mem_ctl.scala 440:5]
|
|
node _T_1623 = or(ic_miss_buff_data_error_bypass, ic_miss_buff_data_error_bypass_inc) @[el2_ifu_mem_ctl.scala 440:70]
|
|
ifu_byp_data_err_new <= _T_1623 @[el2_ifu_mem_ctl.scala 440:36]
|
|
skip @[el2_ifu_mem_ctl.scala 440:5]
|
|
node _T_1624 = bits(ifu_fetch_addr_int_f, 1, 1) @[el2_ifu_mem_ctl.scala 442:59]
|
|
node _T_1625 = bits(_T_1624, 0, 0) @[el2_ifu_mem_ctl.scala 442:63]
|
|
node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 442:38]
|
|
node _T_1627 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1628 = bits(_T_1627, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1629 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1630 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1631 = bits(_T_1630, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1632 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1633 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1634 = bits(_T_1633, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1635 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1636 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1637 = bits(_T_1636, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1638 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1639 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1640 = bits(_T_1639, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1641 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1642 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1643 = bits(_T_1642, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1644 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1645 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1646 = bits(_T_1645, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1647 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1648 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1649 = bits(_T_1648, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1650 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1651 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1652 = bits(_T_1651, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1653 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1654 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1655 = bits(_T_1654, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1656 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1657 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1658 = bits(_T_1657, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1659 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1660 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1661 = bits(_T_1660, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1662 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1663 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1664 = bits(_T_1663, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1665 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1666 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1667 = bits(_T_1666, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1668 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1669 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1670 = bits(_T_1669, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1671 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1672 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 443:73]
|
|
node _T_1673 = bits(_T_1672, 0, 0) @[el2_ifu_mem_ctl.scala 443:81]
|
|
node _T_1674 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 443:109]
|
|
node _T_1675 = mux(_T_1628, _T_1629, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1676 = mux(_T_1631, _T_1632, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1677 = mux(_T_1634, _T_1635, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1678 = mux(_T_1637, _T_1638, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1679 = mux(_T_1640, _T_1641, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1680 = mux(_T_1643, _T_1644, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1681 = mux(_T_1646, _T_1647, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1682 = mux(_T_1649, _T_1650, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1683 = mux(_T_1652, _T_1653, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1684 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1685 = mux(_T_1658, _T_1659, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1686 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1687 = mux(_T_1664, _T_1665, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1688 = mux(_T_1667, _T_1668, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1689 = mux(_T_1670, _T_1671, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1690 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1691 = or(_T_1675, _T_1676) @[Mux.scala 27:72]
|
|
node _T_1692 = or(_T_1691, _T_1677) @[Mux.scala 27:72]
|
|
node _T_1693 = or(_T_1692, _T_1678) @[Mux.scala 27:72]
|
|
node _T_1694 = or(_T_1693, _T_1679) @[Mux.scala 27:72]
|
|
node _T_1695 = or(_T_1694, _T_1680) @[Mux.scala 27:72]
|
|
node _T_1696 = or(_T_1695, _T_1681) @[Mux.scala 27:72]
|
|
node _T_1697 = or(_T_1696, _T_1682) @[Mux.scala 27:72]
|
|
node _T_1698 = or(_T_1697, _T_1683) @[Mux.scala 27:72]
|
|
node _T_1699 = or(_T_1698, _T_1684) @[Mux.scala 27:72]
|
|
node _T_1700 = or(_T_1699, _T_1685) @[Mux.scala 27:72]
|
|
node _T_1701 = or(_T_1700, _T_1686) @[Mux.scala 27:72]
|
|
node _T_1702 = or(_T_1701, _T_1687) @[Mux.scala 27:72]
|
|
node _T_1703 = or(_T_1702, _T_1688) @[Mux.scala 27:72]
|
|
node _T_1704 = or(_T_1703, _T_1689) @[Mux.scala 27:72]
|
|
node _T_1705 = or(_T_1704, _T_1690) @[Mux.scala 27:72]
|
|
wire _T_1706 : UInt<16> @[Mux.scala 27:72]
|
|
_T_1706 <= _T_1705 @[Mux.scala 27:72]
|
|
node _T_1707 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1708 = bits(_T_1707, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1709 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1710 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1711 = bits(_T_1710, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1712 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1713 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1714 = bits(_T_1713, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1715 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1716 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1717 = bits(_T_1716, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1718 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1719 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1720 = bits(_T_1719, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1721 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1722 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1723 = bits(_T_1722, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1724 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1725 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1726 = bits(_T_1725, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1727 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1728 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1729 = bits(_T_1728, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1730 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1731 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1732 = bits(_T_1731, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1733 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1734 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1735 = bits(_T_1734, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1736 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1737 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1738 = bits(_T_1737, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1739 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1740 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1741 = bits(_T_1740, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1742 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1743 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1744 = bits(_T_1743, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1745 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1746 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1747 = bits(_T_1746, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1748 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1749 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1750 = bits(_T_1749, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1751 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1752 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 443:179]
|
|
node _T_1753 = bits(_T_1752, 0, 0) @[el2_ifu_mem_ctl.scala 443:187]
|
|
node _T_1754 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 443:215]
|
|
node _T_1755 = mux(_T_1708, _T_1709, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1756 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1757 = mux(_T_1714, _T_1715, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1758 = mux(_T_1717, _T_1718, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1759 = mux(_T_1720, _T_1721, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1760 = mux(_T_1723, _T_1724, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1761 = mux(_T_1726, _T_1727, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1762 = mux(_T_1729, _T_1730, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1763 = mux(_T_1732, _T_1733, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1764 = mux(_T_1735, _T_1736, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1765 = mux(_T_1738, _T_1739, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1766 = mux(_T_1741, _T_1742, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1767 = mux(_T_1744, _T_1745, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1768 = mux(_T_1747, _T_1748, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1769 = mux(_T_1750, _T_1751, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1770 = mux(_T_1753, _T_1754, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1771 = or(_T_1755, _T_1756) @[Mux.scala 27:72]
|
|
node _T_1772 = or(_T_1771, _T_1757) @[Mux.scala 27:72]
|
|
node _T_1773 = or(_T_1772, _T_1758) @[Mux.scala 27:72]
|
|
node _T_1774 = or(_T_1773, _T_1759) @[Mux.scala 27:72]
|
|
node _T_1775 = or(_T_1774, _T_1760) @[Mux.scala 27:72]
|
|
node _T_1776 = or(_T_1775, _T_1761) @[Mux.scala 27:72]
|
|
node _T_1777 = or(_T_1776, _T_1762) @[Mux.scala 27:72]
|
|
node _T_1778 = or(_T_1777, _T_1763) @[Mux.scala 27:72]
|
|
node _T_1779 = or(_T_1778, _T_1764) @[Mux.scala 27:72]
|
|
node _T_1780 = or(_T_1779, _T_1765) @[Mux.scala 27:72]
|
|
node _T_1781 = or(_T_1780, _T_1766) @[Mux.scala 27:72]
|
|
node _T_1782 = or(_T_1781, _T_1767) @[Mux.scala 27:72]
|
|
node _T_1783 = or(_T_1782, _T_1768) @[Mux.scala 27:72]
|
|
node _T_1784 = or(_T_1783, _T_1769) @[Mux.scala 27:72]
|
|
node _T_1785 = or(_T_1784, _T_1770) @[Mux.scala 27:72]
|
|
wire _T_1786 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1786 <= _T_1785 @[Mux.scala 27:72]
|
|
node _T_1787 = eq(byp_fetch_index_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1788 = bits(_T_1787, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1789 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1790 = eq(byp_fetch_index_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1791 = bits(_T_1790, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1792 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1793 = eq(byp_fetch_index_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1794 = bits(_T_1793, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1795 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1796 = eq(byp_fetch_index_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1797 = bits(_T_1796, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1798 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1799 = eq(byp_fetch_index_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1800 = bits(_T_1799, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1801 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1802 = eq(byp_fetch_index_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1803 = bits(_T_1802, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1804 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1805 = eq(byp_fetch_index_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1806 = bits(_T_1805, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1807 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1808 = eq(byp_fetch_index_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1809 = bits(_T_1808, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1810 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1811 = eq(byp_fetch_index_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1812 = bits(_T_1811, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1813 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1814 = eq(byp_fetch_index_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1815 = bits(_T_1814, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1816 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1817 = eq(byp_fetch_index_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1818 = bits(_T_1817, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1819 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1820 = eq(byp_fetch_index_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1821 = bits(_T_1820, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1822 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1823 = eq(byp_fetch_index_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1824 = bits(_T_1823, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1825 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1826 = eq(byp_fetch_index_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1827 = bits(_T_1826, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1828 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1829 = eq(byp_fetch_index_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1830 = bits(_T_1829, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1831 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1832 = eq(byp_fetch_index_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 443:285]
|
|
node _T_1833 = bits(_T_1832, 0, 0) @[el2_ifu_mem_ctl.scala 443:293]
|
|
node _T_1834 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 443:321]
|
|
node _T_1835 = mux(_T_1788, _T_1789, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1836 = mux(_T_1791, _T_1792, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1837 = mux(_T_1794, _T_1795, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1838 = mux(_T_1797, _T_1798, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1839 = mux(_T_1800, _T_1801, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1840 = mux(_T_1803, _T_1804, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1841 = mux(_T_1806, _T_1807, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1842 = mux(_T_1809, _T_1810, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1843 = mux(_T_1812, _T_1813, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1844 = mux(_T_1815, _T_1816, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1845 = mux(_T_1818, _T_1819, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1846 = mux(_T_1821, _T_1822, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1847 = mux(_T_1824, _T_1825, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1848 = mux(_T_1827, _T_1828, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1849 = mux(_T_1830, _T_1831, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1850 = mux(_T_1833, _T_1834, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1851 = or(_T_1835, _T_1836) @[Mux.scala 27:72]
|
|
node _T_1852 = or(_T_1851, _T_1837) @[Mux.scala 27:72]
|
|
node _T_1853 = or(_T_1852, _T_1838) @[Mux.scala 27:72]
|
|
node _T_1854 = or(_T_1853, _T_1839) @[Mux.scala 27:72]
|
|
node _T_1855 = or(_T_1854, _T_1840) @[Mux.scala 27:72]
|
|
node _T_1856 = or(_T_1855, _T_1841) @[Mux.scala 27:72]
|
|
node _T_1857 = or(_T_1856, _T_1842) @[Mux.scala 27:72]
|
|
node _T_1858 = or(_T_1857, _T_1843) @[Mux.scala 27:72]
|
|
node _T_1859 = or(_T_1858, _T_1844) @[Mux.scala 27:72]
|
|
node _T_1860 = or(_T_1859, _T_1845) @[Mux.scala 27:72]
|
|
node _T_1861 = or(_T_1860, _T_1846) @[Mux.scala 27:72]
|
|
node _T_1862 = or(_T_1861, _T_1847) @[Mux.scala 27:72]
|
|
node _T_1863 = or(_T_1862, _T_1848) @[Mux.scala 27:72]
|
|
node _T_1864 = or(_T_1863, _T_1849) @[Mux.scala 27:72]
|
|
node _T_1865 = or(_T_1864, _T_1850) @[Mux.scala 27:72]
|
|
wire _T_1866 : UInt<32> @[Mux.scala 27:72]
|
|
_T_1866 <= _T_1865 @[Mux.scala 27:72]
|
|
node _T_1867 = cat(_T_1706, _T_1786) @[Cat.scala 29:58]
|
|
node _T_1868 = cat(_T_1867, _T_1866) @[Cat.scala 29:58]
|
|
node _T_1869 = eq(byp_fetch_index_inc_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1870 = bits(_T_1869, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1871 = bits(ic_miss_buff_data[0], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1872 = eq(byp_fetch_index_inc_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1873 = bits(_T_1872, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1874 = bits(ic_miss_buff_data[1], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1875 = eq(byp_fetch_index_inc_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1876 = bits(_T_1875, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1877 = bits(ic_miss_buff_data[2], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1878 = eq(byp_fetch_index_inc_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1879 = bits(_T_1878, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1880 = bits(ic_miss_buff_data[3], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1881 = eq(byp_fetch_index_inc_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1882 = bits(_T_1881, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1883 = bits(ic_miss_buff_data[4], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1884 = eq(byp_fetch_index_inc_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1885 = bits(_T_1884, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1886 = bits(ic_miss_buff_data[5], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1887 = eq(byp_fetch_index_inc_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1888 = bits(_T_1887, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1889 = bits(ic_miss_buff_data[6], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1890 = eq(byp_fetch_index_inc_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1891 = bits(_T_1890, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1892 = bits(ic_miss_buff_data[7], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1893 = eq(byp_fetch_index_inc_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1894 = bits(_T_1893, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1895 = bits(ic_miss_buff_data[8], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1896 = eq(byp_fetch_index_inc_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1897 = bits(_T_1896, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1898 = bits(ic_miss_buff_data[9], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1899 = eq(byp_fetch_index_inc_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1900 = bits(_T_1899, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1901 = bits(ic_miss_buff_data[10], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1902 = eq(byp_fetch_index_inc_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1903 = bits(_T_1902, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1904 = bits(ic_miss_buff_data[11], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1905 = eq(byp_fetch_index_inc_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1906 = bits(_T_1905, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1907 = bits(ic_miss_buff_data[12], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1908 = eq(byp_fetch_index_inc_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1909 = bits(_T_1908, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1910 = bits(ic_miss_buff_data[13], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1911 = eq(byp_fetch_index_inc_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1912 = bits(_T_1911, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1913 = bits(ic_miss_buff_data[14], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1914 = eq(byp_fetch_index_inc_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 444:73]
|
|
node _T_1915 = bits(_T_1914, 0, 0) @[el2_ifu_mem_ctl.scala 444:81]
|
|
node _T_1916 = bits(ic_miss_buff_data[15], 15, 0) @[el2_ifu_mem_ctl.scala 444:109]
|
|
node _T_1917 = mux(_T_1870, _T_1871, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1918 = mux(_T_1873, _T_1874, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1919 = mux(_T_1876, _T_1877, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1920 = mux(_T_1879, _T_1880, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1921 = mux(_T_1882, _T_1883, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1922 = mux(_T_1885, _T_1886, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1923 = mux(_T_1888, _T_1889, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1924 = mux(_T_1891, _T_1892, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1925 = mux(_T_1894, _T_1895, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1926 = mux(_T_1897, _T_1898, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1927 = mux(_T_1900, _T_1901, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1928 = mux(_T_1903, _T_1904, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1929 = mux(_T_1906, _T_1907, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1930 = mux(_T_1909, _T_1910, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1931 = mux(_T_1912, _T_1913, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1932 = mux(_T_1915, _T_1916, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1933 = or(_T_1917, _T_1918) @[Mux.scala 27:72]
|
|
node _T_1934 = or(_T_1933, _T_1919) @[Mux.scala 27:72]
|
|
node _T_1935 = or(_T_1934, _T_1920) @[Mux.scala 27:72]
|
|
node _T_1936 = or(_T_1935, _T_1921) @[Mux.scala 27:72]
|
|
node _T_1937 = or(_T_1936, _T_1922) @[Mux.scala 27:72]
|
|
node _T_1938 = or(_T_1937, _T_1923) @[Mux.scala 27:72]
|
|
node _T_1939 = or(_T_1938, _T_1924) @[Mux.scala 27:72]
|
|
node _T_1940 = or(_T_1939, _T_1925) @[Mux.scala 27:72]
|
|
node _T_1941 = or(_T_1940, _T_1926) @[Mux.scala 27:72]
|
|
node _T_1942 = or(_T_1941, _T_1927) @[Mux.scala 27:72]
|
|
node _T_1943 = or(_T_1942, _T_1928) @[Mux.scala 27:72]
|
|
node _T_1944 = or(_T_1943, _T_1929) @[Mux.scala 27:72]
|
|
node _T_1945 = or(_T_1944, _T_1930) @[Mux.scala 27:72]
|
|
node _T_1946 = or(_T_1945, _T_1931) @[Mux.scala 27:72]
|
|
node _T_1947 = or(_T_1946, _T_1932) @[Mux.scala 27:72]
|
|
wire _T_1948 : UInt<16> @[Mux.scala 27:72]
|
|
_T_1948 <= _T_1947 @[Mux.scala 27:72]
|
|
node _T_1949 = eq(byp_fetch_index_inc_0, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1950 = bits(_T_1949, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1951 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1952 = eq(byp_fetch_index_inc_0, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1953 = bits(_T_1952, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1954 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1955 = eq(byp_fetch_index_inc_0, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1956 = bits(_T_1955, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1957 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1958 = eq(byp_fetch_index_inc_0, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1959 = bits(_T_1958, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1960 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1961 = eq(byp_fetch_index_inc_0, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1962 = bits(_T_1961, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1963 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1964 = eq(byp_fetch_index_inc_0, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1965 = bits(_T_1964, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1966 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1967 = eq(byp_fetch_index_inc_0, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1968 = bits(_T_1967, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1969 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1970 = eq(byp_fetch_index_inc_0, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1971 = bits(_T_1970, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1972 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1973 = eq(byp_fetch_index_inc_0, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1974 = bits(_T_1973, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1975 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1976 = eq(byp_fetch_index_inc_0, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1977 = bits(_T_1976, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1978 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1979 = eq(byp_fetch_index_inc_0, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1980 = bits(_T_1979, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1981 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1982 = eq(byp_fetch_index_inc_0, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1983 = bits(_T_1982, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1984 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1985 = eq(byp_fetch_index_inc_0, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1986 = bits(_T_1985, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1987 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1988 = eq(byp_fetch_index_inc_0, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1989 = bits(_T_1988, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1990 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1991 = eq(byp_fetch_index_inc_0, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1992 = bits(_T_1991, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1993 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1994 = eq(byp_fetch_index_inc_0, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 444:183]
|
|
node _T_1995 = bits(_T_1994, 0, 0) @[el2_ifu_mem_ctl.scala 444:191]
|
|
node _T_1996 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 444:219]
|
|
node _T_1997 = mux(_T_1950, _T_1951, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1998 = mux(_T_1953, _T_1954, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_1999 = mux(_T_1956, _T_1957, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2000 = mux(_T_1959, _T_1960, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2001 = mux(_T_1962, _T_1963, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2002 = mux(_T_1965, _T_1966, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2003 = mux(_T_1968, _T_1969, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2004 = mux(_T_1971, _T_1972, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2005 = mux(_T_1974, _T_1975, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2006 = mux(_T_1977, _T_1978, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2007 = mux(_T_1980, _T_1981, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2008 = mux(_T_1983, _T_1984, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2009 = mux(_T_1986, _T_1987, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2010 = mux(_T_1989, _T_1990, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2011 = mux(_T_1992, _T_1993, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2012 = mux(_T_1995, _T_1996, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2013 = or(_T_1997, _T_1998) @[Mux.scala 27:72]
|
|
node _T_2014 = or(_T_2013, _T_1999) @[Mux.scala 27:72]
|
|
node _T_2015 = or(_T_2014, _T_2000) @[Mux.scala 27:72]
|
|
node _T_2016 = or(_T_2015, _T_2001) @[Mux.scala 27:72]
|
|
node _T_2017 = or(_T_2016, _T_2002) @[Mux.scala 27:72]
|
|
node _T_2018 = or(_T_2017, _T_2003) @[Mux.scala 27:72]
|
|
node _T_2019 = or(_T_2018, _T_2004) @[Mux.scala 27:72]
|
|
node _T_2020 = or(_T_2019, _T_2005) @[Mux.scala 27:72]
|
|
node _T_2021 = or(_T_2020, _T_2006) @[Mux.scala 27:72]
|
|
node _T_2022 = or(_T_2021, _T_2007) @[Mux.scala 27:72]
|
|
node _T_2023 = or(_T_2022, _T_2008) @[Mux.scala 27:72]
|
|
node _T_2024 = or(_T_2023, _T_2009) @[Mux.scala 27:72]
|
|
node _T_2025 = or(_T_2024, _T_2010) @[Mux.scala 27:72]
|
|
node _T_2026 = or(_T_2025, _T_2011) @[Mux.scala 27:72]
|
|
node _T_2027 = or(_T_2026, _T_2012) @[Mux.scala 27:72]
|
|
wire _T_2028 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2028 <= _T_2027 @[Mux.scala 27:72]
|
|
node _T_2029 = eq(byp_fetch_index_1, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2030 = bits(_T_2029, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2031 = bits(ic_miss_buff_data[0], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2032 = eq(byp_fetch_index_1, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2033 = bits(_T_2032, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2034 = bits(ic_miss_buff_data[1], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2035 = eq(byp_fetch_index_1, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2036 = bits(_T_2035, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2037 = bits(ic_miss_buff_data[2], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2038 = eq(byp_fetch_index_1, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2039 = bits(_T_2038, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2040 = bits(ic_miss_buff_data[3], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2041 = eq(byp_fetch_index_1, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2042 = bits(_T_2041, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2043 = bits(ic_miss_buff_data[4], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2044 = eq(byp_fetch_index_1, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2045 = bits(_T_2044, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2046 = bits(ic_miss_buff_data[5], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2047 = eq(byp_fetch_index_1, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2048 = bits(_T_2047, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2049 = bits(ic_miss_buff_data[6], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2050 = eq(byp_fetch_index_1, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2051 = bits(_T_2050, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2052 = bits(ic_miss_buff_data[7], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2053 = eq(byp_fetch_index_1, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2054 = bits(_T_2053, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2055 = bits(ic_miss_buff_data[8], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2056 = eq(byp_fetch_index_1, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2057 = bits(_T_2056, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2058 = bits(ic_miss_buff_data[9], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2059 = eq(byp_fetch_index_1, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2060 = bits(_T_2059, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2061 = bits(ic_miss_buff_data[10], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2062 = eq(byp_fetch_index_1, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2063 = bits(_T_2062, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2064 = bits(ic_miss_buff_data[11], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2065 = eq(byp_fetch_index_1, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2066 = bits(_T_2065, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2067 = bits(ic_miss_buff_data[12], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2068 = eq(byp_fetch_index_1, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2069 = bits(_T_2068, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2070 = bits(ic_miss_buff_data[13], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2071 = eq(byp_fetch_index_1, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2072 = bits(_T_2071, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2073 = bits(ic_miss_buff_data[14], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2074 = eq(byp_fetch_index_1, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 444:289]
|
|
node _T_2075 = bits(_T_2074, 0, 0) @[el2_ifu_mem_ctl.scala 444:297]
|
|
node _T_2076 = bits(ic_miss_buff_data[15], 31, 0) @[el2_ifu_mem_ctl.scala 444:325]
|
|
node _T_2077 = mux(_T_2030, _T_2031, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2078 = mux(_T_2033, _T_2034, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2079 = mux(_T_2036, _T_2037, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2080 = mux(_T_2039, _T_2040, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2081 = mux(_T_2042, _T_2043, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2082 = mux(_T_2045, _T_2046, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2083 = mux(_T_2048, _T_2049, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2084 = mux(_T_2051, _T_2052, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2085 = mux(_T_2054, _T_2055, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2086 = mux(_T_2057, _T_2058, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2087 = mux(_T_2060, _T_2061, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2088 = mux(_T_2063, _T_2064, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2089 = mux(_T_2066, _T_2067, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2090 = mux(_T_2069, _T_2070, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2091 = mux(_T_2072, _T_2073, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2092 = mux(_T_2075, _T_2076, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2093 = or(_T_2077, _T_2078) @[Mux.scala 27:72]
|
|
node _T_2094 = or(_T_2093, _T_2079) @[Mux.scala 27:72]
|
|
node _T_2095 = or(_T_2094, _T_2080) @[Mux.scala 27:72]
|
|
node _T_2096 = or(_T_2095, _T_2081) @[Mux.scala 27:72]
|
|
node _T_2097 = or(_T_2096, _T_2082) @[Mux.scala 27:72]
|
|
node _T_2098 = or(_T_2097, _T_2083) @[Mux.scala 27:72]
|
|
node _T_2099 = or(_T_2098, _T_2084) @[Mux.scala 27:72]
|
|
node _T_2100 = or(_T_2099, _T_2085) @[Mux.scala 27:72]
|
|
node _T_2101 = or(_T_2100, _T_2086) @[Mux.scala 27:72]
|
|
node _T_2102 = or(_T_2101, _T_2087) @[Mux.scala 27:72]
|
|
node _T_2103 = or(_T_2102, _T_2088) @[Mux.scala 27:72]
|
|
node _T_2104 = or(_T_2103, _T_2089) @[Mux.scala 27:72]
|
|
node _T_2105 = or(_T_2104, _T_2090) @[Mux.scala 27:72]
|
|
node _T_2106 = or(_T_2105, _T_2091) @[Mux.scala 27:72]
|
|
node _T_2107 = or(_T_2106, _T_2092) @[Mux.scala 27:72]
|
|
wire _T_2108 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2108 <= _T_2107 @[Mux.scala 27:72]
|
|
node _T_2109 = cat(_T_1948, _T_2028) @[Cat.scala 29:58]
|
|
node _T_2110 = cat(_T_2109, _T_2108) @[Cat.scala 29:58]
|
|
node ic_byp_data_only_pre_new = mux(_T_1626, _T_1868, _T_2110) @[el2_ifu_mem_ctl.scala 442:37]
|
|
node _T_2111 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 446:52]
|
|
node _T_2112 = bits(_T_2111, 0, 0) @[el2_ifu_mem_ctl.scala 446:62]
|
|
node _T_2113 = eq(_T_2112, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 446:31]
|
|
node _T_2114 = bits(ic_byp_data_only_pre_new, 79, 16) @[el2_ifu_mem_ctl.scala 446:128]
|
|
node _T_2115 = cat(UInt<16>("h00"), _T_2114) @[Cat.scala 29:58]
|
|
node _T_2116 = mux(_T_2113, ic_byp_data_only_pre_new, _T_2115) @[el2_ifu_mem_ctl.scala 446:30]
|
|
ic_byp_data_only_new <= _T_2116 @[el2_ifu_mem_ctl.scala 446:24]
|
|
node _T_2117 = bits(imb_ff, 5, 5) @[el2_ifu_mem_ctl.scala 448:27]
|
|
node _T_2118 = bits(ifu_fetch_addr_int_f, 5, 5) @[el2_ifu_mem_ctl.scala 448:75]
|
|
node miss_wrap_f = neq(_T_2117, _T_2118) @[el2_ifu_mem_ctl.scala 448:51]
|
|
node _T_2119 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:102]
|
|
node _T_2120 = eq(_T_2119, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 449:127]
|
|
node _T_2121 = bits(_T_2120, 0, 0) @[el2_ifu_mem_ctl.scala 449:135]
|
|
node _T_2122 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 449:166]
|
|
node _T_2123 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:102]
|
|
node _T_2124 = eq(_T_2123, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 449:127]
|
|
node _T_2125 = bits(_T_2124, 0, 0) @[el2_ifu_mem_ctl.scala 449:135]
|
|
node _T_2126 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 449:166]
|
|
node _T_2127 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:102]
|
|
node _T_2128 = eq(_T_2127, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 449:127]
|
|
node _T_2129 = bits(_T_2128, 0, 0) @[el2_ifu_mem_ctl.scala 449:135]
|
|
node _T_2130 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 449:166]
|
|
node _T_2131 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:102]
|
|
node _T_2132 = eq(_T_2131, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 449:127]
|
|
node _T_2133 = bits(_T_2132, 0, 0) @[el2_ifu_mem_ctl.scala 449:135]
|
|
node _T_2134 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 449:166]
|
|
node _T_2135 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:102]
|
|
node _T_2136 = eq(_T_2135, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 449:127]
|
|
node _T_2137 = bits(_T_2136, 0, 0) @[el2_ifu_mem_ctl.scala 449:135]
|
|
node _T_2138 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 449:166]
|
|
node _T_2139 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:102]
|
|
node _T_2140 = eq(_T_2139, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 449:127]
|
|
node _T_2141 = bits(_T_2140, 0, 0) @[el2_ifu_mem_ctl.scala 449:135]
|
|
node _T_2142 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 449:166]
|
|
node _T_2143 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:102]
|
|
node _T_2144 = eq(_T_2143, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 449:127]
|
|
node _T_2145 = bits(_T_2144, 0, 0) @[el2_ifu_mem_ctl.scala 449:135]
|
|
node _T_2146 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 449:166]
|
|
node _T_2147 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 449:102]
|
|
node _T_2148 = eq(_T_2147, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 449:127]
|
|
node _T_2149 = bits(_T_2148, 0, 0) @[el2_ifu_mem_ctl.scala 449:135]
|
|
node _T_2150 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 449:166]
|
|
node _T_2151 = mux(_T_2121, _T_2122, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2152 = mux(_T_2125, _T_2126, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2153 = mux(_T_2129, _T_2130, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2154 = mux(_T_2133, _T_2134, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2155 = mux(_T_2137, _T_2138, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2156 = mux(_T_2141, _T_2142, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2157 = mux(_T_2145, _T_2146, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2158 = mux(_T_2149, _T_2150, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2159 = or(_T_2151, _T_2152) @[Mux.scala 27:72]
|
|
node _T_2160 = or(_T_2159, _T_2153) @[Mux.scala 27:72]
|
|
node _T_2161 = or(_T_2160, _T_2154) @[Mux.scala 27:72]
|
|
node _T_2162 = or(_T_2161, _T_2155) @[Mux.scala 27:72]
|
|
node _T_2163 = or(_T_2162, _T_2156) @[Mux.scala 27:72]
|
|
node _T_2164 = or(_T_2163, _T_2157) @[Mux.scala 27:72]
|
|
node _T_2165 = or(_T_2164, _T_2158) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_bypass_index : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_valid_bypass_index <= _T_2165 @[Mux.scala 27:72]
|
|
node _T_2166 = eq(byp_fetch_index_inc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 450:110]
|
|
node _T_2167 = bits(_T_2166, 0, 0) @[el2_ifu_mem_ctl.scala 450:118]
|
|
node _T_2168 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 450:149]
|
|
node _T_2169 = eq(byp_fetch_index_inc, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 450:110]
|
|
node _T_2170 = bits(_T_2169, 0, 0) @[el2_ifu_mem_ctl.scala 450:118]
|
|
node _T_2171 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 450:149]
|
|
node _T_2172 = eq(byp_fetch_index_inc, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 450:110]
|
|
node _T_2173 = bits(_T_2172, 0, 0) @[el2_ifu_mem_ctl.scala 450:118]
|
|
node _T_2174 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 450:149]
|
|
node _T_2175 = eq(byp_fetch_index_inc, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 450:110]
|
|
node _T_2176 = bits(_T_2175, 0, 0) @[el2_ifu_mem_ctl.scala 450:118]
|
|
node _T_2177 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 450:149]
|
|
node _T_2178 = eq(byp_fetch_index_inc, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 450:110]
|
|
node _T_2179 = bits(_T_2178, 0, 0) @[el2_ifu_mem_ctl.scala 450:118]
|
|
node _T_2180 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 450:149]
|
|
node _T_2181 = eq(byp_fetch_index_inc, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 450:110]
|
|
node _T_2182 = bits(_T_2181, 0, 0) @[el2_ifu_mem_ctl.scala 450:118]
|
|
node _T_2183 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 450:149]
|
|
node _T_2184 = eq(byp_fetch_index_inc, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 450:110]
|
|
node _T_2185 = bits(_T_2184, 0, 0) @[el2_ifu_mem_ctl.scala 450:118]
|
|
node _T_2186 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 450:149]
|
|
node _T_2187 = eq(byp_fetch_index_inc, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 450:110]
|
|
node _T_2188 = bits(_T_2187, 0, 0) @[el2_ifu_mem_ctl.scala 450:118]
|
|
node _T_2189 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 450:149]
|
|
node _T_2190 = mux(_T_2167, _T_2168, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2191 = mux(_T_2170, _T_2171, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2192 = mux(_T_2173, _T_2174, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2193 = mux(_T_2176, _T_2177, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2194 = mux(_T_2179, _T_2180, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2195 = mux(_T_2182, _T_2183, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2196 = mux(_T_2185, _T_2186, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2197 = mux(_T_2188, _T_2189, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2198 = or(_T_2190, _T_2191) @[Mux.scala 27:72]
|
|
node _T_2199 = or(_T_2198, _T_2192) @[Mux.scala 27:72]
|
|
node _T_2200 = or(_T_2199, _T_2193) @[Mux.scala 27:72]
|
|
node _T_2201 = or(_T_2200, _T_2194) @[Mux.scala 27:72]
|
|
node _T_2202 = or(_T_2201, _T_2195) @[Mux.scala 27:72]
|
|
node _T_2203 = or(_T_2202, _T_2196) @[Mux.scala 27:72]
|
|
node _T_2204 = or(_T_2203, _T_2197) @[Mux.scala 27:72]
|
|
wire ic_miss_buff_data_valid_inc_bypass_index : UInt<1> @[Mux.scala 27:72]
|
|
ic_miss_buff_data_valid_inc_bypass_index <= _T_2204 @[Mux.scala 27:72]
|
|
node _T_2205 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 451:85]
|
|
node _T_2206 = eq(_T_2205, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 451:69]
|
|
node _T_2207 = and(ic_miss_buff_data_valid_bypass_index, _T_2206) @[el2_ifu_mem_ctl.scala 451:67]
|
|
node _T_2208 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 451:107]
|
|
node _T_2209 = eq(_T_2208, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 451:91]
|
|
node _T_2210 = and(_T_2207, _T_2209) @[el2_ifu_mem_ctl.scala 451:89]
|
|
node _T_2211 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 452:61]
|
|
node _T_2212 = eq(_T_2211, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 452:45]
|
|
node _T_2213 = and(ic_miss_buff_data_valid_bypass_index, _T_2212) @[el2_ifu_mem_ctl.scala 452:43]
|
|
node _T_2214 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 452:83]
|
|
node _T_2215 = and(_T_2213, _T_2214) @[el2_ifu_mem_ctl.scala 452:65]
|
|
node _T_2216 = or(_T_2210, _T_2215) @[el2_ifu_mem_ctl.scala 451:112]
|
|
node _T_2217 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 453:61]
|
|
node _T_2218 = and(ic_miss_buff_data_valid_bypass_index, _T_2217) @[el2_ifu_mem_ctl.scala 453:43]
|
|
node _T_2219 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 453:83]
|
|
node _T_2220 = eq(_T_2219, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 453:67]
|
|
node _T_2221 = and(_T_2218, _T_2220) @[el2_ifu_mem_ctl.scala 453:65]
|
|
node _T_2222 = or(_T_2216, _T_2221) @[el2_ifu_mem_ctl.scala 452:88]
|
|
node _T_2223 = bits(byp_fetch_index, 1, 1) @[el2_ifu_mem_ctl.scala 454:61]
|
|
node _T_2224 = and(ic_miss_buff_data_valid_bypass_index, _T_2223) @[el2_ifu_mem_ctl.scala 454:43]
|
|
node _T_2225 = bits(byp_fetch_index, 0, 0) @[el2_ifu_mem_ctl.scala 454:83]
|
|
node _T_2226 = and(_T_2224, _T_2225) @[el2_ifu_mem_ctl.scala 454:65]
|
|
node _T_2227 = and(_T_2226, ic_miss_buff_data_valid_inc_bypass_index) @[el2_ifu_mem_ctl.scala 454:87]
|
|
node _T_2228 = or(_T_2222, _T_2227) @[el2_ifu_mem_ctl.scala 453:88]
|
|
node _T_2229 = bits(byp_fetch_index, 4, 2) @[el2_ifu_mem_ctl.scala 455:61]
|
|
node _T_2230 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2231 = eq(_T_2229, _T_2230) @[el2_ifu_mem_ctl.scala 455:87]
|
|
node _T_2232 = and(ic_miss_buff_data_valid_bypass_index, _T_2231) @[el2_ifu_mem_ctl.scala 455:43]
|
|
node miss_buff_hit_unq_f = or(_T_2228, _T_2232) @[el2_ifu_mem_ctl.scala 454:131]
|
|
node _T_2233 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 457:30]
|
|
node _T_2234 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 457:68]
|
|
node _T_2235 = and(miss_buff_hit_unq_f, _T_2234) @[el2_ifu_mem_ctl.scala 457:66]
|
|
node _T_2236 = and(_T_2233, _T_2235) @[el2_ifu_mem_ctl.scala 457:43]
|
|
stream_hit_f <= _T_2236 @[el2_ifu_mem_ctl.scala 457:16]
|
|
node _T_2237 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 458:31]
|
|
node _T_2238 = eq(miss_wrap_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 458:70]
|
|
node _T_2239 = and(miss_buff_hit_unq_f, _T_2238) @[el2_ifu_mem_ctl.scala 458:68]
|
|
node _T_2240 = eq(_T_2239, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 458:46]
|
|
node _T_2241 = and(_T_2237, _T_2240) @[el2_ifu_mem_ctl.scala 458:44]
|
|
node _T_2242 = and(_T_2241, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 458:84]
|
|
stream_miss_f <= _T_2242 @[el2_ifu_mem_ctl.scala 458:17]
|
|
node _T_2243 = bits(byp_fetch_index, 4, 1) @[el2_ifu_mem_ctl.scala 459:35]
|
|
node _T_2244 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2245 = eq(_T_2243, _T_2244) @[el2_ifu_mem_ctl.scala 459:60]
|
|
node _T_2246 = and(_T_2245, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 459:94]
|
|
node _T_2247 = and(_T_2246, stream_hit_f) @[el2_ifu_mem_ctl.scala 459:112]
|
|
stream_eol_f <= _T_2247 @[el2_ifu_mem_ctl.scala 459:16]
|
|
node _T_2248 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 460:55]
|
|
node _T_2249 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 460:87]
|
|
node _T_2250 = or(_T_2248, _T_2249) @[el2_ifu_mem_ctl.scala 460:74]
|
|
node _T_2251 = and(miss_buff_hit_unq_f, _T_2250) @[el2_ifu_mem_ctl.scala 460:41]
|
|
crit_byp_hit_f <= _T_2251 @[el2_ifu_mem_ctl.scala 460:18]
|
|
node _T_2252 = bits(ifu_bus_rid_ff, 2, 1) @[el2_ifu_mem_ctl.scala 463:37]
|
|
node _T_2253 = bits(ifu_bus_rid_ff, 0, 0) @[el2_ifu_mem_ctl.scala 463:70]
|
|
node _T_2254 = eq(_T_2253, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 463:55]
|
|
node other_tag = cat(_T_2252, _T_2254) @[Cat.scala 29:58]
|
|
node _T_2255 = eq(other_tag, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 464:81]
|
|
node _T_2256 = bits(_T_2255, 0, 0) @[el2_ifu_mem_ctl.scala 464:89]
|
|
node _T_2257 = bits(ic_miss_buff_data_valid, 0, 0) @[el2_ifu_mem_ctl.scala 464:120]
|
|
node _T_2258 = eq(other_tag, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 464:81]
|
|
node _T_2259 = bits(_T_2258, 0, 0) @[el2_ifu_mem_ctl.scala 464:89]
|
|
node _T_2260 = bits(ic_miss_buff_data_valid, 1, 1) @[el2_ifu_mem_ctl.scala 464:120]
|
|
node _T_2261 = eq(other_tag, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 464:81]
|
|
node _T_2262 = bits(_T_2261, 0, 0) @[el2_ifu_mem_ctl.scala 464:89]
|
|
node _T_2263 = bits(ic_miss_buff_data_valid, 2, 2) @[el2_ifu_mem_ctl.scala 464:120]
|
|
node _T_2264 = eq(other_tag, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 464:81]
|
|
node _T_2265 = bits(_T_2264, 0, 0) @[el2_ifu_mem_ctl.scala 464:89]
|
|
node _T_2266 = bits(ic_miss_buff_data_valid, 3, 3) @[el2_ifu_mem_ctl.scala 464:120]
|
|
node _T_2267 = eq(other_tag, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 464:81]
|
|
node _T_2268 = bits(_T_2267, 0, 0) @[el2_ifu_mem_ctl.scala 464:89]
|
|
node _T_2269 = bits(ic_miss_buff_data_valid, 4, 4) @[el2_ifu_mem_ctl.scala 464:120]
|
|
node _T_2270 = eq(other_tag, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 464:81]
|
|
node _T_2271 = bits(_T_2270, 0, 0) @[el2_ifu_mem_ctl.scala 464:89]
|
|
node _T_2272 = bits(ic_miss_buff_data_valid, 5, 5) @[el2_ifu_mem_ctl.scala 464:120]
|
|
node _T_2273 = eq(other_tag, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 464:81]
|
|
node _T_2274 = bits(_T_2273, 0, 0) @[el2_ifu_mem_ctl.scala 464:89]
|
|
node _T_2275 = bits(ic_miss_buff_data_valid, 6, 6) @[el2_ifu_mem_ctl.scala 464:120]
|
|
node _T_2276 = eq(other_tag, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 464:81]
|
|
node _T_2277 = bits(_T_2276, 0, 0) @[el2_ifu_mem_ctl.scala 464:89]
|
|
node _T_2278 = bits(ic_miss_buff_data_valid, 7, 7) @[el2_ifu_mem_ctl.scala 464:120]
|
|
node _T_2279 = mux(_T_2256, _T_2257, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2280 = mux(_T_2259, _T_2260, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2281 = mux(_T_2262, _T_2263, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2282 = mux(_T_2265, _T_2266, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2283 = mux(_T_2268, _T_2269, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2284 = mux(_T_2271, _T_2272, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2285 = mux(_T_2274, _T_2275, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2286 = mux(_T_2277, _T_2278, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2287 = or(_T_2279, _T_2280) @[Mux.scala 27:72]
|
|
node _T_2288 = or(_T_2287, _T_2281) @[Mux.scala 27:72]
|
|
node _T_2289 = or(_T_2288, _T_2282) @[Mux.scala 27:72]
|
|
node _T_2290 = or(_T_2289, _T_2283) @[Mux.scala 27:72]
|
|
node _T_2291 = or(_T_2290, _T_2284) @[Mux.scala 27:72]
|
|
node _T_2292 = or(_T_2291, _T_2285) @[Mux.scala 27:72]
|
|
node _T_2293 = or(_T_2292, _T_2286) @[Mux.scala 27:72]
|
|
wire second_half_available : UInt<1> @[Mux.scala 27:72]
|
|
second_half_available <= _T_2293 @[Mux.scala 27:72]
|
|
node _T_2294 = and(second_half_available, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 465:46]
|
|
write_ic_16_bytes <= _T_2294 @[el2_ifu_mem_ctl.scala 465:21]
|
|
node _T_2295 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2296 = eq(_T_2295, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2297 = bits(_T_2296, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2298 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2299 = eq(_T_2298, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2300 = bits(_T_2299, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2301 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2302 = eq(_T_2301, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2303 = bits(_T_2302, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2304 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2305 = eq(_T_2304, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2306 = bits(_T_2305, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2307 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2308 = eq(_T_2307, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2309 = bits(_T_2308, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2310 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2311 = eq(_T_2310, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2312 = bits(_T_2311, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2313 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2314 = eq(_T_2313, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2315 = bits(_T_2314, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2316 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2317 = eq(_T_2316, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2318 = bits(_T_2317, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2319 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2320 = eq(_T_2319, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2321 = bits(_T_2320, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2322 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2323 = eq(_T_2322, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2324 = bits(_T_2323, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2325 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2326 = eq(_T_2325, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2327 = bits(_T_2326, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2328 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2329 = eq(_T_2328, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2330 = bits(_T_2329, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2331 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2332 = eq(_T_2331, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2333 = bits(_T_2332, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2334 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2335 = eq(_T_2334, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2336 = bits(_T_2335, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2337 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2338 = eq(_T_2337, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2339 = bits(_T_2338, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2340 = cat(other_tag, UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_2341 = eq(_T_2340, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 466:89]
|
|
node _T_2342 = bits(_T_2341, 0, 0) @[el2_ifu_mem_ctl.scala 466:97]
|
|
node _T_2343 = mux(_T_2297, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2344 = mux(_T_2300, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2345 = mux(_T_2303, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2346 = mux(_T_2306, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2347 = mux(_T_2309, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2348 = mux(_T_2312, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2349 = mux(_T_2315, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2350 = mux(_T_2318, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2351 = mux(_T_2321, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2352 = mux(_T_2324, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2353 = mux(_T_2327, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2354 = mux(_T_2330, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2355 = mux(_T_2333, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2356 = mux(_T_2336, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2357 = mux(_T_2339, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2358 = mux(_T_2342, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2359 = or(_T_2343, _T_2344) @[Mux.scala 27:72]
|
|
node _T_2360 = or(_T_2359, _T_2345) @[Mux.scala 27:72]
|
|
node _T_2361 = or(_T_2360, _T_2346) @[Mux.scala 27:72]
|
|
node _T_2362 = or(_T_2361, _T_2347) @[Mux.scala 27:72]
|
|
node _T_2363 = or(_T_2362, _T_2348) @[Mux.scala 27:72]
|
|
node _T_2364 = or(_T_2363, _T_2349) @[Mux.scala 27:72]
|
|
node _T_2365 = or(_T_2364, _T_2350) @[Mux.scala 27:72]
|
|
node _T_2366 = or(_T_2365, _T_2351) @[Mux.scala 27:72]
|
|
node _T_2367 = or(_T_2366, _T_2352) @[Mux.scala 27:72]
|
|
node _T_2368 = or(_T_2367, _T_2353) @[Mux.scala 27:72]
|
|
node _T_2369 = or(_T_2368, _T_2354) @[Mux.scala 27:72]
|
|
node _T_2370 = or(_T_2369, _T_2355) @[Mux.scala 27:72]
|
|
node _T_2371 = or(_T_2370, _T_2356) @[Mux.scala 27:72]
|
|
node _T_2372 = or(_T_2371, _T_2357) @[Mux.scala 27:72]
|
|
node _T_2373 = or(_T_2372, _T_2358) @[Mux.scala 27:72]
|
|
wire _T_2374 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2374 <= _T_2373 @[Mux.scala 27:72]
|
|
node _T_2375 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2376 = eq(_T_2375, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2377 = bits(_T_2376, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2378 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2379 = eq(_T_2378, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2380 = bits(_T_2379, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2381 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2382 = eq(_T_2381, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2383 = bits(_T_2382, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2384 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2385 = eq(_T_2384, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2386 = bits(_T_2385, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2387 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2388 = eq(_T_2387, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2389 = bits(_T_2388, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2390 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2391 = eq(_T_2390, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2392 = bits(_T_2391, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2393 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2394 = eq(_T_2393, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2395 = bits(_T_2394, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2396 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2397 = eq(_T_2396, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2398 = bits(_T_2397, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2399 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2400 = eq(_T_2399, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2401 = bits(_T_2400, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2402 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2403 = eq(_T_2402, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2404 = bits(_T_2403, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2405 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2406 = eq(_T_2405, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2407 = bits(_T_2406, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2408 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2409 = eq(_T_2408, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2410 = bits(_T_2409, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2411 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2412 = eq(_T_2411, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2413 = bits(_T_2412, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2414 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2415 = eq(_T_2414, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2416 = bits(_T_2415, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2417 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2418 = eq(_T_2417, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2419 = bits(_T_2418, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2420 = cat(other_tag, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_2421 = eq(_T_2420, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 467:66]
|
|
node _T_2422 = bits(_T_2421, 0, 0) @[el2_ifu_mem_ctl.scala 467:74]
|
|
node _T_2423 = mux(_T_2377, ic_miss_buff_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2424 = mux(_T_2380, ic_miss_buff_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2425 = mux(_T_2383, ic_miss_buff_data[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2426 = mux(_T_2386, ic_miss_buff_data[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2427 = mux(_T_2389, ic_miss_buff_data[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2428 = mux(_T_2392, ic_miss_buff_data[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2429 = mux(_T_2395, ic_miss_buff_data[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2430 = mux(_T_2398, ic_miss_buff_data[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2431 = mux(_T_2401, ic_miss_buff_data[8], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2432 = mux(_T_2404, ic_miss_buff_data[9], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2433 = mux(_T_2407, ic_miss_buff_data[10], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2434 = mux(_T_2410, ic_miss_buff_data[11], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2435 = mux(_T_2413, ic_miss_buff_data[12], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2436 = mux(_T_2416, ic_miss_buff_data[13], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2437 = mux(_T_2419, ic_miss_buff_data[14], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2438 = mux(_T_2422, ic_miss_buff_data[15], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2439 = or(_T_2423, _T_2424) @[Mux.scala 27:72]
|
|
node _T_2440 = or(_T_2439, _T_2425) @[Mux.scala 27:72]
|
|
node _T_2441 = or(_T_2440, _T_2426) @[Mux.scala 27:72]
|
|
node _T_2442 = or(_T_2441, _T_2427) @[Mux.scala 27:72]
|
|
node _T_2443 = or(_T_2442, _T_2428) @[Mux.scala 27:72]
|
|
node _T_2444 = or(_T_2443, _T_2429) @[Mux.scala 27:72]
|
|
node _T_2445 = or(_T_2444, _T_2430) @[Mux.scala 27:72]
|
|
node _T_2446 = or(_T_2445, _T_2431) @[Mux.scala 27:72]
|
|
node _T_2447 = or(_T_2446, _T_2432) @[Mux.scala 27:72]
|
|
node _T_2448 = or(_T_2447, _T_2433) @[Mux.scala 27:72]
|
|
node _T_2449 = or(_T_2448, _T_2434) @[Mux.scala 27:72]
|
|
node _T_2450 = or(_T_2449, _T_2435) @[Mux.scala 27:72]
|
|
node _T_2451 = or(_T_2450, _T_2436) @[Mux.scala 27:72]
|
|
node _T_2452 = or(_T_2451, _T_2437) @[Mux.scala 27:72]
|
|
node _T_2453 = or(_T_2452, _T_2438) @[Mux.scala 27:72]
|
|
wire _T_2454 : UInt<32> @[Mux.scala 27:72]
|
|
_T_2454 <= _T_2453 @[Mux.scala 27:72]
|
|
node _T_2455 = cat(_T_2374, _T_2454) @[Cat.scala 29:58]
|
|
ic_miss_buff_half <= _T_2455 @[el2_ifu_mem_ctl.scala 466:21]
|
|
node _T_2456 = and(io.ic_tag_perr, sel_ic_data) @[el2_ifu_mem_ctl.scala 471:44]
|
|
node _T_2457 = or(ifc_region_acc_fault_final_f, ifc_bus_acc_fault_f) @[el2_ifu_mem_ctl.scala 471:91]
|
|
node _T_2458 = eq(_T_2457, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 471:60]
|
|
node _T_2459 = and(_T_2456, _T_2458) @[el2_ifu_mem_ctl.scala 471:58]
|
|
ic_rd_parity_final_err <= _T_2459 @[el2_ifu_mem_ctl.scala 471:26]
|
|
wire ifu_ic_rw_int_addr_ff : UInt<7>
|
|
ifu_ic_rw_int_addr_ff <= UInt<1>("h00")
|
|
wire perr_sb_write_status : UInt<1>
|
|
perr_sb_write_status <= UInt<1>("h00")
|
|
reg perr_ic_index_ff : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when perr_sb_write_status : @[Reg.scala 28:19]
|
|
perr_ic_index_ff <= ifu_ic_rw_int_addr_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
wire perr_sel_invalidate : UInt<1>
|
|
perr_sel_invalidate <= UInt<1>("h00")
|
|
node _T_2460 = bits(perr_sel_invalidate, 0, 0) @[Bitwise.scala 72:15]
|
|
node perr_err_inv_way = mux(_T_2460, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2461 = eq(perr_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 478:34]
|
|
iccm_correct_ecc <= _T_2461 @[el2_ifu_mem_ctl.scala 478:20]
|
|
node dma_sb_err_state = eq(perr_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 479:37]
|
|
wire dma_sb_err_state_ff : UInt<1> @[el2_ifu_mem_ctl.scala 480:33]
|
|
node _T_2462 = eq(dma_sb_err_state_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 481:49]
|
|
node _T_2463 = and(iccm_correct_ecc, _T_2462) @[el2_ifu_mem_ctl.scala 481:47]
|
|
io.iccm_buf_correct_ecc <= _T_2463 @[el2_ifu_mem_ctl.scala 481:27]
|
|
reg _T_2464 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 482:58]
|
|
_T_2464 <= dma_sb_err_state @[el2_ifu_mem_ctl.scala 482:58]
|
|
dma_sb_err_state_ff <= _T_2464 @[el2_ifu_mem_ctl.scala 482:23]
|
|
wire perr_nxtstate : UInt<3>
|
|
perr_nxtstate <= UInt<1>("h00")
|
|
wire perr_state_en : UInt<1>
|
|
perr_state_en <= UInt<1>("h00")
|
|
wire iccm_error_start : UInt<1>
|
|
iccm_error_start <= UInt<1>("h00")
|
|
node _T_2465 = eq(UInt<3>("h00"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2465 : @[Conditional.scala 40:58]
|
|
node _T_2466 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 490:89]
|
|
node _T_2467 = and(io.ic_error_start, _T_2466) @[el2_ifu_mem_ctl.scala 490:87]
|
|
node _T_2468 = bits(_T_2467, 0, 0) @[el2_ifu_mem_ctl.scala 490:110]
|
|
node _T_2469 = mux(_T_2468, UInt<3>("h01"), UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 490:67]
|
|
node _T_2470 = mux(io.iccm_dma_sb_error, UInt<3>("h04"), _T_2469) @[el2_ifu_mem_ctl.scala 490:27]
|
|
perr_nxtstate <= _T_2470 @[el2_ifu_mem_ctl.scala 490:21]
|
|
node _T_2471 = or(iccm_error_start, io.ic_error_start) @[el2_ifu_mem_ctl.scala 491:44]
|
|
node _T_2472 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 491:67]
|
|
node _T_2473 = and(_T_2471, _T_2472) @[el2_ifu_mem_ctl.scala 491:65]
|
|
node _T_2474 = or(_T_2473, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 491:88]
|
|
node _T_2475 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 491:114]
|
|
node _T_2476 = and(_T_2474, _T_2475) @[el2_ifu_mem_ctl.scala 491:112]
|
|
perr_state_en <= _T_2476 @[el2_ifu_mem_ctl.scala 491:21]
|
|
perr_sb_write_status <= perr_state_en @[el2_ifu_mem_ctl.scala 492:28]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2477 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2477 : @[Conditional.scala 39:67]
|
|
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 495:21]
|
|
node _T_2478 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 496:50]
|
|
perr_state_en <= _T_2478 @[el2_ifu_mem_ctl.scala 496:21]
|
|
node _T_2479 = and(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 497:56]
|
|
perr_sel_invalidate <= _T_2479 @[el2_ifu_mem_ctl.scala 497:27]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2480 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2480 : @[Conditional.scala 39:67]
|
|
node _T_2481 = and(io.dec_tlu_flush_err_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_mem_ctl.scala 500:54]
|
|
node _T_2482 = or(_T_2481, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 500:84]
|
|
node _T_2483 = bits(_T_2482, 0, 0) @[el2_ifu_mem_ctl.scala 500:115]
|
|
node _T_2484 = mux(_T_2483, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 500:27]
|
|
perr_nxtstate <= _T_2484 @[el2_ifu_mem_ctl.scala 500:21]
|
|
node _T_2485 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 501:50]
|
|
perr_state_en <= _T_2485 @[el2_ifu_mem_ctl.scala 501:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2486 = eq(UInt<3>("h04"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2486 : @[Conditional.scala 39:67]
|
|
node _T_2487 = mux(io.dec_tlu_force_halt, UInt<3>("h00"), UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 504:27]
|
|
perr_nxtstate <= _T_2487 @[el2_ifu_mem_ctl.scala 504:21]
|
|
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 505:21]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2488 = eq(UInt<3>("h03"), perr_state) @[Conditional.scala 37:30]
|
|
when _T_2488 : @[Conditional.scala 39:67]
|
|
perr_nxtstate <= UInt<3>("h00") @[el2_ifu_mem_ctl.scala 508:21]
|
|
perr_state_en <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 509:21]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_2489 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when perr_state_en : @[Reg.scala 28:19]
|
|
_T_2489 <= perr_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
perr_state <= _T_2489 @[el2_ifu_mem_ctl.scala 512:14]
|
|
wire err_stop_nxtstate : UInt<2>
|
|
err_stop_nxtstate <= UInt<1>("h00")
|
|
wire err_stop_state_en : UInt<1>
|
|
err_stop_state_en <= UInt<1>("h00")
|
|
io.iccm_correction_state <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 516:28]
|
|
node _T_2490 = eq(UInt<2>("h00"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2490 : @[Conditional.scala 40:58]
|
|
err_stop_nxtstate <= UInt<2>("h01") @[el2_ifu_mem_ctl.scala 520:25]
|
|
node _T_2491 = eq(perr_state, UInt<3>("h02")) @[el2_ifu_mem_ctl.scala 521:66]
|
|
node _T_2492 = and(io.dec_tlu_flush_err_wb, _T_2491) @[el2_ifu_mem_ctl.scala 521:52]
|
|
node _T_2493 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 521:83]
|
|
node _T_2494 = and(_T_2492, _T_2493) @[el2_ifu_mem_ctl.scala 521:81]
|
|
err_stop_state_en <= _T_2494 @[el2_ifu_mem_ctl.scala 521:25]
|
|
skip @[Conditional.scala 40:58]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2495 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2495 : @[Conditional.scala 39:67]
|
|
node _T_2496 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 524:59]
|
|
node _T_2497 = or(_T_2496, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 524:86]
|
|
node _T_2498 = bits(_T_2497, 0, 0) @[el2_ifu_mem_ctl.scala 524:117]
|
|
node _T_2499 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 525:31]
|
|
node _T_2500 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 525:56]
|
|
node _T_2501 = and(_T_2500, two_byte_instr) @[el2_ifu_mem_ctl.scala 525:59]
|
|
node _T_2502 = or(_T_2499, _T_2501) @[el2_ifu_mem_ctl.scala 525:38]
|
|
node _T_2503 = bits(_T_2502, 0, 0) @[el2_ifu_mem_ctl.scala 525:83]
|
|
node _T_2504 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 526:31]
|
|
node _T_2505 = bits(_T_2504, 0, 0) @[el2_ifu_mem_ctl.scala 526:41]
|
|
node _T_2506 = mux(_T_2505, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_mem_ctl.scala 526:14]
|
|
node _T_2507 = mux(_T_2503, UInt<2>("h03"), _T_2506) @[el2_ifu_mem_ctl.scala 525:12]
|
|
node _T_2508 = mux(_T_2498, UInt<2>("h00"), _T_2507) @[el2_ifu_mem_ctl.scala 524:31]
|
|
err_stop_nxtstate <= _T_2508 @[el2_ifu_mem_ctl.scala 524:25]
|
|
node _T_2509 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 527:54]
|
|
node _T_2510 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 527:99]
|
|
node _T_2511 = or(_T_2509, _T_2510) @[el2_ifu_mem_ctl.scala 527:81]
|
|
node _T_2512 = or(_T_2511, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 527:103]
|
|
node _T_2513 = or(_T_2512, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 527:126]
|
|
err_stop_state_en <= _T_2513 @[el2_ifu_mem_ctl.scala 527:25]
|
|
node _T_2514 = bits(io.ifu_fetch_val, 1, 0) @[el2_ifu_mem_ctl.scala 528:43]
|
|
node _T_2515 = eq(_T_2514, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 528:48]
|
|
node _T_2516 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 528:75]
|
|
node _T_2517 = and(_T_2516, two_byte_instr) @[el2_ifu_mem_ctl.scala 528:79]
|
|
node _T_2518 = or(_T_2515, _T_2517) @[el2_ifu_mem_ctl.scala 528:56]
|
|
node _T_2519 = or(io.exu_flush_final, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 528:122]
|
|
node _T_2520 = eq(_T_2519, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 528:101]
|
|
node _T_2521 = and(_T_2518, _T_2520) @[el2_ifu_mem_ctl.scala 528:99]
|
|
err_stop_fetch <= _T_2521 @[el2_ifu_mem_ctl.scala 528:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 529:32]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2522 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2522 : @[Conditional.scala 39:67]
|
|
node _T_2523 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 532:59]
|
|
node _T_2524 = or(_T_2523, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 532:86]
|
|
node _T_2525 = bits(_T_2524, 0, 0) @[el2_ifu_mem_ctl.scala 532:111]
|
|
node _T_2526 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 533:46]
|
|
node _T_2527 = bits(_T_2526, 0, 0) @[el2_ifu_mem_ctl.scala 533:50]
|
|
node _T_2528 = mux(_T_2527, UInt<2>("h03"), UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 533:29]
|
|
node _T_2529 = mux(_T_2525, UInt<2>("h00"), _T_2528) @[el2_ifu_mem_ctl.scala 532:31]
|
|
err_stop_nxtstate <= _T_2529 @[el2_ifu_mem_ctl.scala 532:25]
|
|
node _T_2530 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 534:54]
|
|
node _T_2531 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 534:99]
|
|
node _T_2532 = or(_T_2530, _T_2531) @[el2_ifu_mem_ctl.scala 534:81]
|
|
node _T_2533 = or(_T_2532, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 534:103]
|
|
err_stop_state_en <= _T_2533 @[el2_ifu_mem_ctl.scala 534:25]
|
|
node _T_2534 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_mem_ctl.scala 535:41]
|
|
node _T_2535 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 535:47]
|
|
node _T_2536 = and(_T_2534, _T_2535) @[el2_ifu_mem_ctl.scala 535:45]
|
|
node _T_2537 = eq(io.dec_tlu_i0_commit_cmt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 535:69]
|
|
node _T_2538 = and(_T_2536, _T_2537) @[el2_ifu_mem_ctl.scala 535:67]
|
|
err_stop_fetch <= _T_2538 @[el2_ifu_mem_ctl.scala 535:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 536:32]
|
|
skip @[Conditional.scala 39:67]
|
|
else : @[Conditional.scala 39:67]
|
|
node _T_2539 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30]
|
|
when _T_2539 : @[Conditional.scala 39:67]
|
|
node _T_2540 = eq(io.dec_tlu_flush_err_wb, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 539:62]
|
|
node _T_2541 = and(io.dec_tlu_flush_lower_wb, _T_2540) @[el2_ifu_mem_ctl.scala 539:60]
|
|
node _T_2542 = or(_T_2541, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 539:88]
|
|
node _T_2543 = or(_T_2542, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 539:115]
|
|
node _T_2544 = bits(_T_2543, 0, 0) @[el2_ifu_mem_ctl.scala 539:140]
|
|
node _T_2545 = bits(io.dec_tlu_flush_err_wb, 0, 0) @[el2_ifu_mem_ctl.scala 540:60]
|
|
node _T_2546 = mux(_T_2545, UInt<2>("h01"), UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 540:29]
|
|
node _T_2547 = mux(_T_2544, UInt<2>("h00"), _T_2546) @[el2_ifu_mem_ctl.scala 539:31]
|
|
err_stop_nxtstate <= _T_2547 @[el2_ifu_mem_ctl.scala 539:25]
|
|
node _T_2548 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_i0_commit_cmt) @[el2_ifu_mem_ctl.scala 541:54]
|
|
node _T_2549 = or(_T_2548, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 541:81]
|
|
err_stop_state_en <= _T_2549 @[el2_ifu_mem_ctl.scala 541:25]
|
|
err_stop_fetch <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 542:22]
|
|
io.iccm_correction_state <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 543:32]
|
|
skip @[Conditional.scala 39:67]
|
|
reg _T_2550 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when err_stop_state_en : @[Reg.scala 28:19]
|
|
_T_2550 <= err_stop_nxtstate @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
err_stop_state <= _T_2550 @[el2_ifu_mem_ctl.scala 546:18]
|
|
bus_ifu_bus_clk_en <= io.ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 547:22]
|
|
reg bus_ifu_bus_clk_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 548:61]
|
|
bus_ifu_bus_clk_en_ff <= bus_ifu_bus_clk_en @[el2_ifu_mem_ctl.scala 548:61]
|
|
reg _T_2551 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 549:52]
|
|
_T_2551 <= scnd_miss_req_in @[el2_ifu_mem_ctl.scala 549:52]
|
|
scnd_miss_req_q <= _T_2551 @[el2_ifu_mem_ctl.scala 549:19]
|
|
reg scnd_miss_req_ff2 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 550:57]
|
|
scnd_miss_req_ff2 <= scnd_miss_req @[el2_ifu_mem_ctl.scala 550:57]
|
|
node _T_2552 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 551:39]
|
|
node _T_2553 = and(scnd_miss_req_q, _T_2552) @[el2_ifu_mem_ctl.scala 551:36]
|
|
scnd_miss_req <= _T_2553 @[el2_ifu_mem_ctl.scala 551:17]
|
|
wire bus_cmd_req_hold : UInt<1>
|
|
bus_cmd_req_hold <= UInt<1>("h00")
|
|
wire ifu_bus_cmd_valid : UInt<1>
|
|
ifu_bus_cmd_valid <= UInt<1>("h00")
|
|
wire bus_cmd_beat_count : UInt<3>
|
|
bus_cmd_beat_count <= UInt<1>("h00")
|
|
wire ifu_bus_cmd_ready : UInt<1>
|
|
ifu_bus_cmd_ready <= UInt<1>("h00")
|
|
node _T_2554 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 556:45]
|
|
node _T_2555 = or(_T_2554, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 556:64]
|
|
node _T_2556 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 556:87]
|
|
node _T_2557 = and(_T_2555, _T_2556) @[el2_ifu_mem_ctl.scala 556:85]
|
|
node _T_2558 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2559 = eq(bus_cmd_beat_count, _T_2558) @[el2_ifu_mem_ctl.scala 556:133]
|
|
node _T_2560 = and(_T_2559, ifu_bus_cmd_valid) @[el2_ifu_mem_ctl.scala 556:164]
|
|
node _T_2561 = and(_T_2560, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 556:184]
|
|
node _T_2562 = and(_T_2561, miss_pending) @[el2_ifu_mem_ctl.scala 556:204]
|
|
node _T_2563 = eq(_T_2562, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 556:112]
|
|
node ifc_bus_ic_req_ff_in = and(_T_2557, _T_2563) @[el2_ifu_mem_ctl.scala 556:110]
|
|
node _T_2564 = or(bus_ifu_bus_clk_en, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 557:80]
|
|
reg _T_2565 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2564 : @[Reg.scala 28:19]
|
|
_T_2565 <= ifc_bus_ic_req_ff_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_cmd_valid <= _T_2565 @[el2_ifu_mem_ctl.scala 557:21]
|
|
wire bus_cmd_sent : UInt<1>
|
|
bus_cmd_sent <= UInt<1>("h00")
|
|
node _T_2566 = or(ic_act_miss_f, bus_cmd_req_hold) @[el2_ifu_mem_ctl.scala 559:39]
|
|
node _T_2567 = eq(bus_cmd_sent, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 559:61]
|
|
node _T_2568 = and(_T_2566, _T_2567) @[el2_ifu_mem_ctl.scala 559:59]
|
|
node _T_2569 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 559:77]
|
|
node bus_cmd_req_in = and(_T_2568, _T_2569) @[el2_ifu_mem_ctl.scala 559:75]
|
|
reg _T_2570 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 560:49]
|
|
_T_2570 <= bus_cmd_req_in @[el2_ifu_mem_ctl.scala 560:49]
|
|
bus_cmd_sent <= _T_2570 @[el2_ifu_mem_ctl.scala 560:16]
|
|
io.ifu_axi_arvalid <= ifu_bus_cmd_valid @[el2_ifu_mem_ctl.scala 562:22]
|
|
node _T_2571 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2572 = mux(_T_2571, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2573 = and(bus_rd_addr_count, _T_2572) @[el2_ifu_mem_ctl.scala 563:40]
|
|
io.ifu_axi_arid <= _T_2573 @[el2_ifu_mem_ctl.scala 563:19]
|
|
node _T_2574 = cat(ifu_ic_req_addr_f, UInt<3>("h00")) @[Cat.scala 29:58]
|
|
node _T_2575 = bits(ifu_bus_cmd_valid, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2576 = mux(_T_2575, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2577 = and(_T_2574, _T_2576) @[el2_ifu_mem_ctl.scala 564:57]
|
|
io.ifu_axi_araddr <= _T_2577 @[el2_ifu_mem_ctl.scala 564:21]
|
|
io.ifu_axi_arsize <= UInt<3>("h03") @[el2_ifu_mem_ctl.scala 565:21]
|
|
io.ifu_axi_arcache <= UInt<4>("h0f") @[el2_ifu_mem_ctl.scala 566:22]
|
|
node _T_2578 = bits(ifu_ic_req_addr_f, 28, 25) @[el2_ifu_mem_ctl.scala 567:43]
|
|
io.ifu_axi_arregion <= _T_2578 @[el2_ifu_mem_ctl.scala 567:23]
|
|
io.ifu_axi_arburst <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 568:22]
|
|
io.ifu_axi_rready <= UInt<1>("h01") @[el2_ifu_mem_ctl.scala 569:21]
|
|
reg ifu_bus_arready_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_arready_unq_ff <= io.ifu_axi_arready @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_rvalid_unq_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_rvalid_unq_ff <= io.ifu_axi_rvalid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_arvalid_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_arvalid_ff <= io.ifu_axi_arvalid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg ifu_bus_rresp_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
ifu_bus_rresp_ff <= io.ifu_axi_rresp @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
reg _T_2579 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
_T_2579 <= io.ifu_axi_rdata @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_rdata_ff <= _T_2579 @[el2_ifu_mem_ctl.scala 579:20]
|
|
reg _T_2580 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when bus_ifu_bus_clk_en : @[Reg.scala 28:19]
|
|
_T_2580 <= io.ifu_axi_rid @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ifu_bus_rid_ff <= _T_2580 @[el2_ifu_mem_ctl.scala 580:18]
|
|
ifu_bus_cmd_ready <= io.ifu_axi_arready @[el2_ifu_mem_ctl.scala 581:21]
|
|
ifu_bus_rsp_valid <= io.ifu_axi_rvalid @[el2_ifu_mem_ctl.scala 582:21]
|
|
ifu_bus_rsp_ready <= io.ifu_axi_rready @[el2_ifu_mem_ctl.scala 583:21]
|
|
ifu_bus_rsp_tag <= io.ifu_axi_rid @[el2_ifu_mem_ctl.scala 584:19]
|
|
ic_miss_buff_data_in <= io.ifu_axi_rdata @[el2_ifu_mem_ctl.scala 585:21]
|
|
node ifu_bus_rvalid = and(ifu_bus_rsp_valid, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 587:42]
|
|
node ifu_bus_arready = and(io.ifu_axi_arready, bus_ifu_bus_clk_en) @[el2_ifu_mem_ctl.scala 588:45]
|
|
node ifu_bus_arready_ff = and(ifu_bus_arready_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 589:51]
|
|
node ifu_bus_rvalid_ff = and(ifu_bus_rvalid_unq_ff, bus_ifu_bus_clk_en_ff) @[el2_ifu_mem_ctl.scala 590:49]
|
|
node _T_2581 = and(io.ifu_axi_arvalid, ifu_bus_arready) @[el2_ifu_mem_ctl.scala 591:35]
|
|
node _T_2582 = and(_T_2581, miss_pending) @[el2_ifu_mem_ctl.scala 591:53]
|
|
node _T_2583 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 591:70]
|
|
node _T_2584 = and(_T_2582, _T_2583) @[el2_ifu_mem_ctl.scala 591:68]
|
|
bus_cmd_sent <= _T_2584 @[el2_ifu_mem_ctl.scala 591:16]
|
|
wire bus_last_data_beat : UInt<1>
|
|
bus_last_data_beat <= UInt<1>("h00")
|
|
node _T_2585 = eq(bus_last_data_beat, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 593:50]
|
|
node _T_2586 = and(bus_ifu_wr_en_ff, _T_2585) @[el2_ifu_mem_ctl.scala 593:48]
|
|
node _T_2587 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 593:72]
|
|
node bus_inc_data_beat_cnt = and(_T_2586, _T_2587) @[el2_ifu_mem_ctl.scala 593:70]
|
|
node _T_2588 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 594:68]
|
|
node _T_2589 = or(ic_act_miss_f, _T_2588) @[el2_ifu_mem_ctl.scala 594:48]
|
|
node bus_reset_data_beat_cnt = or(_T_2589, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 594:91]
|
|
node _T_2590 = eq(bus_inc_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 595:32]
|
|
node _T_2591 = eq(bus_reset_data_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 595:57]
|
|
node bus_hold_data_beat_cnt = and(_T_2590, _T_2591) @[el2_ifu_mem_ctl.scala 595:55]
|
|
wire bus_data_beat_count : UInt<3>
|
|
bus_data_beat_count <= UInt<1>("h00")
|
|
node _T_2592 = add(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 597:115]
|
|
node _T_2593 = tail(_T_2592, 1) @[el2_ifu_mem_ctl.scala 597:115]
|
|
node _T_2594 = mux(bus_reset_data_beat_cnt, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2595 = mux(bus_inc_data_beat_cnt, _T_2593, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2596 = mux(bus_hold_data_beat_cnt, bus_data_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2597 = or(_T_2594, _T_2595) @[Mux.scala 27:72]
|
|
node _T_2598 = or(_T_2597, _T_2596) @[Mux.scala 27:72]
|
|
wire _T_2599 : UInt<3> @[Mux.scala 27:72]
|
|
_T_2599 <= _T_2598 @[Mux.scala 27:72]
|
|
bus_new_data_beat_count <= _T_2599 @[el2_ifu_mem_ctl.scala 597:27]
|
|
reg _T_2600 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 598:56]
|
|
_T_2600 <= bus_new_data_beat_count @[el2_ifu_mem_ctl.scala 598:56]
|
|
bus_data_beat_count <= _T_2600 @[el2_ifu_mem_ctl.scala 598:23]
|
|
node _T_2601 = and(bus_ifu_wr_en_ff, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 599:49]
|
|
node _T_2602 = eq(scnd_miss_req, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 599:73]
|
|
node _T_2603 = and(_T_2601, _T_2602) @[el2_ifu_mem_ctl.scala 599:71]
|
|
node _T_2604 = eq(ic_act_miss_f, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 599:116]
|
|
node _T_2605 = and(last_data_recieved_ff, _T_2604) @[el2_ifu_mem_ctl.scala 599:114]
|
|
node last_data_recieved_in = or(_T_2603, _T_2605) @[el2_ifu_mem_ctl.scala 599:89]
|
|
reg _T_2606 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 600:58]
|
|
_T_2606 <= last_data_recieved_in @[el2_ifu_mem_ctl.scala 600:58]
|
|
last_data_recieved_ff <= _T_2606 @[el2_ifu_mem_ctl.scala 600:25]
|
|
node _T_2607 = eq(miss_pending, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 602:35]
|
|
node _T_2608 = bits(imb_ff, 4, 2) @[el2_ifu_mem_ctl.scala 602:56]
|
|
node _T_2609 = bits(imb_scnd_ff, 4, 2) @[el2_ifu_mem_ctl.scala 603:39]
|
|
node _T_2610 = add(bus_rd_addr_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 604:45]
|
|
node _T_2611 = tail(_T_2610, 1) @[el2_ifu_mem_ctl.scala 604:45]
|
|
node _T_2612 = mux(bus_cmd_sent, _T_2611, bus_rd_addr_count) @[el2_ifu_mem_ctl.scala 604:12]
|
|
node _T_2613 = mux(scnd_miss_req_q, _T_2609, _T_2612) @[el2_ifu_mem_ctl.scala 603:10]
|
|
node bus_new_rd_addr_count = mux(_T_2607, _T_2608, _T_2613) @[el2_ifu_mem_ctl.scala 602:34]
|
|
node _T_2614 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 605:81]
|
|
node _T_2615 = or(_T_2614, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 605:97]
|
|
reg _T_2616 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2615 : @[Reg.scala 28:19]
|
|
_T_2616 <= bus_new_rd_addr_count @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
bus_rd_addr_count <= _T_2616 @[el2_ifu_mem_ctl.scala 605:21]
|
|
node _T_2617 = and(ifu_bus_cmd_valid, ifu_bus_cmd_ready) @[el2_ifu_mem_ctl.scala 607:48]
|
|
node _T_2618 = and(_T_2617, miss_pending) @[el2_ifu_mem_ctl.scala 607:68]
|
|
node _T_2619 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 607:85]
|
|
node bus_inc_cmd_beat_cnt = and(_T_2618, _T_2619) @[el2_ifu_mem_ctl.scala 607:83]
|
|
node _T_2620 = eq(uncacheable_miss_in, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 608:51]
|
|
node _T_2621 = and(ic_act_miss_f, _T_2620) @[el2_ifu_mem_ctl.scala 608:49]
|
|
node bus_reset_cmd_beat_cnt_0 = or(_T_2621, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 608:73]
|
|
node bus_reset_cmd_beat_cnt_secondlast = and(ic_act_miss_f, uncacheable_miss_in) @[el2_ifu_mem_ctl.scala 609:57]
|
|
node _T_2622 = eq(bus_inc_cmd_beat_cnt, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 610:31]
|
|
node _T_2623 = or(ic_act_miss_f, scnd_miss_req) @[el2_ifu_mem_ctl.scala 610:71]
|
|
node _T_2624 = or(_T_2623, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 610:87]
|
|
node _T_2625 = eq(_T_2624, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 610:55]
|
|
node bus_hold_cmd_beat_cnt = and(_T_2622, _T_2625) @[el2_ifu_mem_ctl.scala 610:53]
|
|
node _T_2626 = or(bus_inc_cmd_beat_cnt, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 611:46]
|
|
node bus_cmd_beat_en = or(_T_2626, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 611:62]
|
|
node _T_2627 = bits(bus_reset_cmd_beat_cnt_secondlast, 0, 0) @[el2_ifu_mem_ctl.scala 612:107]
|
|
node _T_2628 = add(bus_cmd_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 613:46]
|
|
node _T_2629 = tail(_T_2628, 1) @[el2_ifu_mem_ctl.scala 613:46]
|
|
node _T_2630 = mux(bus_reset_cmd_beat_cnt_0, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2631 = mux(_T_2627, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2632 = mux(bus_inc_cmd_beat_cnt, _T_2629, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2633 = mux(bus_hold_cmd_beat_cnt, bus_cmd_beat_count, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
node _T_2634 = or(_T_2630, _T_2631) @[Mux.scala 27:72]
|
|
node _T_2635 = or(_T_2634, _T_2632) @[Mux.scala 27:72]
|
|
node _T_2636 = or(_T_2635, _T_2633) @[Mux.scala 27:72]
|
|
wire bus_new_cmd_beat_count : UInt<3> @[Mux.scala 27:72]
|
|
bus_new_cmd_beat_count <= _T_2636 @[Mux.scala 27:72]
|
|
node _T_2637 = or(bus_ifu_bus_clk_en, ic_act_miss_f) @[el2_ifu_mem_ctl.scala 614:84]
|
|
node _T_2638 = or(_T_2637, io.dec_tlu_force_halt) @[el2_ifu_mem_ctl.scala 614:100]
|
|
node _T_2639 = and(_T_2638, bus_cmd_beat_en) @[el2_ifu_mem_ctl.scala 614:125]
|
|
reg _T_2640 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_2639 : @[Reg.scala 28:19]
|
|
_T_2640 <= bus_new_cmd_beat_count @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
bus_cmd_beat_count <= _T_2640 @[el2_ifu_mem_ctl.scala 614:22]
|
|
node _T_2641 = eq(bus_data_beat_count, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 615:69]
|
|
node _T_2642 = andr(bus_data_beat_count) @[el2_ifu_mem_ctl.scala 615:101]
|
|
node _T_2643 = mux(uncacheable_miss_ff, _T_2641, _T_2642) @[el2_ifu_mem_ctl.scala 615:28]
|
|
bus_last_data_beat <= _T_2643 @[el2_ifu_mem_ctl.scala 615:22]
|
|
node _T_2644 = and(ifu_bus_rvalid, miss_pending) @[el2_ifu_mem_ctl.scala 616:35]
|
|
bus_ifu_wr_en <= _T_2644 @[el2_ifu_mem_ctl.scala 616:17]
|
|
node _T_2645 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 617:41]
|
|
bus_ifu_wr_en_ff <= _T_2645 @[el2_ifu_mem_ctl.scala 617:20]
|
|
node _T_2646 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 618:44]
|
|
node _T_2647 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 618:61]
|
|
node _T_2648 = and(_T_2646, _T_2647) @[el2_ifu_mem_ctl.scala 618:59]
|
|
node _T_2649 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 618:103]
|
|
node _T_2650 = eq(_T_2649, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 618:84]
|
|
node _T_2651 = and(_T_2648, _T_2650) @[el2_ifu_mem_ctl.scala 618:82]
|
|
node _T_2652 = and(_T_2651, write_ic_16_bytes) @[el2_ifu_mem_ctl.scala 618:108]
|
|
bus_ifu_wr_en_ff_q <= _T_2652 @[el2_ifu_mem_ctl.scala 618:22]
|
|
node _T_2653 = and(ifu_bus_rvalid_ff, miss_pending) @[el2_ifu_mem_ctl.scala 619:51]
|
|
node _T_2654 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 619:68]
|
|
node bus_ifu_wr_en_ff_wo_err = and(_T_2653, _T_2654) @[el2_ifu_mem_ctl.scala 619:66]
|
|
reg ic_act_miss_f_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 620:61]
|
|
ic_act_miss_f_delayed <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 620:61]
|
|
node _T_2655 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 621:66]
|
|
node _T_2656 = and(ic_act_miss_f_delayed, _T_2655) @[el2_ifu_mem_ctl.scala 621:53]
|
|
node _T_2657 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 621:86]
|
|
node _T_2658 = and(_T_2656, _T_2657) @[el2_ifu_mem_ctl.scala 621:84]
|
|
reset_tag_valid_for_miss <= _T_2658 @[el2_ifu_mem_ctl.scala 621:28]
|
|
node _T_2659 = orr(io.ifu_axi_rresp) @[el2_ifu_mem_ctl.scala 622:47]
|
|
node _T_2660 = and(_T_2659, ifu_bus_rvalid) @[el2_ifu_mem_ctl.scala 622:50]
|
|
node _T_2661 = and(_T_2660, miss_pending) @[el2_ifu_mem_ctl.scala 622:68]
|
|
bus_ifu_wr_data_error <= _T_2661 @[el2_ifu_mem_ctl.scala 622:25]
|
|
node _T_2662 = orr(ifu_bus_rresp_ff) @[el2_ifu_mem_ctl.scala 623:48]
|
|
node _T_2663 = and(_T_2662, ifu_bus_rvalid_ff) @[el2_ifu_mem_ctl.scala 623:52]
|
|
node _T_2664 = and(_T_2663, miss_pending) @[el2_ifu_mem_ctl.scala 623:73]
|
|
bus_ifu_wr_data_error_ff <= _T_2664 @[el2_ifu_mem_ctl.scala 623:28]
|
|
wire ifc_dma_access_ok_d : UInt<1>
|
|
ifc_dma_access_ok_d <= UInt<1>("h00")
|
|
reg ifc_dma_access_ok_prev : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 625:62]
|
|
ifc_dma_access_ok_prev <= ifc_dma_access_ok_d @[el2_ifu_mem_ctl.scala 625:62]
|
|
node _T_2665 = or(ic_crit_wd_rdy_new_in, ic_crit_wd_rdy_new_ff) @[el2_ifu_mem_ctl.scala 626:43]
|
|
ic_crit_wd_rdy <= _T_2665 @[el2_ifu_mem_ctl.scala 626:18]
|
|
node _T_2666 = and(bus_last_data_beat, bus_ifu_wr_en_ff) @[el2_ifu_mem_ctl.scala 627:35]
|
|
last_beat <= _T_2666 @[el2_ifu_mem_ctl.scala 627:13]
|
|
reset_beat_cnt <= bus_reset_data_beat_cnt @[el2_ifu_mem_ctl.scala 628:18]
|
|
node _T_2667 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 630:50]
|
|
node _T_2668 = and(io.ifc_dma_access_ok, _T_2667) @[el2_ifu_mem_ctl.scala 630:47]
|
|
node _T_2669 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 630:70]
|
|
node _T_2670 = and(_T_2668, _T_2669) @[el2_ifu_mem_ctl.scala 630:68]
|
|
ifc_dma_access_ok_d <= _T_2670 @[el2_ifu_mem_ctl.scala 630:23]
|
|
node _T_2671 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 631:54]
|
|
node _T_2672 = and(io.ifc_dma_access_ok, _T_2671) @[el2_ifu_mem_ctl.scala 631:51]
|
|
node _T_2673 = and(_T_2672, ifc_dma_access_ok_prev) @[el2_ifu_mem_ctl.scala 631:72]
|
|
node _T_2674 = eq(perr_state, UInt<3>("h00")) @[el2_ifu_mem_ctl.scala 631:111]
|
|
node _T_2675 = and(_T_2673, _T_2674) @[el2_ifu_mem_ctl.scala 631:97]
|
|
node _T_2676 = eq(io.iccm_dma_sb_error, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 631:129]
|
|
node ifc_dma_access_q_ok = and(_T_2675, _T_2676) @[el2_ifu_mem_ctl.scala 631:127]
|
|
io.iccm_ready <= ifc_dma_access_q_ok @[el2_ifu_mem_ctl.scala 632:17]
|
|
reg _T_2677 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 633:51]
|
|
_T_2677 <= io.dma_iccm_req @[el2_ifu_mem_ctl.scala 633:51]
|
|
dma_iccm_req_f <= _T_2677 @[el2_ifu_mem_ctl.scala 633:18]
|
|
node _T_2678 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 634:40]
|
|
node _T_2679 = and(_T_2678, io.dma_mem_write) @[el2_ifu_mem_ctl.scala 634:58]
|
|
node _T_2680 = or(_T_2679, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 634:79]
|
|
io.iccm_wren <= _T_2680 @[el2_ifu_mem_ctl.scala 634:16]
|
|
node _T_2681 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 635:40]
|
|
node _T_2682 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 635:60]
|
|
node _T_2683 = and(_T_2681, _T_2682) @[el2_ifu_mem_ctl.scala 635:58]
|
|
node _T_2684 = and(io.ifc_iccm_access_bf, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 635:104]
|
|
node _T_2685 = or(_T_2683, _T_2684) @[el2_ifu_mem_ctl.scala 635:79]
|
|
io.iccm_rden <= _T_2685 @[el2_ifu_mem_ctl.scala 635:16]
|
|
node _T_2686 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 636:43]
|
|
node _T_2687 = eq(io.dma_mem_write, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 636:63]
|
|
node iccm_dma_rden = and(_T_2686, _T_2687) @[el2_ifu_mem_ctl.scala 636:61]
|
|
node _T_2688 = bits(io.dma_iccm_req, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_2689 = mux(_T_2688, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_2690 = and(_T_2689, io.dma_mem_sz) @[el2_ifu_mem_ctl.scala 637:47]
|
|
io.iccm_wr_size <= _T_2690 @[el2_ifu_mem_ctl.scala 637:19]
|
|
node _T_2691 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 638:54]
|
|
wire _T_2692 : UInt<1>[18] @[el2_lib.scala 250:18]
|
|
wire _T_2693 : UInt<1>[18] @[el2_lib.scala 251:18]
|
|
wire _T_2694 : UInt<1>[18] @[el2_lib.scala 252:18]
|
|
wire _T_2695 : UInt<1>[15] @[el2_lib.scala 253:18]
|
|
wire _T_2696 : UInt<1>[15] @[el2_lib.scala 254:18]
|
|
wire _T_2697 : UInt<1>[6] @[el2_lib.scala 255:18]
|
|
node _T_2698 = bits(_T_2691, 0, 0) @[el2_lib.scala 262:36]
|
|
_T_2693[0] <= _T_2698 @[el2_lib.scala 262:30]
|
|
node _T_2699 = bits(_T_2691, 0, 0) @[el2_lib.scala 263:36]
|
|
_T_2694[0] <= _T_2699 @[el2_lib.scala 263:30]
|
|
node _T_2700 = bits(_T_2691, 0, 0) @[el2_lib.scala 266:36]
|
|
_T_2697[0] <= _T_2700 @[el2_lib.scala 266:30]
|
|
node _T_2701 = bits(_T_2691, 1, 1) @[el2_lib.scala 261:36]
|
|
_T_2692[0] <= _T_2701 @[el2_lib.scala 261:30]
|
|
node _T_2702 = bits(_T_2691, 1, 1) @[el2_lib.scala 263:36]
|
|
_T_2694[1] <= _T_2702 @[el2_lib.scala 263:30]
|
|
node _T_2703 = bits(_T_2691, 1, 1) @[el2_lib.scala 266:36]
|
|
_T_2697[1] <= _T_2703 @[el2_lib.scala 266:30]
|
|
node _T_2704 = bits(_T_2691, 2, 2) @[el2_lib.scala 263:36]
|
|
_T_2694[2] <= _T_2704 @[el2_lib.scala 263:30]
|
|
node _T_2705 = bits(_T_2691, 2, 2) @[el2_lib.scala 266:36]
|
|
_T_2697[2] <= _T_2705 @[el2_lib.scala 266:30]
|
|
node _T_2706 = bits(_T_2691, 3, 3) @[el2_lib.scala 261:36]
|
|
_T_2692[1] <= _T_2706 @[el2_lib.scala 261:30]
|
|
node _T_2707 = bits(_T_2691, 3, 3) @[el2_lib.scala 262:36]
|
|
_T_2693[1] <= _T_2707 @[el2_lib.scala 262:30]
|
|
node _T_2708 = bits(_T_2691, 3, 3) @[el2_lib.scala 266:36]
|
|
_T_2697[3] <= _T_2708 @[el2_lib.scala 266:30]
|
|
node _T_2709 = bits(_T_2691, 4, 4) @[el2_lib.scala 262:36]
|
|
_T_2693[2] <= _T_2709 @[el2_lib.scala 262:30]
|
|
node _T_2710 = bits(_T_2691, 4, 4) @[el2_lib.scala 266:36]
|
|
_T_2697[4] <= _T_2710 @[el2_lib.scala 266:30]
|
|
node _T_2711 = bits(_T_2691, 5, 5) @[el2_lib.scala 261:36]
|
|
_T_2692[2] <= _T_2711 @[el2_lib.scala 261:30]
|
|
node _T_2712 = bits(_T_2691, 5, 5) @[el2_lib.scala 266:36]
|
|
_T_2697[5] <= _T_2712 @[el2_lib.scala 266:30]
|
|
node _T_2713 = bits(_T_2691, 6, 6) @[el2_lib.scala 261:36]
|
|
_T_2692[3] <= _T_2713 @[el2_lib.scala 261:30]
|
|
node _T_2714 = bits(_T_2691, 6, 6) @[el2_lib.scala 262:36]
|
|
_T_2693[3] <= _T_2714 @[el2_lib.scala 262:30]
|
|
node _T_2715 = bits(_T_2691, 6, 6) @[el2_lib.scala 263:36]
|
|
_T_2694[3] <= _T_2715 @[el2_lib.scala 263:30]
|
|
node _T_2716 = bits(_T_2691, 6, 6) @[el2_lib.scala 264:36]
|
|
_T_2695[0] <= _T_2716 @[el2_lib.scala 264:30]
|
|
node _T_2717 = bits(_T_2691, 6, 6) @[el2_lib.scala 265:36]
|
|
_T_2696[0] <= _T_2717 @[el2_lib.scala 265:30]
|
|
node _T_2718 = bits(_T_2691, 7, 7) @[el2_lib.scala 262:36]
|
|
_T_2693[4] <= _T_2718 @[el2_lib.scala 262:30]
|
|
node _T_2719 = bits(_T_2691, 7, 7) @[el2_lib.scala 263:36]
|
|
_T_2694[4] <= _T_2719 @[el2_lib.scala 263:30]
|
|
node _T_2720 = bits(_T_2691, 7, 7) @[el2_lib.scala 264:36]
|
|
_T_2695[1] <= _T_2720 @[el2_lib.scala 264:30]
|
|
node _T_2721 = bits(_T_2691, 7, 7) @[el2_lib.scala 265:36]
|
|
_T_2696[1] <= _T_2721 @[el2_lib.scala 265:30]
|
|
node _T_2722 = bits(_T_2691, 8, 8) @[el2_lib.scala 261:36]
|
|
_T_2692[4] <= _T_2722 @[el2_lib.scala 261:30]
|
|
node _T_2723 = bits(_T_2691, 8, 8) @[el2_lib.scala 263:36]
|
|
_T_2694[5] <= _T_2723 @[el2_lib.scala 263:30]
|
|
node _T_2724 = bits(_T_2691, 8, 8) @[el2_lib.scala 264:36]
|
|
_T_2695[2] <= _T_2724 @[el2_lib.scala 264:30]
|
|
node _T_2725 = bits(_T_2691, 8, 8) @[el2_lib.scala 265:36]
|
|
_T_2696[2] <= _T_2725 @[el2_lib.scala 265:30]
|
|
node _T_2726 = bits(_T_2691, 9, 9) @[el2_lib.scala 263:36]
|
|
_T_2694[6] <= _T_2726 @[el2_lib.scala 263:30]
|
|
node _T_2727 = bits(_T_2691, 9, 9) @[el2_lib.scala 264:36]
|
|
_T_2695[3] <= _T_2727 @[el2_lib.scala 264:30]
|
|
node _T_2728 = bits(_T_2691, 9, 9) @[el2_lib.scala 265:36]
|
|
_T_2696[3] <= _T_2728 @[el2_lib.scala 265:30]
|
|
node _T_2729 = bits(_T_2691, 10, 10) @[el2_lib.scala 261:36]
|
|
_T_2692[5] <= _T_2729 @[el2_lib.scala 261:30]
|
|
node _T_2730 = bits(_T_2691, 10, 10) @[el2_lib.scala 262:36]
|
|
_T_2693[5] <= _T_2730 @[el2_lib.scala 262:30]
|
|
node _T_2731 = bits(_T_2691, 10, 10) @[el2_lib.scala 264:36]
|
|
_T_2695[4] <= _T_2731 @[el2_lib.scala 264:30]
|
|
node _T_2732 = bits(_T_2691, 10, 10) @[el2_lib.scala 265:36]
|
|
_T_2696[4] <= _T_2732 @[el2_lib.scala 265:30]
|
|
node _T_2733 = bits(_T_2691, 11, 11) @[el2_lib.scala 262:36]
|
|
_T_2693[6] <= _T_2733 @[el2_lib.scala 262:30]
|
|
node _T_2734 = bits(_T_2691, 11, 11) @[el2_lib.scala 264:36]
|
|
_T_2695[5] <= _T_2734 @[el2_lib.scala 264:30]
|
|
node _T_2735 = bits(_T_2691, 11, 11) @[el2_lib.scala 265:36]
|
|
_T_2696[5] <= _T_2735 @[el2_lib.scala 265:30]
|
|
node _T_2736 = bits(_T_2691, 12, 12) @[el2_lib.scala 261:36]
|
|
_T_2692[6] <= _T_2736 @[el2_lib.scala 261:30]
|
|
node _T_2737 = bits(_T_2691, 12, 12) @[el2_lib.scala 264:36]
|
|
_T_2695[6] <= _T_2737 @[el2_lib.scala 264:30]
|
|
node _T_2738 = bits(_T_2691, 12, 12) @[el2_lib.scala 265:36]
|
|
_T_2696[6] <= _T_2738 @[el2_lib.scala 265:30]
|
|
node _T_2739 = bits(_T_2691, 13, 13) @[el2_lib.scala 264:36]
|
|
_T_2695[7] <= _T_2739 @[el2_lib.scala 264:30]
|
|
node _T_2740 = bits(_T_2691, 13, 13) @[el2_lib.scala 265:36]
|
|
_T_2696[7] <= _T_2740 @[el2_lib.scala 265:30]
|
|
node _T_2741 = bits(_T_2691, 14, 14) @[el2_lib.scala 261:36]
|
|
_T_2692[7] <= _T_2741 @[el2_lib.scala 261:30]
|
|
node _T_2742 = bits(_T_2691, 14, 14) @[el2_lib.scala 262:36]
|
|
_T_2693[7] <= _T_2742 @[el2_lib.scala 262:30]
|
|
node _T_2743 = bits(_T_2691, 14, 14) @[el2_lib.scala 263:36]
|
|
_T_2694[7] <= _T_2743 @[el2_lib.scala 263:30]
|
|
node _T_2744 = bits(_T_2691, 14, 14) @[el2_lib.scala 265:36]
|
|
_T_2696[8] <= _T_2744 @[el2_lib.scala 265:30]
|
|
node _T_2745 = bits(_T_2691, 15, 15) @[el2_lib.scala 262:36]
|
|
_T_2693[8] <= _T_2745 @[el2_lib.scala 262:30]
|
|
node _T_2746 = bits(_T_2691, 15, 15) @[el2_lib.scala 263:36]
|
|
_T_2694[8] <= _T_2746 @[el2_lib.scala 263:30]
|
|
node _T_2747 = bits(_T_2691, 15, 15) @[el2_lib.scala 265:36]
|
|
_T_2696[9] <= _T_2747 @[el2_lib.scala 265:30]
|
|
node _T_2748 = bits(_T_2691, 16, 16) @[el2_lib.scala 261:36]
|
|
_T_2692[8] <= _T_2748 @[el2_lib.scala 261:30]
|
|
node _T_2749 = bits(_T_2691, 16, 16) @[el2_lib.scala 263:36]
|
|
_T_2694[9] <= _T_2749 @[el2_lib.scala 263:30]
|
|
node _T_2750 = bits(_T_2691, 16, 16) @[el2_lib.scala 265:36]
|
|
_T_2696[10] <= _T_2750 @[el2_lib.scala 265:30]
|
|
node _T_2751 = bits(_T_2691, 17, 17) @[el2_lib.scala 263:36]
|
|
_T_2694[10] <= _T_2751 @[el2_lib.scala 263:30]
|
|
node _T_2752 = bits(_T_2691, 17, 17) @[el2_lib.scala 265:36]
|
|
_T_2696[11] <= _T_2752 @[el2_lib.scala 265:30]
|
|
node _T_2753 = bits(_T_2691, 18, 18) @[el2_lib.scala 261:36]
|
|
_T_2692[9] <= _T_2753 @[el2_lib.scala 261:30]
|
|
node _T_2754 = bits(_T_2691, 18, 18) @[el2_lib.scala 262:36]
|
|
_T_2693[9] <= _T_2754 @[el2_lib.scala 262:30]
|
|
node _T_2755 = bits(_T_2691, 18, 18) @[el2_lib.scala 265:36]
|
|
_T_2696[12] <= _T_2755 @[el2_lib.scala 265:30]
|
|
node _T_2756 = bits(_T_2691, 19, 19) @[el2_lib.scala 262:36]
|
|
_T_2693[10] <= _T_2756 @[el2_lib.scala 262:30]
|
|
node _T_2757 = bits(_T_2691, 19, 19) @[el2_lib.scala 265:36]
|
|
_T_2696[13] <= _T_2757 @[el2_lib.scala 265:30]
|
|
node _T_2758 = bits(_T_2691, 20, 20) @[el2_lib.scala 261:36]
|
|
_T_2692[10] <= _T_2758 @[el2_lib.scala 261:30]
|
|
node _T_2759 = bits(_T_2691, 20, 20) @[el2_lib.scala 265:36]
|
|
_T_2696[14] <= _T_2759 @[el2_lib.scala 265:30]
|
|
node _T_2760 = bits(_T_2691, 21, 21) @[el2_lib.scala 261:36]
|
|
_T_2692[11] <= _T_2760 @[el2_lib.scala 261:30]
|
|
node _T_2761 = bits(_T_2691, 21, 21) @[el2_lib.scala 262:36]
|
|
_T_2693[11] <= _T_2761 @[el2_lib.scala 262:30]
|
|
node _T_2762 = bits(_T_2691, 21, 21) @[el2_lib.scala 263:36]
|
|
_T_2694[11] <= _T_2762 @[el2_lib.scala 263:30]
|
|
node _T_2763 = bits(_T_2691, 21, 21) @[el2_lib.scala 264:36]
|
|
_T_2695[8] <= _T_2763 @[el2_lib.scala 264:30]
|
|
node _T_2764 = bits(_T_2691, 22, 22) @[el2_lib.scala 262:36]
|
|
_T_2693[12] <= _T_2764 @[el2_lib.scala 262:30]
|
|
node _T_2765 = bits(_T_2691, 22, 22) @[el2_lib.scala 263:36]
|
|
_T_2694[12] <= _T_2765 @[el2_lib.scala 263:30]
|
|
node _T_2766 = bits(_T_2691, 22, 22) @[el2_lib.scala 264:36]
|
|
_T_2695[9] <= _T_2766 @[el2_lib.scala 264:30]
|
|
node _T_2767 = bits(_T_2691, 23, 23) @[el2_lib.scala 261:36]
|
|
_T_2692[12] <= _T_2767 @[el2_lib.scala 261:30]
|
|
node _T_2768 = bits(_T_2691, 23, 23) @[el2_lib.scala 263:36]
|
|
_T_2694[13] <= _T_2768 @[el2_lib.scala 263:30]
|
|
node _T_2769 = bits(_T_2691, 23, 23) @[el2_lib.scala 264:36]
|
|
_T_2695[10] <= _T_2769 @[el2_lib.scala 264:30]
|
|
node _T_2770 = bits(_T_2691, 24, 24) @[el2_lib.scala 263:36]
|
|
_T_2694[14] <= _T_2770 @[el2_lib.scala 263:30]
|
|
node _T_2771 = bits(_T_2691, 24, 24) @[el2_lib.scala 264:36]
|
|
_T_2695[11] <= _T_2771 @[el2_lib.scala 264:30]
|
|
node _T_2772 = bits(_T_2691, 25, 25) @[el2_lib.scala 261:36]
|
|
_T_2692[13] <= _T_2772 @[el2_lib.scala 261:30]
|
|
node _T_2773 = bits(_T_2691, 25, 25) @[el2_lib.scala 262:36]
|
|
_T_2693[13] <= _T_2773 @[el2_lib.scala 262:30]
|
|
node _T_2774 = bits(_T_2691, 25, 25) @[el2_lib.scala 264:36]
|
|
_T_2695[12] <= _T_2774 @[el2_lib.scala 264:30]
|
|
node _T_2775 = bits(_T_2691, 26, 26) @[el2_lib.scala 262:36]
|
|
_T_2693[14] <= _T_2775 @[el2_lib.scala 262:30]
|
|
node _T_2776 = bits(_T_2691, 26, 26) @[el2_lib.scala 264:36]
|
|
_T_2695[13] <= _T_2776 @[el2_lib.scala 264:30]
|
|
node _T_2777 = bits(_T_2691, 27, 27) @[el2_lib.scala 261:36]
|
|
_T_2692[14] <= _T_2777 @[el2_lib.scala 261:30]
|
|
node _T_2778 = bits(_T_2691, 27, 27) @[el2_lib.scala 264:36]
|
|
_T_2695[14] <= _T_2778 @[el2_lib.scala 264:30]
|
|
node _T_2779 = bits(_T_2691, 28, 28) @[el2_lib.scala 261:36]
|
|
_T_2692[15] <= _T_2779 @[el2_lib.scala 261:30]
|
|
node _T_2780 = bits(_T_2691, 28, 28) @[el2_lib.scala 262:36]
|
|
_T_2693[15] <= _T_2780 @[el2_lib.scala 262:30]
|
|
node _T_2781 = bits(_T_2691, 28, 28) @[el2_lib.scala 263:36]
|
|
_T_2694[15] <= _T_2781 @[el2_lib.scala 263:30]
|
|
node _T_2782 = bits(_T_2691, 29, 29) @[el2_lib.scala 262:36]
|
|
_T_2693[16] <= _T_2782 @[el2_lib.scala 262:30]
|
|
node _T_2783 = bits(_T_2691, 29, 29) @[el2_lib.scala 263:36]
|
|
_T_2694[16] <= _T_2783 @[el2_lib.scala 263:30]
|
|
node _T_2784 = bits(_T_2691, 30, 30) @[el2_lib.scala 261:36]
|
|
_T_2692[16] <= _T_2784 @[el2_lib.scala 261:30]
|
|
node _T_2785 = bits(_T_2691, 30, 30) @[el2_lib.scala 263:36]
|
|
_T_2694[17] <= _T_2785 @[el2_lib.scala 263:30]
|
|
node _T_2786 = bits(_T_2691, 31, 31) @[el2_lib.scala 261:36]
|
|
_T_2692[17] <= _T_2786 @[el2_lib.scala 261:30]
|
|
node _T_2787 = bits(_T_2691, 31, 31) @[el2_lib.scala 262:36]
|
|
_T_2693[17] <= _T_2787 @[el2_lib.scala 262:30]
|
|
node _T_2788 = cat(_T_2692[1], _T_2692[0]) @[el2_lib.scala 268:22]
|
|
node _T_2789 = cat(_T_2692[3], _T_2692[2]) @[el2_lib.scala 268:22]
|
|
node _T_2790 = cat(_T_2789, _T_2788) @[el2_lib.scala 268:22]
|
|
node _T_2791 = cat(_T_2692[5], _T_2692[4]) @[el2_lib.scala 268:22]
|
|
node _T_2792 = cat(_T_2692[8], _T_2692[7]) @[el2_lib.scala 268:22]
|
|
node _T_2793 = cat(_T_2792, _T_2692[6]) @[el2_lib.scala 268:22]
|
|
node _T_2794 = cat(_T_2793, _T_2791) @[el2_lib.scala 268:22]
|
|
node _T_2795 = cat(_T_2794, _T_2790) @[el2_lib.scala 268:22]
|
|
node _T_2796 = cat(_T_2692[10], _T_2692[9]) @[el2_lib.scala 268:22]
|
|
node _T_2797 = cat(_T_2692[12], _T_2692[11]) @[el2_lib.scala 268:22]
|
|
node _T_2798 = cat(_T_2797, _T_2796) @[el2_lib.scala 268:22]
|
|
node _T_2799 = cat(_T_2692[14], _T_2692[13]) @[el2_lib.scala 268:22]
|
|
node _T_2800 = cat(_T_2692[17], _T_2692[16]) @[el2_lib.scala 268:22]
|
|
node _T_2801 = cat(_T_2800, _T_2692[15]) @[el2_lib.scala 268:22]
|
|
node _T_2802 = cat(_T_2801, _T_2799) @[el2_lib.scala 268:22]
|
|
node _T_2803 = cat(_T_2802, _T_2798) @[el2_lib.scala 268:22]
|
|
node _T_2804 = cat(_T_2803, _T_2795) @[el2_lib.scala 268:22]
|
|
node _T_2805 = xorr(_T_2804) @[el2_lib.scala 268:29]
|
|
node _T_2806 = cat(_T_2693[1], _T_2693[0]) @[el2_lib.scala 268:39]
|
|
node _T_2807 = cat(_T_2693[3], _T_2693[2]) @[el2_lib.scala 268:39]
|
|
node _T_2808 = cat(_T_2807, _T_2806) @[el2_lib.scala 268:39]
|
|
node _T_2809 = cat(_T_2693[5], _T_2693[4]) @[el2_lib.scala 268:39]
|
|
node _T_2810 = cat(_T_2693[8], _T_2693[7]) @[el2_lib.scala 268:39]
|
|
node _T_2811 = cat(_T_2810, _T_2693[6]) @[el2_lib.scala 268:39]
|
|
node _T_2812 = cat(_T_2811, _T_2809) @[el2_lib.scala 268:39]
|
|
node _T_2813 = cat(_T_2812, _T_2808) @[el2_lib.scala 268:39]
|
|
node _T_2814 = cat(_T_2693[10], _T_2693[9]) @[el2_lib.scala 268:39]
|
|
node _T_2815 = cat(_T_2693[12], _T_2693[11]) @[el2_lib.scala 268:39]
|
|
node _T_2816 = cat(_T_2815, _T_2814) @[el2_lib.scala 268:39]
|
|
node _T_2817 = cat(_T_2693[14], _T_2693[13]) @[el2_lib.scala 268:39]
|
|
node _T_2818 = cat(_T_2693[17], _T_2693[16]) @[el2_lib.scala 268:39]
|
|
node _T_2819 = cat(_T_2818, _T_2693[15]) @[el2_lib.scala 268:39]
|
|
node _T_2820 = cat(_T_2819, _T_2817) @[el2_lib.scala 268:39]
|
|
node _T_2821 = cat(_T_2820, _T_2816) @[el2_lib.scala 268:39]
|
|
node _T_2822 = cat(_T_2821, _T_2813) @[el2_lib.scala 268:39]
|
|
node _T_2823 = xorr(_T_2822) @[el2_lib.scala 268:46]
|
|
node _T_2824 = cat(_T_2694[1], _T_2694[0]) @[el2_lib.scala 268:56]
|
|
node _T_2825 = cat(_T_2694[3], _T_2694[2]) @[el2_lib.scala 268:56]
|
|
node _T_2826 = cat(_T_2825, _T_2824) @[el2_lib.scala 268:56]
|
|
node _T_2827 = cat(_T_2694[5], _T_2694[4]) @[el2_lib.scala 268:56]
|
|
node _T_2828 = cat(_T_2694[8], _T_2694[7]) @[el2_lib.scala 268:56]
|
|
node _T_2829 = cat(_T_2828, _T_2694[6]) @[el2_lib.scala 268:56]
|
|
node _T_2830 = cat(_T_2829, _T_2827) @[el2_lib.scala 268:56]
|
|
node _T_2831 = cat(_T_2830, _T_2826) @[el2_lib.scala 268:56]
|
|
node _T_2832 = cat(_T_2694[10], _T_2694[9]) @[el2_lib.scala 268:56]
|
|
node _T_2833 = cat(_T_2694[12], _T_2694[11]) @[el2_lib.scala 268:56]
|
|
node _T_2834 = cat(_T_2833, _T_2832) @[el2_lib.scala 268:56]
|
|
node _T_2835 = cat(_T_2694[14], _T_2694[13]) @[el2_lib.scala 268:56]
|
|
node _T_2836 = cat(_T_2694[17], _T_2694[16]) @[el2_lib.scala 268:56]
|
|
node _T_2837 = cat(_T_2836, _T_2694[15]) @[el2_lib.scala 268:56]
|
|
node _T_2838 = cat(_T_2837, _T_2835) @[el2_lib.scala 268:56]
|
|
node _T_2839 = cat(_T_2838, _T_2834) @[el2_lib.scala 268:56]
|
|
node _T_2840 = cat(_T_2839, _T_2831) @[el2_lib.scala 268:56]
|
|
node _T_2841 = xorr(_T_2840) @[el2_lib.scala 268:63]
|
|
node _T_2842 = cat(_T_2695[2], _T_2695[1]) @[el2_lib.scala 268:73]
|
|
node _T_2843 = cat(_T_2842, _T_2695[0]) @[el2_lib.scala 268:73]
|
|
node _T_2844 = cat(_T_2695[4], _T_2695[3]) @[el2_lib.scala 268:73]
|
|
node _T_2845 = cat(_T_2695[6], _T_2695[5]) @[el2_lib.scala 268:73]
|
|
node _T_2846 = cat(_T_2845, _T_2844) @[el2_lib.scala 268:73]
|
|
node _T_2847 = cat(_T_2846, _T_2843) @[el2_lib.scala 268:73]
|
|
node _T_2848 = cat(_T_2695[8], _T_2695[7]) @[el2_lib.scala 268:73]
|
|
node _T_2849 = cat(_T_2695[10], _T_2695[9]) @[el2_lib.scala 268:73]
|
|
node _T_2850 = cat(_T_2849, _T_2848) @[el2_lib.scala 268:73]
|
|
node _T_2851 = cat(_T_2695[12], _T_2695[11]) @[el2_lib.scala 268:73]
|
|
node _T_2852 = cat(_T_2695[14], _T_2695[13]) @[el2_lib.scala 268:73]
|
|
node _T_2853 = cat(_T_2852, _T_2851) @[el2_lib.scala 268:73]
|
|
node _T_2854 = cat(_T_2853, _T_2850) @[el2_lib.scala 268:73]
|
|
node _T_2855 = cat(_T_2854, _T_2847) @[el2_lib.scala 268:73]
|
|
node _T_2856 = xorr(_T_2855) @[el2_lib.scala 268:80]
|
|
node _T_2857 = cat(_T_2696[2], _T_2696[1]) @[el2_lib.scala 268:90]
|
|
node _T_2858 = cat(_T_2857, _T_2696[0]) @[el2_lib.scala 268:90]
|
|
node _T_2859 = cat(_T_2696[4], _T_2696[3]) @[el2_lib.scala 268:90]
|
|
node _T_2860 = cat(_T_2696[6], _T_2696[5]) @[el2_lib.scala 268:90]
|
|
node _T_2861 = cat(_T_2860, _T_2859) @[el2_lib.scala 268:90]
|
|
node _T_2862 = cat(_T_2861, _T_2858) @[el2_lib.scala 268:90]
|
|
node _T_2863 = cat(_T_2696[8], _T_2696[7]) @[el2_lib.scala 268:90]
|
|
node _T_2864 = cat(_T_2696[10], _T_2696[9]) @[el2_lib.scala 268:90]
|
|
node _T_2865 = cat(_T_2864, _T_2863) @[el2_lib.scala 268:90]
|
|
node _T_2866 = cat(_T_2696[12], _T_2696[11]) @[el2_lib.scala 268:90]
|
|
node _T_2867 = cat(_T_2696[14], _T_2696[13]) @[el2_lib.scala 268:90]
|
|
node _T_2868 = cat(_T_2867, _T_2866) @[el2_lib.scala 268:90]
|
|
node _T_2869 = cat(_T_2868, _T_2865) @[el2_lib.scala 268:90]
|
|
node _T_2870 = cat(_T_2869, _T_2862) @[el2_lib.scala 268:90]
|
|
node _T_2871 = xorr(_T_2870) @[el2_lib.scala 268:97]
|
|
node _T_2872 = cat(_T_2697[2], _T_2697[1]) @[el2_lib.scala 268:107]
|
|
node _T_2873 = cat(_T_2872, _T_2697[0]) @[el2_lib.scala 268:107]
|
|
node _T_2874 = cat(_T_2697[5], _T_2697[4]) @[el2_lib.scala 268:107]
|
|
node _T_2875 = cat(_T_2874, _T_2697[3]) @[el2_lib.scala 268:107]
|
|
node _T_2876 = cat(_T_2875, _T_2873) @[el2_lib.scala 268:107]
|
|
node _T_2877 = xorr(_T_2876) @[el2_lib.scala 268:114]
|
|
node _T_2878 = cat(_T_2856, _T_2871) @[Cat.scala 29:58]
|
|
node _T_2879 = cat(_T_2878, _T_2877) @[Cat.scala 29:58]
|
|
node _T_2880 = cat(_T_2805, _T_2823) @[Cat.scala 29:58]
|
|
node _T_2881 = cat(_T_2880, _T_2841) @[Cat.scala 29:58]
|
|
node _T_2882 = cat(_T_2881, _T_2879) @[Cat.scala 29:58]
|
|
node _T_2883 = xorr(_T_2691) @[el2_lib.scala 269:13]
|
|
node _T_2884 = xorr(_T_2882) @[el2_lib.scala 269:23]
|
|
node _T_2885 = xor(_T_2883, _T_2884) @[el2_lib.scala 269:18]
|
|
node _T_2886 = cat(_T_2885, _T_2882) @[Cat.scala 29:58]
|
|
node _T_2887 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 638:93]
|
|
wire _T_2888 : UInt<1>[18] @[el2_lib.scala 250:18]
|
|
wire _T_2889 : UInt<1>[18] @[el2_lib.scala 251:18]
|
|
wire _T_2890 : UInt<1>[18] @[el2_lib.scala 252:18]
|
|
wire _T_2891 : UInt<1>[15] @[el2_lib.scala 253:18]
|
|
wire _T_2892 : UInt<1>[15] @[el2_lib.scala 254:18]
|
|
wire _T_2893 : UInt<1>[6] @[el2_lib.scala 255:18]
|
|
node _T_2894 = bits(_T_2887, 0, 0) @[el2_lib.scala 262:36]
|
|
_T_2889[0] <= _T_2894 @[el2_lib.scala 262:30]
|
|
node _T_2895 = bits(_T_2887, 0, 0) @[el2_lib.scala 263:36]
|
|
_T_2890[0] <= _T_2895 @[el2_lib.scala 263:30]
|
|
node _T_2896 = bits(_T_2887, 0, 0) @[el2_lib.scala 266:36]
|
|
_T_2893[0] <= _T_2896 @[el2_lib.scala 266:30]
|
|
node _T_2897 = bits(_T_2887, 1, 1) @[el2_lib.scala 261:36]
|
|
_T_2888[0] <= _T_2897 @[el2_lib.scala 261:30]
|
|
node _T_2898 = bits(_T_2887, 1, 1) @[el2_lib.scala 263:36]
|
|
_T_2890[1] <= _T_2898 @[el2_lib.scala 263:30]
|
|
node _T_2899 = bits(_T_2887, 1, 1) @[el2_lib.scala 266:36]
|
|
_T_2893[1] <= _T_2899 @[el2_lib.scala 266:30]
|
|
node _T_2900 = bits(_T_2887, 2, 2) @[el2_lib.scala 263:36]
|
|
_T_2890[2] <= _T_2900 @[el2_lib.scala 263:30]
|
|
node _T_2901 = bits(_T_2887, 2, 2) @[el2_lib.scala 266:36]
|
|
_T_2893[2] <= _T_2901 @[el2_lib.scala 266:30]
|
|
node _T_2902 = bits(_T_2887, 3, 3) @[el2_lib.scala 261:36]
|
|
_T_2888[1] <= _T_2902 @[el2_lib.scala 261:30]
|
|
node _T_2903 = bits(_T_2887, 3, 3) @[el2_lib.scala 262:36]
|
|
_T_2889[1] <= _T_2903 @[el2_lib.scala 262:30]
|
|
node _T_2904 = bits(_T_2887, 3, 3) @[el2_lib.scala 266:36]
|
|
_T_2893[3] <= _T_2904 @[el2_lib.scala 266:30]
|
|
node _T_2905 = bits(_T_2887, 4, 4) @[el2_lib.scala 262:36]
|
|
_T_2889[2] <= _T_2905 @[el2_lib.scala 262:30]
|
|
node _T_2906 = bits(_T_2887, 4, 4) @[el2_lib.scala 266:36]
|
|
_T_2893[4] <= _T_2906 @[el2_lib.scala 266:30]
|
|
node _T_2907 = bits(_T_2887, 5, 5) @[el2_lib.scala 261:36]
|
|
_T_2888[2] <= _T_2907 @[el2_lib.scala 261:30]
|
|
node _T_2908 = bits(_T_2887, 5, 5) @[el2_lib.scala 266:36]
|
|
_T_2893[5] <= _T_2908 @[el2_lib.scala 266:30]
|
|
node _T_2909 = bits(_T_2887, 6, 6) @[el2_lib.scala 261:36]
|
|
_T_2888[3] <= _T_2909 @[el2_lib.scala 261:30]
|
|
node _T_2910 = bits(_T_2887, 6, 6) @[el2_lib.scala 262:36]
|
|
_T_2889[3] <= _T_2910 @[el2_lib.scala 262:30]
|
|
node _T_2911 = bits(_T_2887, 6, 6) @[el2_lib.scala 263:36]
|
|
_T_2890[3] <= _T_2911 @[el2_lib.scala 263:30]
|
|
node _T_2912 = bits(_T_2887, 6, 6) @[el2_lib.scala 264:36]
|
|
_T_2891[0] <= _T_2912 @[el2_lib.scala 264:30]
|
|
node _T_2913 = bits(_T_2887, 6, 6) @[el2_lib.scala 265:36]
|
|
_T_2892[0] <= _T_2913 @[el2_lib.scala 265:30]
|
|
node _T_2914 = bits(_T_2887, 7, 7) @[el2_lib.scala 262:36]
|
|
_T_2889[4] <= _T_2914 @[el2_lib.scala 262:30]
|
|
node _T_2915 = bits(_T_2887, 7, 7) @[el2_lib.scala 263:36]
|
|
_T_2890[4] <= _T_2915 @[el2_lib.scala 263:30]
|
|
node _T_2916 = bits(_T_2887, 7, 7) @[el2_lib.scala 264:36]
|
|
_T_2891[1] <= _T_2916 @[el2_lib.scala 264:30]
|
|
node _T_2917 = bits(_T_2887, 7, 7) @[el2_lib.scala 265:36]
|
|
_T_2892[1] <= _T_2917 @[el2_lib.scala 265:30]
|
|
node _T_2918 = bits(_T_2887, 8, 8) @[el2_lib.scala 261:36]
|
|
_T_2888[4] <= _T_2918 @[el2_lib.scala 261:30]
|
|
node _T_2919 = bits(_T_2887, 8, 8) @[el2_lib.scala 263:36]
|
|
_T_2890[5] <= _T_2919 @[el2_lib.scala 263:30]
|
|
node _T_2920 = bits(_T_2887, 8, 8) @[el2_lib.scala 264:36]
|
|
_T_2891[2] <= _T_2920 @[el2_lib.scala 264:30]
|
|
node _T_2921 = bits(_T_2887, 8, 8) @[el2_lib.scala 265:36]
|
|
_T_2892[2] <= _T_2921 @[el2_lib.scala 265:30]
|
|
node _T_2922 = bits(_T_2887, 9, 9) @[el2_lib.scala 263:36]
|
|
_T_2890[6] <= _T_2922 @[el2_lib.scala 263:30]
|
|
node _T_2923 = bits(_T_2887, 9, 9) @[el2_lib.scala 264:36]
|
|
_T_2891[3] <= _T_2923 @[el2_lib.scala 264:30]
|
|
node _T_2924 = bits(_T_2887, 9, 9) @[el2_lib.scala 265:36]
|
|
_T_2892[3] <= _T_2924 @[el2_lib.scala 265:30]
|
|
node _T_2925 = bits(_T_2887, 10, 10) @[el2_lib.scala 261:36]
|
|
_T_2888[5] <= _T_2925 @[el2_lib.scala 261:30]
|
|
node _T_2926 = bits(_T_2887, 10, 10) @[el2_lib.scala 262:36]
|
|
_T_2889[5] <= _T_2926 @[el2_lib.scala 262:30]
|
|
node _T_2927 = bits(_T_2887, 10, 10) @[el2_lib.scala 264:36]
|
|
_T_2891[4] <= _T_2927 @[el2_lib.scala 264:30]
|
|
node _T_2928 = bits(_T_2887, 10, 10) @[el2_lib.scala 265:36]
|
|
_T_2892[4] <= _T_2928 @[el2_lib.scala 265:30]
|
|
node _T_2929 = bits(_T_2887, 11, 11) @[el2_lib.scala 262:36]
|
|
_T_2889[6] <= _T_2929 @[el2_lib.scala 262:30]
|
|
node _T_2930 = bits(_T_2887, 11, 11) @[el2_lib.scala 264:36]
|
|
_T_2891[5] <= _T_2930 @[el2_lib.scala 264:30]
|
|
node _T_2931 = bits(_T_2887, 11, 11) @[el2_lib.scala 265:36]
|
|
_T_2892[5] <= _T_2931 @[el2_lib.scala 265:30]
|
|
node _T_2932 = bits(_T_2887, 12, 12) @[el2_lib.scala 261:36]
|
|
_T_2888[6] <= _T_2932 @[el2_lib.scala 261:30]
|
|
node _T_2933 = bits(_T_2887, 12, 12) @[el2_lib.scala 264:36]
|
|
_T_2891[6] <= _T_2933 @[el2_lib.scala 264:30]
|
|
node _T_2934 = bits(_T_2887, 12, 12) @[el2_lib.scala 265:36]
|
|
_T_2892[6] <= _T_2934 @[el2_lib.scala 265:30]
|
|
node _T_2935 = bits(_T_2887, 13, 13) @[el2_lib.scala 264:36]
|
|
_T_2891[7] <= _T_2935 @[el2_lib.scala 264:30]
|
|
node _T_2936 = bits(_T_2887, 13, 13) @[el2_lib.scala 265:36]
|
|
_T_2892[7] <= _T_2936 @[el2_lib.scala 265:30]
|
|
node _T_2937 = bits(_T_2887, 14, 14) @[el2_lib.scala 261:36]
|
|
_T_2888[7] <= _T_2937 @[el2_lib.scala 261:30]
|
|
node _T_2938 = bits(_T_2887, 14, 14) @[el2_lib.scala 262:36]
|
|
_T_2889[7] <= _T_2938 @[el2_lib.scala 262:30]
|
|
node _T_2939 = bits(_T_2887, 14, 14) @[el2_lib.scala 263:36]
|
|
_T_2890[7] <= _T_2939 @[el2_lib.scala 263:30]
|
|
node _T_2940 = bits(_T_2887, 14, 14) @[el2_lib.scala 265:36]
|
|
_T_2892[8] <= _T_2940 @[el2_lib.scala 265:30]
|
|
node _T_2941 = bits(_T_2887, 15, 15) @[el2_lib.scala 262:36]
|
|
_T_2889[8] <= _T_2941 @[el2_lib.scala 262:30]
|
|
node _T_2942 = bits(_T_2887, 15, 15) @[el2_lib.scala 263:36]
|
|
_T_2890[8] <= _T_2942 @[el2_lib.scala 263:30]
|
|
node _T_2943 = bits(_T_2887, 15, 15) @[el2_lib.scala 265:36]
|
|
_T_2892[9] <= _T_2943 @[el2_lib.scala 265:30]
|
|
node _T_2944 = bits(_T_2887, 16, 16) @[el2_lib.scala 261:36]
|
|
_T_2888[8] <= _T_2944 @[el2_lib.scala 261:30]
|
|
node _T_2945 = bits(_T_2887, 16, 16) @[el2_lib.scala 263:36]
|
|
_T_2890[9] <= _T_2945 @[el2_lib.scala 263:30]
|
|
node _T_2946 = bits(_T_2887, 16, 16) @[el2_lib.scala 265:36]
|
|
_T_2892[10] <= _T_2946 @[el2_lib.scala 265:30]
|
|
node _T_2947 = bits(_T_2887, 17, 17) @[el2_lib.scala 263:36]
|
|
_T_2890[10] <= _T_2947 @[el2_lib.scala 263:30]
|
|
node _T_2948 = bits(_T_2887, 17, 17) @[el2_lib.scala 265:36]
|
|
_T_2892[11] <= _T_2948 @[el2_lib.scala 265:30]
|
|
node _T_2949 = bits(_T_2887, 18, 18) @[el2_lib.scala 261:36]
|
|
_T_2888[9] <= _T_2949 @[el2_lib.scala 261:30]
|
|
node _T_2950 = bits(_T_2887, 18, 18) @[el2_lib.scala 262:36]
|
|
_T_2889[9] <= _T_2950 @[el2_lib.scala 262:30]
|
|
node _T_2951 = bits(_T_2887, 18, 18) @[el2_lib.scala 265:36]
|
|
_T_2892[12] <= _T_2951 @[el2_lib.scala 265:30]
|
|
node _T_2952 = bits(_T_2887, 19, 19) @[el2_lib.scala 262:36]
|
|
_T_2889[10] <= _T_2952 @[el2_lib.scala 262:30]
|
|
node _T_2953 = bits(_T_2887, 19, 19) @[el2_lib.scala 265:36]
|
|
_T_2892[13] <= _T_2953 @[el2_lib.scala 265:30]
|
|
node _T_2954 = bits(_T_2887, 20, 20) @[el2_lib.scala 261:36]
|
|
_T_2888[10] <= _T_2954 @[el2_lib.scala 261:30]
|
|
node _T_2955 = bits(_T_2887, 20, 20) @[el2_lib.scala 265:36]
|
|
_T_2892[14] <= _T_2955 @[el2_lib.scala 265:30]
|
|
node _T_2956 = bits(_T_2887, 21, 21) @[el2_lib.scala 261:36]
|
|
_T_2888[11] <= _T_2956 @[el2_lib.scala 261:30]
|
|
node _T_2957 = bits(_T_2887, 21, 21) @[el2_lib.scala 262:36]
|
|
_T_2889[11] <= _T_2957 @[el2_lib.scala 262:30]
|
|
node _T_2958 = bits(_T_2887, 21, 21) @[el2_lib.scala 263:36]
|
|
_T_2890[11] <= _T_2958 @[el2_lib.scala 263:30]
|
|
node _T_2959 = bits(_T_2887, 21, 21) @[el2_lib.scala 264:36]
|
|
_T_2891[8] <= _T_2959 @[el2_lib.scala 264:30]
|
|
node _T_2960 = bits(_T_2887, 22, 22) @[el2_lib.scala 262:36]
|
|
_T_2889[12] <= _T_2960 @[el2_lib.scala 262:30]
|
|
node _T_2961 = bits(_T_2887, 22, 22) @[el2_lib.scala 263:36]
|
|
_T_2890[12] <= _T_2961 @[el2_lib.scala 263:30]
|
|
node _T_2962 = bits(_T_2887, 22, 22) @[el2_lib.scala 264:36]
|
|
_T_2891[9] <= _T_2962 @[el2_lib.scala 264:30]
|
|
node _T_2963 = bits(_T_2887, 23, 23) @[el2_lib.scala 261:36]
|
|
_T_2888[12] <= _T_2963 @[el2_lib.scala 261:30]
|
|
node _T_2964 = bits(_T_2887, 23, 23) @[el2_lib.scala 263:36]
|
|
_T_2890[13] <= _T_2964 @[el2_lib.scala 263:30]
|
|
node _T_2965 = bits(_T_2887, 23, 23) @[el2_lib.scala 264:36]
|
|
_T_2891[10] <= _T_2965 @[el2_lib.scala 264:30]
|
|
node _T_2966 = bits(_T_2887, 24, 24) @[el2_lib.scala 263:36]
|
|
_T_2890[14] <= _T_2966 @[el2_lib.scala 263:30]
|
|
node _T_2967 = bits(_T_2887, 24, 24) @[el2_lib.scala 264:36]
|
|
_T_2891[11] <= _T_2967 @[el2_lib.scala 264:30]
|
|
node _T_2968 = bits(_T_2887, 25, 25) @[el2_lib.scala 261:36]
|
|
_T_2888[13] <= _T_2968 @[el2_lib.scala 261:30]
|
|
node _T_2969 = bits(_T_2887, 25, 25) @[el2_lib.scala 262:36]
|
|
_T_2889[13] <= _T_2969 @[el2_lib.scala 262:30]
|
|
node _T_2970 = bits(_T_2887, 25, 25) @[el2_lib.scala 264:36]
|
|
_T_2891[12] <= _T_2970 @[el2_lib.scala 264:30]
|
|
node _T_2971 = bits(_T_2887, 26, 26) @[el2_lib.scala 262:36]
|
|
_T_2889[14] <= _T_2971 @[el2_lib.scala 262:30]
|
|
node _T_2972 = bits(_T_2887, 26, 26) @[el2_lib.scala 264:36]
|
|
_T_2891[13] <= _T_2972 @[el2_lib.scala 264:30]
|
|
node _T_2973 = bits(_T_2887, 27, 27) @[el2_lib.scala 261:36]
|
|
_T_2888[14] <= _T_2973 @[el2_lib.scala 261:30]
|
|
node _T_2974 = bits(_T_2887, 27, 27) @[el2_lib.scala 264:36]
|
|
_T_2891[14] <= _T_2974 @[el2_lib.scala 264:30]
|
|
node _T_2975 = bits(_T_2887, 28, 28) @[el2_lib.scala 261:36]
|
|
_T_2888[15] <= _T_2975 @[el2_lib.scala 261:30]
|
|
node _T_2976 = bits(_T_2887, 28, 28) @[el2_lib.scala 262:36]
|
|
_T_2889[15] <= _T_2976 @[el2_lib.scala 262:30]
|
|
node _T_2977 = bits(_T_2887, 28, 28) @[el2_lib.scala 263:36]
|
|
_T_2890[15] <= _T_2977 @[el2_lib.scala 263:30]
|
|
node _T_2978 = bits(_T_2887, 29, 29) @[el2_lib.scala 262:36]
|
|
_T_2889[16] <= _T_2978 @[el2_lib.scala 262:30]
|
|
node _T_2979 = bits(_T_2887, 29, 29) @[el2_lib.scala 263:36]
|
|
_T_2890[16] <= _T_2979 @[el2_lib.scala 263:30]
|
|
node _T_2980 = bits(_T_2887, 30, 30) @[el2_lib.scala 261:36]
|
|
_T_2888[16] <= _T_2980 @[el2_lib.scala 261:30]
|
|
node _T_2981 = bits(_T_2887, 30, 30) @[el2_lib.scala 263:36]
|
|
_T_2890[17] <= _T_2981 @[el2_lib.scala 263:30]
|
|
node _T_2982 = bits(_T_2887, 31, 31) @[el2_lib.scala 261:36]
|
|
_T_2888[17] <= _T_2982 @[el2_lib.scala 261:30]
|
|
node _T_2983 = bits(_T_2887, 31, 31) @[el2_lib.scala 262:36]
|
|
_T_2889[17] <= _T_2983 @[el2_lib.scala 262:30]
|
|
node _T_2984 = cat(_T_2888[1], _T_2888[0]) @[el2_lib.scala 268:22]
|
|
node _T_2985 = cat(_T_2888[3], _T_2888[2]) @[el2_lib.scala 268:22]
|
|
node _T_2986 = cat(_T_2985, _T_2984) @[el2_lib.scala 268:22]
|
|
node _T_2987 = cat(_T_2888[5], _T_2888[4]) @[el2_lib.scala 268:22]
|
|
node _T_2988 = cat(_T_2888[8], _T_2888[7]) @[el2_lib.scala 268:22]
|
|
node _T_2989 = cat(_T_2988, _T_2888[6]) @[el2_lib.scala 268:22]
|
|
node _T_2990 = cat(_T_2989, _T_2987) @[el2_lib.scala 268:22]
|
|
node _T_2991 = cat(_T_2990, _T_2986) @[el2_lib.scala 268:22]
|
|
node _T_2992 = cat(_T_2888[10], _T_2888[9]) @[el2_lib.scala 268:22]
|
|
node _T_2993 = cat(_T_2888[12], _T_2888[11]) @[el2_lib.scala 268:22]
|
|
node _T_2994 = cat(_T_2993, _T_2992) @[el2_lib.scala 268:22]
|
|
node _T_2995 = cat(_T_2888[14], _T_2888[13]) @[el2_lib.scala 268:22]
|
|
node _T_2996 = cat(_T_2888[17], _T_2888[16]) @[el2_lib.scala 268:22]
|
|
node _T_2997 = cat(_T_2996, _T_2888[15]) @[el2_lib.scala 268:22]
|
|
node _T_2998 = cat(_T_2997, _T_2995) @[el2_lib.scala 268:22]
|
|
node _T_2999 = cat(_T_2998, _T_2994) @[el2_lib.scala 268:22]
|
|
node _T_3000 = cat(_T_2999, _T_2991) @[el2_lib.scala 268:22]
|
|
node _T_3001 = xorr(_T_3000) @[el2_lib.scala 268:29]
|
|
node _T_3002 = cat(_T_2889[1], _T_2889[0]) @[el2_lib.scala 268:39]
|
|
node _T_3003 = cat(_T_2889[3], _T_2889[2]) @[el2_lib.scala 268:39]
|
|
node _T_3004 = cat(_T_3003, _T_3002) @[el2_lib.scala 268:39]
|
|
node _T_3005 = cat(_T_2889[5], _T_2889[4]) @[el2_lib.scala 268:39]
|
|
node _T_3006 = cat(_T_2889[8], _T_2889[7]) @[el2_lib.scala 268:39]
|
|
node _T_3007 = cat(_T_3006, _T_2889[6]) @[el2_lib.scala 268:39]
|
|
node _T_3008 = cat(_T_3007, _T_3005) @[el2_lib.scala 268:39]
|
|
node _T_3009 = cat(_T_3008, _T_3004) @[el2_lib.scala 268:39]
|
|
node _T_3010 = cat(_T_2889[10], _T_2889[9]) @[el2_lib.scala 268:39]
|
|
node _T_3011 = cat(_T_2889[12], _T_2889[11]) @[el2_lib.scala 268:39]
|
|
node _T_3012 = cat(_T_3011, _T_3010) @[el2_lib.scala 268:39]
|
|
node _T_3013 = cat(_T_2889[14], _T_2889[13]) @[el2_lib.scala 268:39]
|
|
node _T_3014 = cat(_T_2889[17], _T_2889[16]) @[el2_lib.scala 268:39]
|
|
node _T_3015 = cat(_T_3014, _T_2889[15]) @[el2_lib.scala 268:39]
|
|
node _T_3016 = cat(_T_3015, _T_3013) @[el2_lib.scala 268:39]
|
|
node _T_3017 = cat(_T_3016, _T_3012) @[el2_lib.scala 268:39]
|
|
node _T_3018 = cat(_T_3017, _T_3009) @[el2_lib.scala 268:39]
|
|
node _T_3019 = xorr(_T_3018) @[el2_lib.scala 268:46]
|
|
node _T_3020 = cat(_T_2890[1], _T_2890[0]) @[el2_lib.scala 268:56]
|
|
node _T_3021 = cat(_T_2890[3], _T_2890[2]) @[el2_lib.scala 268:56]
|
|
node _T_3022 = cat(_T_3021, _T_3020) @[el2_lib.scala 268:56]
|
|
node _T_3023 = cat(_T_2890[5], _T_2890[4]) @[el2_lib.scala 268:56]
|
|
node _T_3024 = cat(_T_2890[8], _T_2890[7]) @[el2_lib.scala 268:56]
|
|
node _T_3025 = cat(_T_3024, _T_2890[6]) @[el2_lib.scala 268:56]
|
|
node _T_3026 = cat(_T_3025, _T_3023) @[el2_lib.scala 268:56]
|
|
node _T_3027 = cat(_T_3026, _T_3022) @[el2_lib.scala 268:56]
|
|
node _T_3028 = cat(_T_2890[10], _T_2890[9]) @[el2_lib.scala 268:56]
|
|
node _T_3029 = cat(_T_2890[12], _T_2890[11]) @[el2_lib.scala 268:56]
|
|
node _T_3030 = cat(_T_3029, _T_3028) @[el2_lib.scala 268:56]
|
|
node _T_3031 = cat(_T_2890[14], _T_2890[13]) @[el2_lib.scala 268:56]
|
|
node _T_3032 = cat(_T_2890[17], _T_2890[16]) @[el2_lib.scala 268:56]
|
|
node _T_3033 = cat(_T_3032, _T_2890[15]) @[el2_lib.scala 268:56]
|
|
node _T_3034 = cat(_T_3033, _T_3031) @[el2_lib.scala 268:56]
|
|
node _T_3035 = cat(_T_3034, _T_3030) @[el2_lib.scala 268:56]
|
|
node _T_3036 = cat(_T_3035, _T_3027) @[el2_lib.scala 268:56]
|
|
node _T_3037 = xorr(_T_3036) @[el2_lib.scala 268:63]
|
|
node _T_3038 = cat(_T_2891[2], _T_2891[1]) @[el2_lib.scala 268:73]
|
|
node _T_3039 = cat(_T_3038, _T_2891[0]) @[el2_lib.scala 268:73]
|
|
node _T_3040 = cat(_T_2891[4], _T_2891[3]) @[el2_lib.scala 268:73]
|
|
node _T_3041 = cat(_T_2891[6], _T_2891[5]) @[el2_lib.scala 268:73]
|
|
node _T_3042 = cat(_T_3041, _T_3040) @[el2_lib.scala 268:73]
|
|
node _T_3043 = cat(_T_3042, _T_3039) @[el2_lib.scala 268:73]
|
|
node _T_3044 = cat(_T_2891[8], _T_2891[7]) @[el2_lib.scala 268:73]
|
|
node _T_3045 = cat(_T_2891[10], _T_2891[9]) @[el2_lib.scala 268:73]
|
|
node _T_3046 = cat(_T_3045, _T_3044) @[el2_lib.scala 268:73]
|
|
node _T_3047 = cat(_T_2891[12], _T_2891[11]) @[el2_lib.scala 268:73]
|
|
node _T_3048 = cat(_T_2891[14], _T_2891[13]) @[el2_lib.scala 268:73]
|
|
node _T_3049 = cat(_T_3048, _T_3047) @[el2_lib.scala 268:73]
|
|
node _T_3050 = cat(_T_3049, _T_3046) @[el2_lib.scala 268:73]
|
|
node _T_3051 = cat(_T_3050, _T_3043) @[el2_lib.scala 268:73]
|
|
node _T_3052 = xorr(_T_3051) @[el2_lib.scala 268:80]
|
|
node _T_3053 = cat(_T_2892[2], _T_2892[1]) @[el2_lib.scala 268:90]
|
|
node _T_3054 = cat(_T_3053, _T_2892[0]) @[el2_lib.scala 268:90]
|
|
node _T_3055 = cat(_T_2892[4], _T_2892[3]) @[el2_lib.scala 268:90]
|
|
node _T_3056 = cat(_T_2892[6], _T_2892[5]) @[el2_lib.scala 268:90]
|
|
node _T_3057 = cat(_T_3056, _T_3055) @[el2_lib.scala 268:90]
|
|
node _T_3058 = cat(_T_3057, _T_3054) @[el2_lib.scala 268:90]
|
|
node _T_3059 = cat(_T_2892[8], _T_2892[7]) @[el2_lib.scala 268:90]
|
|
node _T_3060 = cat(_T_2892[10], _T_2892[9]) @[el2_lib.scala 268:90]
|
|
node _T_3061 = cat(_T_3060, _T_3059) @[el2_lib.scala 268:90]
|
|
node _T_3062 = cat(_T_2892[12], _T_2892[11]) @[el2_lib.scala 268:90]
|
|
node _T_3063 = cat(_T_2892[14], _T_2892[13]) @[el2_lib.scala 268:90]
|
|
node _T_3064 = cat(_T_3063, _T_3062) @[el2_lib.scala 268:90]
|
|
node _T_3065 = cat(_T_3064, _T_3061) @[el2_lib.scala 268:90]
|
|
node _T_3066 = cat(_T_3065, _T_3058) @[el2_lib.scala 268:90]
|
|
node _T_3067 = xorr(_T_3066) @[el2_lib.scala 268:97]
|
|
node _T_3068 = cat(_T_2893[2], _T_2893[1]) @[el2_lib.scala 268:107]
|
|
node _T_3069 = cat(_T_3068, _T_2893[0]) @[el2_lib.scala 268:107]
|
|
node _T_3070 = cat(_T_2893[5], _T_2893[4]) @[el2_lib.scala 268:107]
|
|
node _T_3071 = cat(_T_3070, _T_2893[3]) @[el2_lib.scala 268:107]
|
|
node _T_3072 = cat(_T_3071, _T_3069) @[el2_lib.scala 268:107]
|
|
node _T_3073 = xorr(_T_3072) @[el2_lib.scala 268:114]
|
|
node _T_3074 = cat(_T_3052, _T_3067) @[Cat.scala 29:58]
|
|
node _T_3075 = cat(_T_3074, _T_3073) @[Cat.scala 29:58]
|
|
node _T_3076 = cat(_T_3001, _T_3019) @[Cat.scala 29:58]
|
|
node _T_3077 = cat(_T_3076, _T_3037) @[Cat.scala 29:58]
|
|
node _T_3078 = cat(_T_3077, _T_3075) @[Cat.scala 29:58]
|
|
node _T_3079 = xorr(_T_2887) @[el2_lib.scala 269:13]
|
|
node _T_3080 = xorr(_T_3078) @[el2_lib.scala 269:23]
|
|
node _T_3081 = xor(_T_3079, _T_3080) @[el2_lib.scala 269:18]
|
|
node _T_3082 = cat(_T_3081, _T_3078) @[Cat.scala 29:58]
|
|
node dma_mem_ecc = cat(_T_2886, _T_3082) @[Cat.scala 29:58]
|
|
wire iccm_ecc_corr_data_ff : UInt<39>
|
|
iccm_ecc_corr_data_ff <= UInt<1>("h00")
|
|
node _T_3083 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 640:67]
|
|
node _T_3084 = eq(_T_3083, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 640:45]
|
|
node _T_3085 = and(iccm_correct_ecc, _T_3084) @[el2_ifu_mem_ctl.scala 640:43]
|
|
node _T_3086 = cat(iccm_ecc_corr_data_ff, iccm_ecc_corr_data_ff) @[Cat.scala 29:58]
|
|
node _T_3087 = bits(dma_mem_ecc, 13, 7) @[el2_ifu_mem_ctl.scala 641:20]
|
|
node _T_3088 = bits(io.dma_mem_wdata, 63, 32) @[el2_ifu_mem_ctl.scala 641:43]
|
|
node _T_3089 = bits(dma_mem_ecc, 6, 0) @[el2_ifu_mem_ctl.scala 641:63]
|
|
node _T_3090 = bits(io.dma_mem_wdata, 31, 0) @[el2_ifu_mem_ctl.scala 641:86]
|
|
node _T_3091 = cat(_T_3089, _T_3090) @[Cat.scala 29:58]
|
|
node _T_3092 = cat(_T_3087, _T_3088) @[Cat.scala 29:58]
|
|
node _T_3093 = cat(_T_3092, _T_3091) @[Cat.scala 29:58]
|
|
node _T_3094 = mux(_T_3085, _T_3086, _T_3093) @[el2_ifu_mem_ctl.scala 640:25]
|
|
io.iccm_wr_data <= _T_3094 @[el2_ifu_mem_ctl.scala 640:19]
|
|
wire iccm_corrected_data : UInt<32>[2] @[el2_ifu_mem_ctl.scala 642:33]
|
|
iccm_corrected_data[0] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 643:26]
|
|
iccm_corrected_data[1] <= UInt<1>("h00") @[el2_ifu_mem_ctl.scala 644:26]
|
|
wire dma_mem_addr_ff : UInt<2>
|
|
dma_mem_addr_ff <= UInt<1>("h00")
|
|
node _T_3095 = bits(dma_mem_addr_ff, 0, 0) @[el2_ifu_mem_ctl.scala 646:51]
|
|
node _T_3096 = bits(_T_3095, 0, 0) @[el2_ifu_mem_ctl.scala 646:55]
|
|
node iccm_dma_rdata_1_muxed = mux(_T_3096, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 646:35]
|
|
wire iccm_double_ecc_error : UInt<2>
|
|
iccm_double_ecc_error <= UInt<1>("h00")
|
|
node iccm_dma_ecc_error_in = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 648:53]
|
|
node _T_3097 = cat(io.dma_mem_addr, io.dma_mem_addr) @[Cat.scala 29:58]
|
|
node _T_3098 = cat(iccm_dma_rdata_1_muxed, iccm_corrected_data[0]) @[Cat.scala 29:58]
|
|
node iccm_dma_rdata_in = mux(iccm_dma_ecc_error_in, _T_3097, _T_3098) @[el2_ifu_mem_ctl.scala 649:30]
|
|
reg dma_mem_tag_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 650:54]
|
|
dma_mem_tag_ff <= io.dma_mem_tag @[el2_ifu_mem_ctl.scala 650:54]
|
|
reg iccm_dma_rtag : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 651:69]
|
|
iccm_dma_rtag <= dma_mem_tag_ff @[el2_ifu_mem_ctl.scala 651:69]
|
|
io.iccm_dma_rtag <= iccm_dma_rtag @[el2_ifu_mem_ctl.scala 652:20]
|
|
node _T_3099 = bits(io.dma_mem_addr, 3, 2) @[el2_ifu_mem_ctl.scala 654:69]
|
|
reg _T_3100 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 654:53]
|
|
_T_3100 <= _T_3099 @[el2_ifu_mem_ctl.scala 654:53]
|
|
dma_mem_addr_ff <= _T_3100 @[el2_ifu_mem_ctl.scala 654:19]
|
|
reg iccm_dma_rvalid_in : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 655:59]
|
|
iccm_dma_rvalid_in <= iccm_dma_rden @[el2_ifu_mem_ctl.scala 655:59]
|
|
reg iccm_dma_rvalid : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 656:71]
|
|
iccm_dma_rvalid <= iccm_dma_rvalid_in @[el2_ifu_mem_ctl.scala 656:71]
|
|
io.iccm_dma_rvalid <= iccm_dma_rvalid @[el2_ifu_mem_ctl.scala 657:22]
|
|
reg iccm_dma_ecc_error : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 658:74]
|
|
iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 658:74]
|
|
io.iccm_dma_ecc_error <= iccm_dma_ecc_error_in @[el2_ifu_mem_ctl.scala 659:25]
|
|
reg iccm_dma_rdata : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 660:70]
|
|
iccm_dma_rdata <= iccm_dma_rdata_in @[el2_ifu_mem_ctl.scala 660:70]
|
|
io.iccm_dma_rdata <= iccm_dma_rdata @[el2_ifu_mem_ctl.scala 661:21]
|
|
wire iccm_ecc_corr_index_ff : UInt<14>
|
|
iccm_ecc_corr_index_ff <= UInt<1>("h00")
|
|
node _T_3101 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 663:46]
|
|
node _T_3102 = eq(iccm_correct_ecc, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 663:67]
|
|
node _T_3103 = and(_T_3101, _T_3102) @[el2_ifu_mem_ctl.scala 663:65]
|
|
node _T_3104 = and(ifc_dma_access_q_ok, io.dma_iccm_req) @[el2_ifu_mem_ctl.scala 664:31]
|
|
node _T_3105 = eq(_T_3104, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 664:9]
|
|
node _T_3106 = and(_T_3105, iccm_correct_ecc) @[el2_ifu_mem_ctl.scala 664:50]
|
|
node _T_3107 = cat(iccm_ecc_corr_index_ff, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_3108 = bits(io.ifc_fetch_addr_bf, 15, 0) @[el2_ifu_mem_ctl.scala 664:124]
|
|
node _T_3109 = mux(_T_3106, _T_3107, _T_3108) @[el2_ifu_mem_ctl.scala 664:8]
|
|
node _T_3110 = mux(_T_3103, io.dma_mem_addr, _T_3109) @[el2_ifu_mem_ctl.scala 663:25]
|
|
io.iccm_rw_addr <= _T_3110 @[el2_ifu_mem_ctl.scala 663:19]
|
|
node ic_fetch_val_int_f = cat(UInt<2>("h00"), io.ic_fetch_val_f) @[Cat.scala 29:58]
|
|
node _T_3111 = bits(ifu_fetch_addr_int_f, 0, 0) @[el2_ifu_mem_ctl.scala 666:76]
|
|
node ic_fetch_val_shift_right = dshl(ic_fetch_val_int_f, _T_3111) @[el2_ifu_mem_ctl.scala 666:53]
|
|
node _T_3112 = bits(ic_fetch_val_shift_right, 1, 0) @[el2_ifu_mem_ctl.scala 669:75]
|
|
node _T_3113 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:93]
|
|
node _T_3114 = and(_T_3112, _T_3113) @[el2_ifu_mem_ctl.scala 669:91]
|
|
node _T_3115 = and(_T_3114, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 669:113]
|
|
node _T_3116 = or(_T_3115, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 669:130]
|
|
node _T_3117 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:154]
|
|
node _T_3118 = and(_T_3116, _T_3117) @[el2_ifu_mem_ctl.scala 669:152]
|
|
node _T_3119 = bits(ic_fetch_val_shift_right, 3, 2) @[el2_ifu_mem_ctl.scala 669:75]
|
|
node _T_3120 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:93]
|
|
node _T_3121 = and(_T_3119, _T_3120) @[el2_ifu_mem_ctl.scala 669:91]
|
|
node _T_3122 = and(_T_3121, fetch_req_iccm_f) @[el2_ifu_mem_ctl.scala 669:113]
|
|
node _T_3123 = or(_T_3122, iccm_dma_rvalid_in) @[el2_ifu_mem_ctl.scala 669:130]
|
|
node _T_3124 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 669:154]
|
|
node _T_3125 = and(_T_3123, _T_3124) @[el2_ifu_mem_ctl.scala 669:152]
|
|
node iccm_ecc_word_enable = cat(_T_3125, _T_3118) @[Cat.scala 29:58]
|
|
node _T_3126 = bits(iccm_ecc_word_enable, 0, 0) @[el2_ifu_mem_ctl.scala 670:73]
|
|
node _T_3127 = bits(io.iccm_rd_data_ecc, 31, 0) @[el2_ifu_mem_ctl.scala 670:93]
|
|
node _T_3128 = bits(io.iccm_rd_data_ecc, 38, 32) @[el2_ifu_mem_ctl.scala 670:128]
|
|
wire _T_3129 : UInt<1>[18] @[el2_lib.scala 281:18]
|
|
wire _T_3130 : UInt<1>[18] @[el2_lib.scala 282:18]
|
|
wire _T_3131 : UInt<1>[18] @[el2_lib.scala 283:18]
|
|
wire _T_3132 : UInt<1>[15] @[el2_lib.scala 284:18]
|
|
wire _T_3133 : UInt<1>[15] @[el2_lib.scala 285:18]
|
|
wire _T_3134 : UInt<1>[6] @[el2_lib.scala 286:18]
|
|
node _T_3135 = bits(_T_3127, 0, 0) @[el2_lib.scala 293:36]
|
|
_T_3129[0] <= _T_3135 @[el2_lib.scala 293:30]
|
|
node _T_3136 = bits(_T_3127, 0, 0) @[el2_lib.scala 294:36]
|
|
_T_3130[0] <= _T_3136 @[el2_lib.scala 294:30]
|
|
node _T_3137 = bits(_T_3127, 1, 1) @[el2_lib.scala 293:36]
|
|
_T_3129[1] <= _T_3137 @[el2_lib.scala 293:30]
|
|
node _T_3138 = bits(_T_3127, 1, 1) @[el2_lib.scala 295:36]
|
|
_T_3131[0] <= _T_3138 @[el2_lib.scala 295:30]
|
|
node _T_3139 = bits(_T_3127, 2, 2) @[el2_lib.scala 294:36]
|
|
_T_3130[1] <= _T_3139 @[el2_lib.scala 294:30]
|
|
node _T_3140 = bits(_T_3127, 2, 2) @[el2_lib.scala 295:36]
|
|
_T_3131[1] <= _T_3140 @[el2_lib.scala 295:30]
|
|
node _T_3141 = bits(_T_3127, 3, 3) @[el2_lib.scala 293:36]
|
|
_T_3129[2] <= _T_3141 @[el2_lib.scala 293:30]
|
|
node _T_3142 = bits(_T_3127, 3, 3) @[el2_lib.scala 294:36]
|
|
_T_3130[2] <= _T_3142 @[el2_lib.scala 294:30]
|
|
node _T_3143 = bits(_T_3127, 3, 3) @[el2_lib.scala 295:36]
|
|
_T_3131[2] <= _T_3143 @[el2_lib.scala 295:30]
|
|
node _T_3144 = bits(_T_3127, 4, 4) @[el2_lib.scala 293:36]
|
|
_T_3129[3] <= _T_3144 @[el2_lib.scala 293:30]
|
|
node _T_3145 = bits(_T_3127, 4, 4) @[el2_lib.scala 296:36]
|
|
_T_3132[0] <= _T_3145 @[el2_lib.scala 296:30]
|
|
node _T_3146 = bits(_T_3127, 5, 5) @[el2_lib.scala 294:36]
|
|
_T_3130[3] <= _T_3146 @[el2_lib.scala 294:30]
|
|
node _T_3147 = bits(_T_3127, 5, 5) @[el2_lib.scala 296:36]
|
|
_T_3132[1] <= _T_3147 @[el2_lib.scala 296:30]
|
|
node _T_3148 = bits(_T_3127, 6, 6) @[el2_lib.scala 293:36]
|
|
_T_3129[4] <= _T_3148 @[el2_lib.scala 293:30]
|
|
node _T_3149 = bits(_T_3127, 6, 6) @[el2_lib.scala 294:36]
|
|
_T_3130[4] <= _T_3149 @[el2_lib.scala 294:30]
|
|
node _T_3150 = bits(_T_3127, 6, 6) @[el2_lib.scala 296:36]
|
|
_T_3132[2] <= _T_3150 @[el2_lib.scala 296:30]
|
|
node _T_3151 = bits(_T_3127, 7, 7) @[el2_lib.scala 295:36]
|
|
_T_3131[3] <= _T_3151 @[el2_lib.scala 295:30]
|
|
node _T_3152 = bits(_T_3127, 7, 7) @[el2_lib.scala 296:36]
|
|
_T_3132[3] <= _T_3152 @[el2_lib.scala 296:30]
|
|
node _T_3153 = bits(_T_3127, 8, 8) @[el2_lib.scala 293:36]
|
|
_T_3129[5] <= _T_3153 @[el2_lib.scala 293:30]
|
|
node _T_3154 = bits(_T_3127, 8, 8) @[el2_lib.scala 295:36]
|
|
_T_3131[4] <= _T_3154 @[el2_lib.scala 295:30]
|
|
node _T_3155 = bits(_T_3127, 8, 8) @[el2_lib.scala 296:36]
|
|
_T_3132[4] <= _T_3155 @[el2_lib.scala 296:30]
|
|
node _T_3156 = bits(_T_3127, 9, 9) @[el2_lib.scala 294:36]
|
|
_T_3130[5] <= _T_3156 @[el2_lib.scala 294:30]
|
|
node _T_3157 = bits(_T_3127, 9, 9) @[el2_lib.scala 295:36]
|
|
_T_3131[5] <= _T_3157 @[el2_lib.scala 295:30]
|
|
node _T_3158 = bits(_T_3127, 9, 9) @[el2_lib.scala 296:36]
|
|
_T_3132[5] <= _T_3158 @[el2_lib.scala 296:30]
|
|
node _T_3159 = bits(_T_3127, 10, 10) @[el2_lib.scala 293:36]
|
|
_T_3129[6] <= _T_3159 @[el2_lib.scala 293:30]
|
|
node _T_3160 = bits(_T_3127, 10, 10) @[el2_lib.scala 294:36]
|
|
_T_3130[6] <= _T_3160 @[el2_lib.scala 294:30]
|
|
node _T_3161 = bits(_T_3127, 10, 10) @[el2_lib.scala 295:36]
|
|
_T_3131[6] <= _T_3161 @[el2_lib.scala 295:30]
|
|
node _T_3162 = bits(_T_3127, 10, 10) @[el2_lib.scala 296:36]
|
|
_T_3132[6] <= _T_3162 @[el2_lib.scala 296:30]
|
|
node _T_3163 = bits(_T_3127, 11, 11) @[el2_lib.scala 293:36]
|
|
_T_3129[7] <= _T_3163 @[el2_lib.scala 293:30]
|
|
node _T_3164 = bits(_T_3127, 11, 11) @[el2_lib.scala 297:36]
|
|
_T_3133[0] <= _T_3164 @[el2_lib.scala 297:30]
|
|
node _T_3165 = bits(_T_3127, 12, 12) @[el2_lib.scala 294:36]
|
|
_T_3130[7] <= _T_3165 @[el2_lib.scala 294:30]
|
|
node _T_3166 = bits(_T_3127, 12, 12) @[el2_lib.scala 297:36]
|
|
_T_3133[1] <= _T_3166 @[el2_lib.scala 297:30]
|
|
node _T_3167 = bits(_T_3127, 13, 13) @[el2_lib.scala 293:36]
|
|
_T_3129[8] <= _T_3167 @[el2_lib.scala 293:30]
|
|
node _T_3168 = bits(_T_3127, 13, 13) @[el2_lib.scala 294:36]
|
|
_T_3130[8] <= _T_3168 @[el2_lib.scala 294:30]
|
|
node _T_3169 = bits(_T_3127, 13, 13) @[el2_lib.scala 297:36]
|
|
_T_3133[2] <= _T_3169 @[el2_lib.scala 297:30]
|
|
node _T_3170 = bits(_T_3127, 14, 14) @[el2_lib.scala 295:36]
|
|
_T_3131[7] <= _T_3170 @[el2_lib.scala 295:30]
|
|
node _T_3171 = bits(_T_3127, 14, 14) @[el2_lib.scala 297:36]
|
|
_T_3133[3] <= _T_3171 @[el2_lib.scala 297:30]
|
|
node _T_3172 = bits(_T_3127, 15, 15) @[el2_lib.scala 293:36]
|
|
_T_3129[9] <= _T_3172 @[el2_lib.scala 293:30]
|
|
node _T_3173 = bits(_T_3127, 15, 15) @[el2_lib.scala 295:36]
|
|
_T_3131[8] <= _T_3173 @[el2_lib.scala 295:30]
|
|
node _T_3174 = bits(_T_3127, 15, 15) @[el2_lib.scala 297:36]
|
|
_T_3133[4] <= _T_3174 @[el2_lib.scala 297:30]
|
|
node _T_3175 = bits(_T_3127, 16, 16) @[el2_lib.scala 294:36]
|
|
_T_3130[9] <= _T_3175 @[el2_lib.scala 294:30]
|
|
node _T_3176 = bits(_T_3127, 16, 16) @[el2_lib.scala 295:36]
|
|
_T_3131[9] <= _T_3176 @[el2_lib.scala 295:30]
|
|
node _T_3177 = bits(_T_3127, 16, 16) @[el2_lib.scala 297:36]
|
|
_T_3133[5] <= _T_3177 @[el2_lib.scala 297:30]
|
|
node _T_3178 = bits(_T_3127, 17, 17) @[el2_lib.scala 293:36]
|
|
_T_3129[10] <= _T_3178 @[el2_lib.scala 293:30]
|
|
node _T_3179 = bits(_T_3127, 17, 17) @[el2_lib.scala 294:36]
|
|
_T_3130[10] <= _T_3179 @[el2_lib.scala 294:30]
|
|
node _T_3180 = bits(_T_3127, 17, 17) @[el2_lib.scala 295:36]
|
|
_T_3131[10] <= _T_3180 @[el2_lib.scala 295:30]
|
|
node _T_3181 = bits(_T_3127, 17, 17) @[el2_lib.scala 297:36]
|
|
_T_3133[6] <= _T_3181 @[el2_lib.scala 297:30]
|
|
node _T_3182 = bits(_T_3127, 18, 18) @[el2_lib.scala 296:36]
|
|
_T_3132[7] <= _T_3182 @[el2_lib.scala 296:30]
|
|
node _T_3183 = bits(_T_3127, 18, 18) @[el2_lib.scala 297:36]
|
|
_T_3133[7] <= _T_3183 @[el2_lib.scala 297:30]
|
|
node _T_3184 = bits(_T_3127, 19, 19) @[el2_lib.scala 293:36]
|
|
_T_3129[11] <= _T_3184 @[el2_lib.scala 293:30]
|
|
node _T_3185 = bits(_T_3127, 19, 19) @[el2_lib.scala 296:36]
|
|
_T_3132[8] <= _T_3185 @[el2_lib.scala 296:30]
|
|
node _T_3186 = bits(_T_3127, 19, 19) @[el2_lib.scala 297:36]
|
|
_T_3133[8] <= _T_3186 @[el2_lib.scala 297:30]
|
|
node _T_3187 = bits(_T_3127, 20, 20) @[el2_lib.scala 294:36]
|
|
_T_3130[11] <= _T_3187 @[el2_lib.scala 294:30]
|
|
node _T_3188 = bits(_T_3127, 20, 20) @[el2_lib.scala 296:36]
|
|
_T_3132[9] <= _T_3188 @[el2_lib.scala 296:30]
|
|
node _T_3189 = bits(_T_3127, 20, 20) @[el2_lib.scala 297:36]
|
|
_T_3133[9] <= _T_3189 @[el2_lib.scala 297:30]
|
|
node _T_3190 = bits(_T_3127, 21, 21) @[el2_lib.scala 293:36]
|
|
_T_3129[12] <= _T_3190 @[el2_lib.scala 293:30]
|
|
node _T_3191 = bits(_T_3127, 21, 21) @[el2_lib.scala 294:36]
|
|
_T_3130[12] <= _T_3191 @[el2_lib.scala 294:30]
|
|
node _T_3192 = bits(_T_3127, 21, 21) @[el2_lib.scala 296:36]
|
|
_T_3132[10] <= _T_3192 @[el2_lib.scala 296:30]
|
|
node _T_3193 = bits(_T_3127, 21, 21) @[el2_lib.scala 297:36]
|
|
_T_3133[10] <= _T_3193 @[el2_lib.scala 297:30]
|
|
node _T_3194 = bits(_T_3127, 22, 22) @[el2_lib.scala 295:36]
|
|
_T_3131[11] <= _T_3194 @[el2_lib.scala 295:30]
|
|
node _T_3195 = bits(_T_3127, 22, 22) @[el2_lib.scala 296:36]
|
|
_T_3132[11] <= _T_3195 @[el2_lib.scala 296:30]
|
|
node _T_3196 = bits(_T_3127, 22, 22) @[el2_lib.scala 297:36]
|
|
_T_3133[11] <= _T_3196 @[el2_lib.scala 297:30]
|
|
node _T_3197 = bits(_T_3127, 23, 23) @[el2_lib.scala 293:36]
|
|
_T_3129[13] <= _T_3197 @[el2_lib.scala 293:30]
|
|
node _T_3198 = bits(_T_3127, 23, 23) @[el2_lib.scala 295:36]
|
|
_T_3131[12] <= _T_3198 @[el2_lib.scala 295:30]
|
|
node _T_3199 = bits(_T_3127, 23, 23) @[el2_lib.scala 296:36]
|
|
_T_3132[12] <= _T_3199 @[el2_lib.scala 296:30]
|
|
node _T_3200 = bits(_T_3127, 23, 23) @[el2_lib.scala 297:36]
|
|
_T_3133[12] <= _T_3200 @[el2_lib.scala 297:30]
|
|
node _T_3201 = bits(_T_3127, 24, 24) @[el2_lib.scala 294:36]
|
|
_T_3130[13] <= _T_3201 @[el2_lib.scala 294:30]
|
|
node _T_3202 = bits(_T_3127, 24, 24) @[el2_lib.scala 295:36]
|
|
_T_3131[13] <= _T_3202 @[el2_lib.scala 295:30]
|
|
node _T_3203 = bits(_T_3127, 24, 24) @[el2_lib.scala 296:36]
|
|
_T_3132[13] <= _T_3203 @[el2_lib.scala 296:30]
|
|
node _T_3204 = bits(_T_3127, 24, 24) @[el2_lib.scala 297:36]
|
|
_T_3133[13] <= _T_3204 @[el2_lib.scala 297:30]
|
|
node _T_3205 = bits(_T_3127, 25, 25) @[el2_lib.scala 293:36]
|
|
_T_3129[14] <= _T_3205 @[el2_lib.scala 293:30]
|
|
node _T_3206 = bits(_T_3127, 25, 25) @[el2_lib.scala 294:36]
|
|
_T_3130[14] <= _T_3206 @[el2_lib.scala 294:30]
|
|
node _T_3207 = bits(_T_3127, 25, 25) @[el2_lib.scala 295:36]
|
|
_T_3131[14] <= _T_3207 @[el2_lib.scala 295:30]
|
|
node _T_3208 = bits(_T_3127, 25, 25) @[el2_lib.scala 296:36]
|
|
_T_3132[14] <= _T_3208 @[el2_lib.scala 296:30]
|
|
node _T_3209 = bits(_T_3127, 25, 25) @[el2_lib.scala 297:36]
|
|
_T_3133[14] <= _T_3209 @[el2_lib.scala 297:30]
|
|
node _T_3210 = bits(_T_3127, 26, 26) @[el2_lib.scala 293:36]
|
|
_T_3129[15] <= _T_3210 @[el2_lib.scala 293:30]
|
|
node _T_3211 = bits(_T_3127, 26, 26) @[el2_lib.scala 298:36]
|
|
_T_3134[0] <= _T_3211 @[el2_lib.scala 298:30]
|
|
node _T_3212 = bits(_T_3127, 27, 27) @[el2_lib.scala 294:36]
|
|
_T_3130[15] <= _T_3212 @[el2_lib.scala 294:30]
|
|
node _T_3213 = bits(_T_3127, 27, 27) @[el2_lib.scala 298:36]
|
|
_T_3134[1] <= _T_3213 @[el2_lib.scala 298:30]
|
|
node _T_3214 = bits(_T_3127, 28, 28) @[el2_lib.scala 293:36]
|
|
_T_3129[16] <= _T_3214 @[el2_lib.scala 293:30]
|
|
node _T_3215 = bits(_T_3127, 28, 28) @[el2_lib.scala 294:36]
|
|
_T_3130[16] <= _T_3215 @[el2_lib.scala 294:30]
|
|
node _T_3216 = bits(_T_3127, 28, 28) @[el2_lib.scala 298:36]
|
|
_T_3134[2] <= _T_3216 @[el2_lib.scala 298:30]
|
|
node _T_3217 = bits(_T_3127, 29, 29) @[el2_lib.scala 295:36]
|
|
_T_3131[15] <= _T_3217 @[el2_lib.scala 295:30]
|
|
node _T_3218 = bits(_T_3127, 29, 29) @[el2_lib.scala 298:36]
|
|
_T_3134[3] <= _T_3218 @[el2_lib.scala 298:30]
|
|
node _T_3219 = bits(_T_3127, 30, 30) @[el2_lib.scala 293:36]
|
|
_T_3129[17] <= _T_3219 @[el2_lib.scala 293:30]
|
|
node _T_3220 = bits(_T_3127, 30, 30) @[el2_lib.scala 295:36]
|
|
_T_3131[16] <= _T_3220 @[el2_lib.scala 295:30]
|
|
node _T_3221 = bits(_T_3127, 30, 30) @[el2_lib.scala 298:36]
|
|
_T_3134[4] <= _T_3221 @[el2_lib.scala 298:30]
|
|
node _T_3222 = bits(_T_3127, 31, 31) @[el2_lib.scala 294:36]
|
|
_T_3130[17] <= _T_3222 @[el2_lib.scala 294:30]
|
|
node _T_3223 = bits(_T_3127, 31, 31) @[el2_lib.scala 295:36]
|
|
_T_3131[17] <= _T_3223 @[el2_lib.scala 295:30]
|
|
node _T_3224 = bits(_T_3127, 31, 31) @[el2_lib.scala 298:36]
|
|
_T_3134[5] <= _T_3224 @[el2_lib.scala 298:30]
|
|
node _T_3225 = xorr(_T_3127) @[el2_lib.scala 301:30]
|
|
node _T_3226 = xorr(_T_3128) @[el2_lib.scala 301:44]
|
|
node _T_3227 = xor(_T_3225, _T_3226) @[el2_lib.scala 301:35]
|
|
node _T_3228 = not(UInt<1>("h00")) @[el2_lib.scala 301:52]
|
|
node _T_3229 = and(_T_3227, _T_3228) @[el2_lib.scala 301:50]
|
|
node _T_3230 = bits(_T_3128, 5, 5) @[el2_lib.scala 301:68]
|
|
node _T_3231 = cat(_T_3134[2], _T_3134[1]) @[el2_lib.scala 301:76]
|
|
node _T_3232 = cat(_T_3231, _T_3134[0]) @[el2_lib.scala 301:76]
|
|
node _T_3233 = cat(_T_3134[5], _T_3134[4]) @[el2_lib.scala 301:76]
|
|
node _T_3234 = cat(_T_3233, _T_3134[3]) @[el2_lib.scala 301:76]
|
|
node _T_3235 = cat(_T_3234, _T_3232) @[el2_lib.scala 301:76]
|
|
node _T_3236 = xorr(_T_3235) @[el2_lib.scala 301:83]
|
|
node _T_3237 = xor(_T_3230, _T_3236) @[el2_lib.scala 301:71]
|
|
node _T_3238 = bits(_T_3128, 4, 4) @[el2_lib.scala 301:95]
|
|
node _T_3239 = cat(_T_3133[2], _T_3133[1]) @[el2_lib.scala 301:103]
|
|
node _T_3240 = cat(_T_3239, _T_3133[0]) @[el2_lib.scala 301:103]
|
|
node _T_3241 = cat(_T_3133[4], _T_3133[3]) @[el2_lib.scala 301:103]
|
|
node _T_3242 = cat(_T_3133[6], _T_3133[5]) @[el2_lib.scala 301:103]
|
|
node _T_3243 = cat(_T_3242, _T_3241) @[el2_lib.scala 301:103]
|
|
node _T_3244 = cat(_T_3243, _T_3240) @[el2_lib.scala 301:103]
|
|
node _T_3245 = cat(_T_3133[8], _T_3133[7]) @[el2_lib.scala 301:103]
|
|
node _T_3246 = cat(_T_3133[10], _T_3133[9]) @[el2_lib.scala 301:103]
|
|
node _T_3247 = cat(_T_3246, _T_3245) @[el2_lib.scala 301:103]
|
|
node _T_3248 = cat(_T_3133[12], _T_3133[11]) @[el2_lib.scala 301:103]
|
|
node _T_3249 = cat(_T_3133[14], _T_3133[13]) @[el2_lib.scala 301:103]
|
|
node _T_3250 = cat(_T_3249, _T_3248) @[el2_lib.scala 301:103]
|
|
node _T_3251 = cat(_T_3250, _T_3247) @[el2_lib.scala 301:103]
|
|
node _T_3252 = cat(_T_3251, _T_3244) @[el2_lib.scala 301:103]
|
|
node _T_3253 = xorr(_T_3252) @[el2_lib.scala 301:110]
|
|
node _T_3254 = xor(_T_3238, _T_3253) @[el2_lib.scala 301:98]
|
|
node _T_3255 = bits(_T_3128, 3, 3) @[el2_lib.scala 301:122]
|
|
node _T_3256 = cat(_T_3132[2], _T_3132[1]) @[el2_lib.scala 301:130]
|
|
node _T_3257 = cat(_T_3256, _T_3132[0]) @[el2_lib.scala 301:130]
|
|
node _T_3258 = cat(_T_3132[4], _T_3132[3]) @[el2_lib.scala 301:130]
|
|
node _T_3259 = cat(_T_3132[6], _T_3132[5]) @[el2_lib.scala 301:130]
|
|
node _T_3260 = cat(_T_3259, _T_3258) @[el2_lib.scala 301:130]
|
|
node _T_3261 = cat(_T_3260, _T_3257) @[el2_lib.scala 301:130]
|
|
node _T_3262 = cat(_T_3132[8], _T_3132[7]) @[el2_lib.scala 301:130]
|
|
node _T_3263 = cat(_T_3132[10], _T_3132[9]) @[el2_lib.scala 301:130]
|
|
node _T_3264 = cat(_T_3263, _T_3262) @[el2_lib.scala 301:130]
|
|
node _T_3265 = cat(_T_3132[12], _T_3132[11]) @[el2_lib.scala 301:130]
|
|
node _T_3266 = cat(_T_3132[14], _T_3132[13]) @[el2_lib.scala 301:130]
|
|
node _T_3267 = cat(_T_3266, _T_3265) @[el2_lib.scala 301:130]
|
|
node _T_3268 = cat(_T_3267, _T_3264) @[el2_lib.scala 301:130]
|
|
node _T_3269 = cat(_T_3268, _T_3261) @[el2_lib.scala 301:130]
|
|
node _T_3270 = xorr(_T_3269) @[el2_lib.scala 301:137]
|
|
node _T_3271 = xor(_T_3255, _T_3270) @[el2_lib.scala 301:125]
|
|
node _T_3272 = bits(_T_3128, 2, 2) @[el2_lib.scala 301:149]
|
|
node _T_3273 = cat(_T_3131[1], _T_3131[0]) @[el2_lib.scala 301:157]
|
|
node _T_3274 = cat(_T_3131[3], _T_3131[2]) @[el2_lib.scala 301:157]
|
|
node _T_3275 = cat(_T_3274, _T_3273) @[el2_lib.scala 301:157]
|
|
node _T_3276 = cat(_T_3131[5], _T_3131[4]) @[el2_lib.scala 301:157]
|
|
node _T_3277 = cat(_T_3131[8], _T_3131[7]) @[el2_lib.scala 301:157]
|
|
node _T_3278 = cat(_T_3277, _T_3131[6]) @[el2_lib.scala 301:157]
|
|
node _T_3279 = cat(_T_3278, _T_3276) @[el2_lib.scala 301:157]
|
|
node _T_3280 = cat(_T_3279, _T_3275) @[el2_lib.scala 301:157]
|
|
node _T_3281 = cat(_T_3131[10], _T_3131[9]) @[el2_lib.scala 301:157]
|
|
node _T_3282 = cat(_T_3131[12], _T_3131[11]) @[el2_lib.scala 301:157]
|
|
node _T_3283 = cat(_T_3282, _T_3281) @[el2_lib.scala 301:157]
|
|
node _T_3284 = cat(_T_3131[14], _T_3131[13]) @[el2_lib.scala 301:157]
|
|
node _T_3285 = cat(_T_3131[17], _T_3131[16]) @[el2_lib.scala 301:157]
|
|
node _T_3286 = cat(_T_3285, _T_3131[15]) @[el2_lib.scala 301:157]
|
|
node _T_3287 = cat(_T_3286, _T_3284) @[el2_lib.scala 301:157]
|
|
node _T_3288 = cat(_T_3287, _T_3283) @[el2_lib.scala 301:157]
|
|
node _T_3289 = cat(_T_3288, _T_3280) @[el2_lib.scala 301:157]
|
|
node _T_3290 = xorr(_T_3289) @[el2_lib.scala 301:164]
|
|
node _T_3291 = xor(_T_3272, _T_3290) @[el2_lib.scala 301:152]
|
|
node _T_3292 = bits(_T_3128, 1, 1) @[el2_lib.scala 301:176]
|
|
node _T_3293 = cat(_T_3130[1], _T_3130[0]) @[el2_lib.scala 301:184]
|
|
node _T_3294 = cat(_T_3130[3], _T_3130[2]) @[el2_lib.scala 301:184]
|
|
node _T_3295 = cat(_T_3294, _T_3293) @[el2_lib.scala 301:184]
|
|
node _T_3296 = cat(_T_3130[5], _T_3130[4]) @[el2_lib.scala 301:184]
|
|
node _T_3297 = cat(_T_3130[8], _T_3130[7]) @[el2_lib.scala 301:184]
|
|
node _T_3298 = cat(_T_3297, _T_3130[6]) @[el2_lib.scala 301:184]
|
|
node _T_3299 = cat(_T_3298, _T_3296) @[el2_lib.scala 301:184]
|
|
node _T_3300 = cat(_T_3299, _T_3295) @[el2_lib.scala 301:184]
|
|
node _T_3301 = cat(_T_3130[10], _T_3130[9]) @[el2_lib.scala 301:184]
|
|
node _T_3302 = cat(_T_3130[12], _T_3130[11]) @[el2_lib.scala 301:184]
|
|
node _T_3303 = cat(_T_3302, _T_3301) @[el2_lib.scala 301:184]
|
|
node _T_3304 = cat(_T_3130[14], _T_3130[13]) @[el2_lib.scala 301:184]
|
|
node _T_3305 = cat(_T_3130[17], _T_3130[16]) @[el2_lib.scala 301:184]
|
|
node _T_3306 = cat(_T_3305, _T_3130[15]) @[el2_lib.scala 301:184]
|
|
node _T_3307 = cat(_T_3306, _T_3304) @[el2_lib.scala 301:184]
|
|
node _T_3308 = cat(_T_3307, _T_3303) @[el2_lib.scala 301:184]
|
|
node _T_3309 = cat(_T_3308, _T_3300) @[el2_lib.scala 301:184]
|
|
node _T_3310 = xorr(_T_3309) @[el2_lib.scala 301:191]
|
|
node _T_3311 = xor(_T_3292, _T_3310) @[el2_lib.scala 301:179]
|
|
node _T_3312 = bits(_T_3128, 0, 0) @[el2_lib.scala 301:203]
|
|
node _T_3313 = cat(_T_3129[1], _T_3129[0]) @[el2_lib.scala 301:211]
|
|
node _T_3314 = cat(_T_3129[3], _T_3129[2]) @[el2_lib.scala 301:211]
|
|
node _T_3315 = cat(_T_3314, _T_3313) @[el2_lib.scala 301:211]
|
|
node _T_3316 = cat(_T_3129[5], _T_3129[4]) @[el2_lib.scala 301:211]
|
|
node _T_3317 = cat(_T_3129[8], _T_3129[7]) @[el2_lib.scala 301:211]
|
|
node _T_3318 = cat(_T_3317, _T_3129[6]) @[el2_lib.scala 301:211]
|
|
node _T_3319 = cat(_T_3318, _T_3316) @[el2_lib.scala 301:211]
|
|
node _T_3320 = cat(_T_3319, _T_3315) @[el2_lib.scala 301:211]
|
|
node _T_3321 = cat(_T_3129[10], _T_3129[9]) @[el2_lib.scala 301:211]
|
|
node _T_3322 = cat(_T_3129[12], _T_3129[11]) @[el2_lib.scala 301:211]
|
|
node _T_3323 = cat(_T_3322, _T_3321) @[el2_lib.scala 301:211]
|
|
node _T_3324 = cat(_T_3129[14], _T_3129[13]) @[el2_lib.scala 301:211]
|
|
node _T_3325 = cat(_T_3129[17], _T_3129[16]) @[el2_lib.scala 301:211]
|
|
node _T_3326 = cat(_T_3325, _T_3129[15]) @[el2_lib.scala 301:211]
|
|
node _T_3327 = cat(_T_3326, _T_3324) @[el2_lib.scala 301:211]
|
|
node _T_3328 = cat(_T_3327, _T_3323) @[el2_lib.scala 301:211]
|
|
node _T_3329 = cat(_T_3328, _T_3320) @[el2_lib.scala 301:211]
|
|
node _T_3330 = xorr(_T_3329) @[el2_lib.scala 301:218]
|
|
node _T_3331 = xor(_T_3312, _T_3330) @[el2_lib.scala 301:206]
|
|
node _T_3332 = cat(_T_3291, _T_3311) @[Cat.scala 29:58]
|
|
node _T_3333 = cat(_T_3332, _T_3331) @[Cat.scala 29:58]
|
|
node _T_3334 = cat(_T_3254, _T_3271) @[Cat.scala 29:58]
|
|
node _T_3335 = cat(_T_3229, _T_3237) @[Cat.scala 29:58]
|
|
node _T_3336 = cat(_T_3335, _T_3334) @[Cat.scala 29:58]
|
|
node _T_3337 = cat(_T_3336, _T_3333) @[Cat.scala 29:58]
|
|
node _T_3338 = neq(_T_3337, UInt<1>("h00")) @[el2_lib.scala 302:44]
|
|
node _T_3339 = and(_T_3126, _T_3338) @[el2_lib.scala 302:32]
|
|
node _T_3340 = bits(_T_3337, 6, 6) @[el2_lib.scala 302:64]
|
|
node _T_3341 = and(_T_3339, _T_3340) @[el2_lib.scala 302:53]
|
|
node _T_3342 = neq(_T_3337, UInt<1>("h00")) @[el2_lib.scala 303:44]
|
|
node _T_3343 = and(_T_3126, _T_3342) @[el2_lib.scala 303:32]
|
|
node _T_3344 = bits(_T_3337, 6, 6) @[el2_lib.scala 303:65]
|
|
node _T_3345 = not(_T_3344) @[el2_lib.scala 303:55]
|
|
node _T_3346 = and(_T_3343, _T_3345) @[el2_lib.scala 303:53]
|
|
wire _T_3347 : UInt<1>[39] @[el2_lib.scala 304:26]
|
|
node _T_3348 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3349 = eq(_T_3348, UInt<1>("h01")) @[el2_lib.scala 307:41]
|
|
_T_3347[0] <= _T_3349 @[el2_lib.scala 307:23]
|
|
node _T_3350 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3351 = eq(_T_3350, UInt<2>("h02")) @[el2_lib.scala 307:41]
|
|
_T_3347[1] <= _T_3351 @[el2_lib.scala 307:23]
|
|
node _T_3352 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3353 = eq(_T_3352, UInt<2>("h03")) @[el2_lib.scala 307:41]
|
|
_T_3347[2] <= _T_3353 @[el2_lib.scala 307:23]
|
|
node _T_3354 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3355 = eq(_T_3354, UInt<3>("h04")) @[el2_lib.scala 307:41]
|
|
_T_3347[3] <= _T_3355 @[el2_lib.scala 307:23]
|
|
node _T_3356 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3357 = eq(_T_3356, UInt<3>("h05")) @[el2_lib.scala 307:41]
|
|
_T_3347[4] <= _T_3357 @[el2_lib.scala 307:23]
|
|
node _T_3358 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3359 = eq(_T_3358, UInt<3>("h06")) @[el2_lib.scala 307:41]
|
|
_T_3347[5] <= _T_3359 @[el2_lib.scala 307:23]
|
|
node _T_3360 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3361 = eq(_T_3360, UInt<3>("h07")) @[el2_lib.scala 307:41]
|
|
_T_3347[6] <= _T_3361 @[el2_lib.scala 307:23]
|
|
node _T_3362 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3363 = eq(_T_3362, UInt<4>("h08")) @[el2_lib.scala 307:41]
|
|
_T_3347[7] <= _T_3363 @[el2_lib.scala 307:23]
|
|
node _T_3364 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3365 = eq(_T_3364, UInt<4>("h09")) @[el2_lib.scala 307:41]
|
|
_T_3347[8] <= _T_3365 @[el2_lib.scala 307:23]
|
|
node _T_3366 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3367 = eq(_T_3366, UInt<4>("h0a")) @[el2_lib.scala 307:41]
|
|
_T_3347[9] <= _T_3367 @[el2_lib.scala 307:23]
|
|
node _T_3368 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3369 = eq(_T_3368, UInt<4>("h0b")) @[el2_lib.scala 307:41]
|
|
_T_3347[10] <= _T_3369 @[el2_lib.scala 307:23]
|
|
node _T_3370 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3371 = eq(_T_3370, UInt<4>("h0c")) @[el2_lib.scala 307:41]
|
|
_T_3347[11] <= _T_3371 @[el2_lib.scala 307:23]
|
|
node _T_3372 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3373 = eq(_T_3372, UInt<4>("h0d")) @[el2_lib.scala 307:41]
|
|
_T_3347[12] <= _T_3373 @[el2_lib.scala 307:23]
|
|
node _T_3374 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3375 = eq(_T_3374, UInt<4>("h0e")) @[el2_lib.scala 307:41]
|
|
_T_3347[13] <= _T_3375 @[el2_lib.scala 307:23]
|
|
node _T_3376 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3377 = eq(_T_3376, UInt<4>("h0f")) @[el2_lib.scala 307:41]
|
|
_T_3347[14] <= _T_3377 @[el2_lib.scala 307:23]
|
|
node _T_3378 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3379 = eq(_T_3378, UInt<5>("h010")) @[el2_lib.scala 307:41]
|
|
_T_3347[15] <= _T_3379 @[el2_lib.scala 307:23]
|
|
node _T_3380 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3381 = eq(_T_3380, UInt<5>("h011")) @[el2_lib.scala 307:41]
|
|
_T_3347[16] <= _T_3381 @[el2_lib.scala 307:23]
|
|
node _T_3382 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3383 = eq(_T_3382, UInt<5>("h012")) @[el2_lib.scala 307:41]
|
|
_T_3347[17] <= _T_3383 @[el2_lib.scala 307:23]
|
|
node _T_3384 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3385 = eq(_T_3384, UInt<5>("h013")) @[el2_lib.scala 307:41]
|
|
_T_3347[18] <= _T_3385 @[el2_lib.scala 307:23]
|
|
node _T_3386 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3387 = eq(_T_3386, UInt<5>("h014")) @[el2_lib.scala 307:41]
|
|
_T_3347[19] <= _T_3387 @[el2_lib.scala 307:23]
|
|
node _T_3388 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3389 = eq(_T_3388, UInt<5>("h015")) @[el2_lib.scala 307:41]
|
|
_T_3347[20] <= _T_3389 @[el2_lib.scala 307:23]
|
|
node _T_3390 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3391 = eq(_T_3390, UInt<5>("h016")) @[el2_lib.scala 307:41]
|
|
_T_3347[21] <= _T_3391 @[el2_lib.scala 307:23]
|
|
node _T_3392 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3393 = eq(_T_3392, UInt<5>("h017")) @[el2_lib.scala 307:41]
|
|
_T_3347[22] <= _T_3393 @[el2_lib.scala 307:23]
|
|
node _T_3394 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3395 = eq(_T_3394, UInt<5>("h018")) @[el2_lib.scala 307:41]
|
|
_T_3347[23] <= _T_3395 @[el2_lib.scala 307:23]
|
|
node _T_3396 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3397 = eq(_T_3396, UInt<5>("h019")) @[el2_lib.scala 307:41]
|
|
_T_3347[24] <= _T_3397 @[el2_lib.scala 307:23]
|
|
node _T_3398 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3399 = eq(_T_3398, UInt<5>("h01a")) @[el2_lib.scala 307:41]
|
|
_T_3347[25] <= _T_3399 @[el2_lib.scala 307:23]
|
|
node _T_3400 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3401 = eq(_T_3400, UInt<5>("h01b")) @[el2_lib.scala 307:41]
|
|
_T_3347[26] <= _T_3401 @[el2_lib.scala 307:23]
|
|
node _T_3402 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3403 = eq(_T_3402, UInt<5>("h01c")) @[el2_lib.scala 307:41]
|
|
_T_3347[27] <= _T_3403 @[el2_lib.scala 307:23]
|
|
node _T_3404 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3405 = eq(_T_3404, UInt<5>("h01d")) @[el2_lib.scala 307:41]
|
|
_T_3347[28] <= _T_3405 @[el2_lib.scala 307:23]
|
|
node _T_3406 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3407 = eq(_T_3406, UInt<5>("h01e")) @[el2_lib.scala 307:41]
|
|
_T_3347[29] <= _T_3407 @[el2_lib.scala 307:23]
|
|
node _T_3408 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3409 = eq(_T_3408, UInt<5>("h01f")) @[el2_lib.scala 307:41]
|
|
_T_3347[30] <= _T_3409 @[el2_lib.scala 307:23]
|
|
node _T_3410 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3411 = eq(_T_3410, UInt<6>("h020")) @[el2_lib.scala 307:41]
|
|
_T_3347[31] <= _T_3411 @[el2_lib.scala 307:23]
|
|
node _T_3412 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3413 = eq(_T_3412, UInt<6>("h021")) @[el2_lib.scala 307:41]
|
|
_T_3347[32] <= _T_3413 @[el2_lib.scala 307:23]
|
|
node _T_3414 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3415 = eq(_T_3414, UInt<6>("h022")) @[el2_lib.scala 307:41]
|
|
_T_3347[33] <= _T_3415 @[el2_lib.scala 307:23]
|
|
node _T_3416 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3417 = eq(_T_3416, UInt<6>("h023")) @[el2_lib.scala 307:41]
|
|
_T_3347[34] <= _T_3417 @[el2_lib.scala 307:23]
|
|
node _T_3418 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3419 = eq(_T_3418, UInt<6>("h024")) @[el2_lib.scala 307:41]
|
|
_T_3347[35] <= _T_3419 @[el2_lib.scala 307:23]
|
|
node _T_3420 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3421 = eq(_T_3420, UInt<6>("h025")) @[el2_lib.scala 307:41]
|
|
_T_3347[36] <= _T_3421 @[el2_lib.scala 307:23]
|
|
node _T_3422 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3423 = eq(_T_3422, UInt<6>("h026")) @[el2_lib.scala 307:41]
|
|
_T_3347[37] <= _T_3423 @[el2_lib.scala 307:23]
|
|
node _T_3424 = bits(_T_3337, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3425 = eq(_T_3424, UInt<6>("h027")) @[el2_lib.scala 307:41]
|
|
_T_3347[38] <= _T_3425 @[el2_lib.scala 307:23]
|
|
node _T_3426 = bits(_T_3128, 6, 6) @[el2_lib.scala 309:37]
|
|
node _T_3427 = bits(_T_3127, 31, 26) @[el2_lib.scala 309:45]
|
|
node _T_3428 = bits(_T_3128, 5, 5) @[el2_lib.scala 309:60]
|
|
node _T_3429 = bits(_T_3127, 25, 11) @[el2_lib.scala 309:68]
|
|
node _T_3430 = bits(_T_3128, 4, 4) @[el2_lib.scala 309:83]
|
|
node _T_3431 = bits(_T_3127, 10, 4) @[el2_lib.scala 309:91]
|
|
node _T_3432 = bits(_T_3128, 3, 3) @[el2_lib.scala 309:105]
|
|
node _T_3433 = bits(_T_3127, 3, 1) @[el2_lib.scala 309:113]
|
|
node _T_3434 = bits(_T_3128, 2, 2) @[el2_lib.scala 309:126]
|
|
node _T_3435 = bits(_T_3127, 0, 0) @[el2_lib.scala 309:134]
|
|
node _T_3436 = bits(_T_3128, 1, 0) @[el2_lib.scala 309:145]
|
|
node _T_3437 = cat(_T_3435, _T_3436) @[Cat.scala 29:58]
|
|
node _T_3438 = cat(_T_3432, _T_3433) @[Cat.scala 29:58]
|
|
node _T_3439 = cat(_T_3438, _T_3434) @[Cat.scala 29:58]
|
|
node _T_3440 = cat(_T_3439, _T_3437) @[Cat.scala 29:58]
|
|
node _T_3441 = cat(_T_3429, _T_3430) @[Cat.scala 29:58]
|
|
node _T_3442 = cat(_T_3441, _T_3431) @[Cat.scala 29:58]
|
|
node _T_3443 = cat(_T_3426, _T_3427) @[Cat.scala 29:58]
|
|
node _T_3444 = cat(_T_3443, _T_3428) @[Cat.scala 29:58]
|
|
node _T_3445 = cat(_T_3444, _T_3442) @[Cat.scala 29:58]
|
|
node _T_3446 = cat(_T_3445, _T_3440) @[Cat.scala 29:58]
|
|
node _T_3447 = bits(_T_3341, 0, 0) @[el2_lib.scala 310:49]
|
|
node _T_3448 = cat(_T_3347[1], _T_3347[0]) @[el2_lib.scala 310:69]
|
|
node _T_3449 = cat(_T_3347[3], _T_3347[2]) @[el2_lib.scala 310:69]
|
|
node _T_3450 = cat(_T_3449, _T_3448) @[el2_lib.scala 310:69]
|
|
node _T_3451 = cat(_T_3347[5], _T_3347[4]) @[el2_lib.scala 310:69]
|
|
node _T_3452 = cat(_T_3347[8], _T_3347[7]) @[el2_lib.scala 310:69]
|
|
node _T_3453 = cat(_T_3452, _T_3347[6]) @[el2_lib.scala 310:69]
|
|
node _T_3454 = cat(_T_3453, _T_3451) @[el2_lib.scala 310:69]
|
|
node _T_3455 = cat(_T_3454, _T_3450) @[el2_lib.scala 310:69]
|
|
node _T_3456 = cat(_T_3347[10], _T_3347[9]) @[el2_lib.scala 310:69]
|
|
node _T_3457 = cat(_T_3347[13], _T_3347[12]) @[el2_lib.scala 310:69]
|
|
node _T_3458 = cat(_T_3457, _T_3347[11]) @[el2_lib.scala 310:69]
|
|
node _T_3459 = cat(_T_3458, _T_3456) @[el2_lib.scala 310:69]
|
|
node _T_3460 = cat(_T_3347[15], _T_3347[14]) @[el2_lib.scala 310:69]
|
|
node _T_3461 = cat(_T_3347[18], _T_3347[17]) @[el2_lib.scala 310:69]
|
|
node _T_3462 = cat(_T_3461, _T_3347[16]) @[el2_lib.scala 310:69]
|
|
node _T_3463 = cat(_T_3462, _T_3460) @[el2_lib.scala 310:69]
|
|
node _T_3464 = cat(_T_3463, _T_3459) @[el2_lib.scala 310:69]
|
|
node _T_3465 = cat(_T_3464, _T_3455) @[el2_lib.scala 310:69]
|
|
node _T_3466 = cat(_T_3347[20], _T_3347[19]) @[el2_lib.scala 310:69]
|
|
node _T_3467 = cat(_T_3347[23], _T_3347[22]) @[el2_lib.scala 310:69]
|
|
node _T_3468 = cat(_T_3467, _T_3347[21]) @[el2_lib.scala 310:69]
|
|
node _T_3469 = cat(_T_3468, _T_3466) @[el2_lib.scala 310:69]
|
|
node _T_3470 = cat(_T_3347[25], _T_3347[24]) @[el2_lib.scala 310:69]
|
|
node _T_3471 = cat(_T_3347[28], _T_3347[27]) @[el2_lib.scala 310:69]
|
|
node _T_3472 = cat(_T_3471, _T_3347[26]) @[el2_lib.scala 310:69]
|
|
node _T_3473 = cat(_T_3472, _T_3470) @[el2_lib.scala 310:69]
|
|
node _T_3474 = cat(_T_3473, _T_3469) @[el2_lib.scala 310:69]
|
|
node _T_3475 = cat(_T_3347[30], _T_3347[29]) @[el2_lib.scala 310:69]
|
|
node _T_3476 = cat(_T_3347[33], _T_3347[32]) @[el2_lib.scala 310:69]
|
|
node _T_3477 = cat(_T_3476, _T_3347[31]) @[el2_lib.scala 310:69]
|
|
node _T_3478 = cat(_T_3477, _T_3475) @[el2_lib.scala 310:69]
|
|
node _T_3479 = cat(_T_3347[35], _T_3347[34]) @[el2_lib.scala 310:69]
|
|
node _T_3480 = cat(_T_3347[38], _T_3347[37]) @[el2_lib.scala 310:69]
|
|
node _T_3481 = cat(_T_3480, _T_3347[36]) @[el2_lib.scala 310:69]
|
|
node _T_3482 = cat(_T_3481, _T_3479) @[el2_lib.scala 310:69]
|
|
node _T_3483 = cat(_T_3482, _T_3478) @[el2_lib.scala 310:69]
|
|
node _T_3484 = cat(_T_3483, _T_3474) @[el2_lib.scala 310:69]
|
|
node _T_3485 = cat(_T_3484, _T_3465) @[el2_lib.scala 310:69]
|
|
node _T_3486 = xor(_T_3485, _T_3446) @[el2_lib.scala 310:76]
|
|
node _T_3487 = mux(_T_3447, _T_3486, _T_3446) @[el2_lib.scala 310:31]
|
|
node _T_3488 = bits(_T_3487, 37, 32) @[el2_lib.scala 312:37]
|
|
node _T_3489 = bits(_T_3487, 30, 16) @[el2_lib.scala 312:61]
|
|
node _T_3490 = bits(_T_3487, 14, 8) @[el2_lib.scala 312:86]
|
|
node _T_3491 = bits(_T_3487, 6, 4) @[el2_lib.scala 312:110]
|
|
node _T_3492 = bits(_T_3487, 2, 2) @[el2_lib.scala 312:133]
|
|
node _T_3493 = cat(_T_3491, _T_3492) @[Cat.scala 29:58]
|
|
node _T_3494 = cat(_T_3488, _T_3489) @[Cat.scala 29:58]
|
|
node _T_3495 = cat(_T_3494, _T_3490) @[Cat.scala 29:58]
|
|
node _T_3496 = cat(_T_3495, _T_3493) @[Cat.scala 29:58]
|
|
node _T_3497 = bits(_T_3487, 38, 38) @[el2_lib.scala 313:39]
|
|
node _T_3498 = bits(_T_3337, 6, 0) @[el2_lib.scala 313:56]
|
|
node _T_3499 = eq(_T_3498, UInt<7>("h040")) @[el2_lib.scala 313:62]
|
|
node _T_3500 = xor(_T_3497, _T_3499) @[el2_lib.scala 313:44]
|
|
node _T_3501 = bits(_T_3487, 31, 31) @[el2_lib.scala 313:102]
|
|
node _T_3502 = bits(_T_3487, 15, 15) @[el2_lib.scala 313:124]
|
|
node _T_3503 = bits(_T_3487, 7, 7) @[el2_lib.scala 313:146]
|
|
node _T_3504 = bits(_T_3487, 3, 3) @[el2_lib.scala 313:167]
|
|
node _T_3505 = bits(_T_3487, 1, 0) @[el2_lib.scala 313:188]
|
|
node _T_3506 = cat(_T_3503, _T_3504) @[Cat.scala 29:58]
|
|
node _T_3507 = cat(_T_3506, _T_3505) @[Cat.scala 29:58]
|
|
node _T_3508 = cat(_T_3500, _T_3501) @[Cat.scala 29:58]
|
|
node _T_3509 = cat(_T_3508, _T_3502) @[Cat.scala 29:58]
|
|
node _T_3510 = cat(_T_3509, _T_3507) @[Cat.scala 29:58]
|
|
node _T_3511 = bits(iccm_ecc_word_enable, 1, 1) @[el2_ifu_mem_ctl.scala 670:73]
|
|
node _T_3512 = bits(io.iccm_rd_data_ecc, 70, 39) @[el2_ifu_mem_ctl.scala 670:93]
|
|
node _T_3513 = bits(io.iccm_rd_data_ecc, 77, 71) @[el2_ifu_mem_ctl.scala 670:128]
|
|
wire _T_3514 : UInt<1>[18] @[el2_lib.scala 281:18]
|
|
wire _T_3515 : UInt<1>[18] @[el2_lib.scala 282:18]
|
|
wire _T_3516 : UInt<1>[18] @[el2_lib.scala 283:18]
|
|
wire _T_3517 : UInt<1>[15] @[el2_lib.scala 284:18]
|
|
wire _T_3518 : UInt<1>[15] @[el2_lib.scala 285:18]
|
|
wire _T_3519 : UInt<1>[6] @[el2_lib.scala 286:18]
|
|
node _T_3520 = bits(_T_3512, 0, 0) @[el2_lib.scala 293:36]
|
|
_T_3514[0] <= _T_3520 @[el2_lib.scala 293:30]
|
|
node _T_3521 = bits(_T_3512, 0, 0) @[el2_lib.scala 294:36]
|
|
_T_3515[0] <= _T_3521 @[el2_lib.scala 294:30]
|
|
node _T_3522 = bits(_T_3512, 1, 1) @[el2_lib.scala 293:36]
|
|
_T_3514[1] <= _T_3522 @[el2_lib.scala 293:30]
|
|
node _T_3523 = bits(_T_3512, 1, 1) @[el2_lib.scala 295:36]
|
|
_T_3516[0] <= _T_3523 @[el2_lib.scala 295:30]
|
|
node _T_3524 = bits(_T_3512, 2, 2) @[el2_lib.scala 294:36]
|
|
_T_3515[1] <= _T_3524 @[el2_lib.scala 294:30]
|
|
node _T_3525 = bits(_T_3512, 2, 2) @[el2_lib.scala 295:36]
|
|
_T_3516[1] <= _T_3525 @[el2_lib.scala 295:30]
|
|
node _T_3526 = bits(_T_3512, 3, 3) @[el2_lib.scala 293:36]
|
|
_T_3514[2] <= _T_3526 @[el2_lib.scala 293:30]
|
|
node _T_3527 = bits(_T_3512, 3, 3) @[el2_lib.scala 294:36]
|
|
_T_3515[2] <= _T_3527 @[el2_lib.scala 294:30]
|
|
node _T_3528 = bits(_T_3512, 3, 3) @[el2_lib.scala 295:36]
|
|
_T_3516[2] <= _T_3528 @[el2_lib.scala 295:30]
|
|
node _T_3529 = bits(_T_3512, 4, 4) @[el2_lib.scala 293:36]
|
|
_T_3514[3] <= _T_3529 @[el2_lib.scala 293:30]
|
|
node _T_3530 = bits(_T_3512, 4, 4) @[el2_lib.scala 296:36]
|
|
_T_3517[0] <= _T_3530 @[el2_lib.scala 296:30]
|
|
node _T_3531 = bits(_T_3512, 5, 5) @[el2_lib.scala 294:36]
|
|
_T_3515[3] <= _T_3531 @[el2_lib.scala 294:30]
|
|
node _T_3532 = bits(_T_3512, 5, 5) @[el2_lib.scala 296:36]
|
|
_T_3517[1] <= _T_3532 @[el2_lib.scala 296:30]
|
|
node _T_3533 = bits(_T_3512, 6, 6) @[el2_lib.scala 293:36]
|
|
_T_3514[4] <= _T_3533 @[el2_lib.scala 293:30]
|
|
node _T_3534 = bits(_T_3512, 6, 6) @[el2_lib.scala 294:36]
|
|
_T_3515[4] <= _T_3534 @[el2_lib.scala 294:30]
|
|
node _T_3535 = bits(_T_3512, 6, 6) @[el2_lib.scala 296:36]
|
|
_T_3517[2] <= _T_3535 @[el2_lib.scala 296:30]
|
|
node _T_3536 = bits(_T_3512, 7, 7) @[el2_lib.scala 295:36]
|
|
_T_3516[3] <= _T_3536 @[el2_lib.scala 295:30]
|
|
node _T_3537 = bits(_T_3512, 7, 7) @[el2_lib.scala 296:36]
|
|
_T_3517[3] <= _T_3537 @[el2_lib.scala 296:30]
|
|
node _T_3538 = bits(_T_3512, 8, 8) @[el2_lib.scala 293:36]
|
|
_T_3514[5] <= _T_3538 @[el2_lib.scala 293:30]
|
|
node _T_3539 = bits(_T_3512, 8, 8) @[el2_lib.scala 295:36]
|
|
_T_3516[4] <= _T_3539 @[el2_lib.scala 295:30]
|
|
node _T_3540 = bits(_T_3512, 8, 8) @[el2_lib.scala 296:36]
|
|
_T_3517[4] <= _T_3540 @[el2_lib.scala 296:30]
|
|
node _T_3541 = bits(_T_3512, 9, 9) @[el2_lib.scala 294:36]
|
|
_T_3515[5] <= _T_3541 @[el2_lib.scala 294:30]
|
|
node _T_3542 = bits(_T_3512, 9, 9) @[el2_lib.scala 295:36]
|
|
_T_3516[5] <= _T_3542 @[el2_lib.scala 295:30]
|
|
node _T_3543 = bits(_T_3512, 9, 9) @[el2_lib.scala 296:36]
|
|
_T_3517[5] <= _T_3543 @[el2_lib.scala 296:30]
|
|
node _T_3544 = bits(_T_3512, 10, 10) @[el2_lib.scala 293:36]
|
|
_T_3514[6] <= _T_3544 @[el2_lib.scala 293:30]
|
|
node _T_3545 = bits(_T_3512, 10, 10) @[el2_lib.scala 294:36]
|
|
_T_3515[6] <= _T_3545 @[el2_lib.scala 294:30]
|
|
node _T_3546 = bits(_T_3512, 10, 10) @[el2_lib.scala 295:36]
|
|
_T_3516[6] <= _T_3546 @[el2_lib.scala 295:30]
|
|
node _T_3547 = bits(_T_3512, 10, 10) @[el2_lib.scala 296:36]
|
|
_T_3517[6] <= _T_3547 @[el2_lib.scala 296:30]
|
|
node _T_3548 = bits(_T_3512, 11, 11) @[el2_lib.scala 293:36]
|
|
_T_3514[7] <= _T_3548 @[el2_lib.scala 293:30]
|
|
node _T_3549 = bits(_T_3512, 11, 11) @[el2_lib.scala 297:36]
|
|
_T_3518[0] <= _T_3549 @[el2_lib.scala 297:30]
|
|
node _T_3550 = bits(_T_3512, 12, 12) @[el2_lib.scala 294:36]
|
|
_T_3515[7] <= _T_3550 @[el2_lib.scala 294:30]
|
|
node _T_3551 = bits(_T_3512, 12, 12) @[el2_lib.scala 297:36]
|
|
_T_3518[1] <= _T_3551 @[el2_lib.scala 297:30]
|
|
node _T_3552 = bits(_T_3512, 13, 13) @[el2_lib.scala 293:36]
|
|
_T_3514[8] <= _T_3552 @[el2_lib.scala 293:30]
|
|
node _T_3553 = bits(_T_3512, 13, 13) @[el2_lib.scala 294:36]
|
|
_T_3515[8] <= _T_3553 @[el2_lib.scala 294:30]
|
|
node _T_3554 = bits(_T_3512, 13, 13) @[el2_lib.scala 297:36]
|
|
_T_3518[2] <= _T_3554 @[el2_lib.scala 297:30]
|
|
node _T_3555 = bits(_T_3512, 14, 14) @[el2_lib.scala 295:36]
|
|
_T_3516[7] <= _T_3555 @[el2_lib.scala 295:30]
|
|
node _T_3556 = bits(_T_3512, 14, 14) @[el2_lib.scala 297:36]
|
|
_T_3518[3] <= _T_3556 @[el2_lib.scala 297:30]
|
|
node _T_3557 = bits(_T_3512, 15, 15) @[el2_lib.scala 293:36]
|
|
_T_3514[9] <= _T_3557 @[el2_lib.scala 293:30]
|
|
node _T_3558 = bits(_T_3512, 15, 15) @[el2_lib.scala 295:36]
|
|
_T_3516[8] <= _T_3558 @[el2_lib.scala 295:30]
|
|
node _T_3559 = bits(_T_3512, 15, 15) @[el2_lib.scala 297:36]
|
|
_T_3518[4] <= _T_3559 @[el2_lib.scala 297:30]
|
|
node _T_3560 = bits(_T_3512, 16, 16) @[el2_lib.scala 294:36]
|
|
_T_3515[9] <= _T_3560 @[el2_lib.scala 294:30]
|
|
node _T_3561 = bits(_T_3512, 16, 16) @[el2_lib.scala 295:36]
|
|
_T_3516[9] <= _T_3561 @[el2_lib.scala 295:30]
|
|
node _T_3562 = bits(_T_3512, 16, 16) @[el2_lib.scala 297:36]
|
|
_T_3518[5] <= _T_3562 @[el2_lib.scala 297:30]
|
|
node _T_3563 = bits(_T_3512, 17, 17) @[el2_lib.scala 293:36]
|
|
_T_3514[10] <= _T_3563 @[el2_lib.scala 293:30]
|
|
node _T_3564 = bits(_T_3512, 17, 17) @[el2_lib.scala 294:36]
|
|
_T_3515[10] <= _T_3564 @[el2_lib.scala 294:30]
|
|
node _T_3565 = bits(_T_3512, 17, 17) @[el2_lib.scala 295:36]
|
|
_T_3516[10] <= _T_3565 @[el2_lib.scala 295:30]
|
|
node _T_3566 = bits(_T_3512, 17, 17) @[el2_lib.scala 297:36]
|
|
_T_3518[6] <= _T_3566 @[el2_lib.scala 297:30]
|
|
node _T_3567 = bits(_T_3512, 18, 18) @[el2_lib.scala 296:36]
|
|
_T_3517[7] <= _T_3567 @[el2_lib.scala 296:30]
|
|
node _T_3568 = bits(_T_3512, 18, 18) @[el2_lib.scala 297:36]
|
|
_T_3518[7] <= _T_3568 @[el2_lib.scala 297:30]
|
|
node _T_3569 = bits(_T_3512, 19, 19) @[el2_lib.scala 293:36]
|
|
_T_3514[11] <= _T_3569 @[el2_lib.scala 293:30]
|
|
node _T_3570 = bits(_T_3512, 19, 19) @[el2_lib.scala 296:36]
|
|
_T_3517[8] <= _T_3570 @[el2_lib.scala 296:30]
|
|
node _T_3571 = bits(_T_3512, 19, 19) @[el2_lib.scala 297:36]
|
|
_T_3518[8] <= _T_3571 @[el2_lib.scala 297:30]
|
|
node _T_3572 = bits(_T_3512, 20, 20) @[el2_lib.scala 294:36]
|
|
_T_3515[11] <= _T_3572 @[el2_lib.scala 294:30]
|
|
node _T_3573 = bits(_T_3512, 20, 20) @[el2_lib.scala 296:36]
|
|
_T_3517[9] <= _T_3573 @[el2_lib.scala 296:30]
|
|
node _T_3574 = bits(_T_3512, 20, 20) @[el2_lib.scala 297:36]
|
|
_T_3518[9] <= _T_3574 @[el2_lib.scala 297:30]
|
|
node _T_3575 = bits(_T_3512, 21, 21) @[el2_lib.scala 293:36]
|
|
_T_3514[12] <= _T_3575 @[el2_lib.scala 293:30]
|
|
node _T_3576 = bits(_T_3512, 21, 21) @[el2_lib.scala 294:36]
|
|
_T_3515[12] <= _T_3576 @[el2_lib.scala 294:30]
|
|
node _T_3577 = bits(_T_3512, 21, 21) @[el2_lib.scala 296:36]
|
|
_T_3517[10] <= _T_3577 @[el2_lib.scala 296:30]
|
|
node _T_3578 = bits(_T_3512, 21, 21) @[el2_lib.scala 297:36]
|
|
_T_3518[10] <= _T_3578 @[el2_lib.scala 297:30]
|
|
node _T_3579 = bits(_T_3512, 22, 22) @[el2_lib.scala 295:36]
|
|
_T_3516[11] <= _T_3579 @[el2_lib.scala 295:30]
|
|
node _T_3580 = bits(_T_3512, 22, 22) @[el2_lib.scala 296:36]
|
|
_T_3517[11] <= _T_3580 @[el2_lib.scala 296:30]
|
|
node _T_3581 = bits(_T_3512, 22, 22) @[el2_lib.scala 297:36]
|
|
_T_3518[11] <= _T_3581 @[el2_lib.scala 297:30]
|
|
node _T_3582 = bits(_T_3512, 23, 23) @[el2_lib.scala 293:36]
|
|
_T_3514[13] <= _T_3582 @[el2_lib.scala 293:30]
|
|
node _T_3583 = bits(_T_3512, 23, 23) @[el2_lib.scala 295:36]
|
|
_T_3516[12] <= _T_3583 @[el2_lib.scala 295:30]
|
|
node _T_3584 = bits(_T_3512, 23, 23) @[el2_lib.scala 296:36]
|
|
_T_3517[12] <= _T_3584 @[el2_lib.scala 296:30]
|
|
node _T_3585 = bits(_T_3512, 23, 23) @[el2_lib.scala 297:36]
|
|
_T_3518[12] <= _T_3585 @[el2_lib.scala 297:30]
|
|
node _T_3586 = bits(_T_3512, 24, 24) @[el2_lib.scala 294:36]
|
|
_T_3515[13] <= _T_3586 @[el2_lib.scala 294:30]
|
|
node _T_3587 = bits(_T_3512, 24, 24) @[el2_lib.scala 295:36]
|
|
_T_3516[13] <= _T_3587 @[el2_lib.scala 295:30]
|
|
node _T_3588 = bits(_T_3512, 24, 24) @[el2_lib.scala 296:36]
|
|
_T_3517[13] <= _T_3588 @[el2_lib.scala 296:30]
|
|
node _T_3589 = bits(_T_3512, 24, 24) @[el2_lib.scala 297:36]
|
|
_T_3518[13] <= _T_3589 @[el2_lib.scala 297:30]
|
|
node _T_3590 = bits(_T_3512, 25, 25) @[el2_lib.scala 293:36]
|
|
_T_3514[14] <= _T_3590 @[el2_lib.scala 293:30]
|
|
node _T_3591 = bits(_T_3512, 25, 25) @[el2_lib.scala 294:36]
|
|
_T_3515[14] <= _T_3591 @[el2_lib.scala 294:30]
|
|
node _T_3592 = bits(_T_3512, 25, 25) @[el2_lib.scala 295:36]
|
|
_T_3516[14] <= _T_3592 @[el2_lib.scala 295:30]
|
|
node _T_3593 = bits(_T_3512, 25, 25) @[el2_lib.scala 296:36]
|
|
_T_3517[14] <= _T_3593 @[el2_lib.scala 296:30]
|
|
node _T_3594 = bits(_T_3512, 25, 25) @[el2_lib.scala 297:36]
|
|
_T_3518[14] <= _T_3594 @[el2_lib.scala 297:30]
|
|
node _T_3595 = bits(_T_3512, 26, 26) @[el2_lib.scala 293:36]
|
|
_T_3514[15] <= _T_3595 @[el2_lib.scala 293:30]
|
|
node _T_3596 = bits(_T_3512, 26, 26) @[el2_lib.scala 298:36]
|
|
_T_3519[0] <= _T_3596 @[el2_lib.scala 298:30]
|
|
node _T_3597 = bits(_T_3512, 27, 27) @[el2_lib.scala 294:36]
|
|
_T_3515[15] <= _T_3597 @[el2_lib.scala 294:30]
|
|
node _T_3598 = bits(_T_3512, 27, 27) @[el2_lib.scala 298:36]
|
|
_T_3519[1] <= _T_3598 @[el2_lib.scala 298:30]
|
|
node _T_3599 = bits(_T_3512, 28, 28) @[el2_lib.scala 293:36]
|
|
_T_3514[16] <= _T_3599 @[el2_lib.scala 293:30]
|
|
node _T_3600 = bits(_T_3512, 28, 28) @[el2_lib.scala 294:36]
|
|
_T_3515[16] <= _T_3600 @[el2_lib.scala 294:30]
|
|
node _T_3601 = bits(_T_3512, 28, 28) @[el2_lib.scala 298:36]
|
|
_T_3519[2] <= _T_3601 @[el2_lib.scala 298:30]
|
|
node _T_3602 = bits(_T_3512, 29, 29) @[el2_lib.scala 295:36]
|
|
_T_3516[15] <= _T_3602 @[el2_lib.scala 295:30]
|
|
node _T_3603 = bits(_T_3512, 29, 29) @[el2_lib.scala 298:36]
|
|
_T_3519[3] <= _T_3603 @[el2_lib.scala 298:30]
|
|
node _T_3604 = bits(_T_3512, 30, 30) @[el2_lib.scala 293:36]
|
|
_T_3514[17] <= _T_3604 @[el2_lib.scala 293:30]
|
|
node _T_3605 = bits(_T_3512, 30, 30) @[el2_lib.scala 295:36]
|
|
_T_3516[16] <= _T_3605 @[el2_lib.scala 295:30]
|
|
node _T_3606 = bits(_T_3512, 30, 30) @[el2_lib.scala 298:36]
|
|
_T_3519[4] <= _T_3606 @[el2_lib.scala 298:30]
|
|
node _T_3607 = bits(_T_3512, 31, 31) @[el2_lib.scala 294:36]
|
|
_T_3515[17] <= _T_3607 @[el2_lib.scala 294:30]
|
|
node _T_3608 = bits(_T_3512, 31, 31) @[el2_lib.scala 295:36]
|
|
_T_3516[17] <= _T_3608 @[el2_lib.scala 295:30]
|
|
node _T_3609 = bits(_T_3512, 31, 31) @[el2_lib.scala 298:36]
|
|
_T_3519[5] <= _T_3609 @[el2_lib.scala 298:30]
|
|
node _T_3610 = xorr(_T_3512) @[el2_lib.scala 301:30]
|
|
node _T_3611 = xorr(_T_3513) @[el2_lib.scala 301:44]
|
|
node _T_3612 = xor(_T_3610, _T_3611) @[el2_lib.scala 301:35]
|
|
node _T_3613 = not(UInt<1>("h00")) @[el2_lib.scala 301:52]
|
|
node _T_3614 = and(_T_3612, _T_3613) @[el2_lib.scala 301:50]
|
|
node _T_3615 = bits(_T_3513, 5, 5) @[el2_lib.scala 301:68]
|
|
node _T_3616 = cat(_T_3519[2], _T_3519[1]) @[el2_lib.scala 301:76]
|
|
node _T_3617 = cat(_T_3616, _T_3519[0]) @[el2_lib.scala 301:76]
|
|
node _T_3618 = cat(_T_3519[5], _T_3519[4]) @[el2_lib.scala 301:76]
|
|
node _T_3619 = cat(_T_3618, _T_3519[3]) @[el2_lib.scala 301:76]
|
|
node _T_3620 = cat(_T_3619, _T_3617) @[el2_lib.scala 301:76]
|
|
node _T_3621 = xorr(_T_3620) @[el2_lib.scala 301:83]
|
|
node _T_3622 = xor(_T_3615, _T_3621) @[el2_lib.scala 301:71]
|
|
node _T_3623 = bits(_T_3513, 4, 4) @[el2_lib.scala 301:95]
|
|
node _T_3624 = cat(_T_3518[2], _T_3518[1]) @[el2_lib.scala 301:103]
|
|
node _T_3625 = cat(_T_3624, _T_3518[0]) @[el2_lib.scala 301:103]
|
|
node _T_3626 = cat(_T_3518[4], _T_3518[3]) @[el2_lib.scala 301:103]
|
|
node _T_3627 = cat(_T_3518[6], _T_3518[5]) @[el2_lib.scala 301:103]
|
|
node _T_3628 = cat(_T_3627, _T_3626) @[el2_lib.scala 301:103]
|
|
node _T_3629 = cat(_T_3628, _T_3625) @[el2_lib.scala 301:103]
|
|
node _T_3630 = cat(_T_3518[8], _T_3518[7]) @[el2_lib.scala 301:103]
|
|
node _T_3631 = cat(_T_3518[10], _T_3518[9]) @[el2_lib.scala 301:103]
|
|
node _T_3632 = cat(_T_3631, _T_3630) @[el2_lib.scala 301:103]
|
|
node _T_3633 = cat(_T_3518[12], _T_3518[11]) @[el2_lib.scala 301:103]
|
|
node _T_3634 = cat(_T_3518[14], _T_3518[13]) @[el2_lib.scala 301:103]
|
|
node _T_3635 = cat(_T_3634, _T_3633) @[el2_lib.scala 301:103]
|
|
node _T_3636 = cat(_T_3635, _T_3632) @[el2_lib.scala 301:103]
|
|
node _T_3637 = cat(_T_3636, _T_3629) @[el2_lib.scala 301:103]
|
|
node _T_3638 = xorr(_T_3637) @[el2_lib.scala 301:110]
|
|
node _T_3639 = xor(_T_3623, _T_3638) @[el2_lib.scala 301:98]
|
|
node _T_3640 = bits(_T_3513, 3, 3) @[el2_lib.scala 301:122]
|
|
node _T_3641 = cat(_T_3517[2], _T_3517[1]) @[el2_lib.scala 301:130]
|
|
node _T_3642 = cat(_T_3641, _T_3517[0]) @[el2_lib.scala 301:130]
|
|
node _T_3643 = cat(_T_3517[4], _T_3517[3]) @[el2_lib.scala 301:130]
|
|
node _T_3644 = cat(_T_3517[6], _T_3517[5]) @[el2_lib.scala 301:130]
|
|
node _T_3645 = cat(_T_3644, _T_3643) @[el2_lib.scala 301:130]
|
|
node _T_3646 = cat(_T_3645, _T_3642) @[el2_lib.scala 301:130]
|
|
node _T_3647 = cat(_T_3517[8], _T_3517[7]) @[el2_lib.scala 301:130]
|
|
node _T_3648 = cat(_T_3517[10], _T_3517[9]) @[el2_lib.scala 301:130]
|
|
node _T_3649 = cat(_T_3648, _T_3647) @[el2_lib.scala 301:130]
|
|
node _T_3650 = cat(_T_3517[12], _T_3517[11]) @[el2_lib.scala 301:130]
|
|
node _T_3651 = cat(_T_3517[14], _T_3517[13]) @[el2_lib.scala 301:130]
|
|
node _T_3652 = cat(_T_3651, _T_3650) @[el2_lib.scala 301:130]
|
|
node _T_3653 = cat(_T_3652, _T_3649) @[el2_lib.scala 301:130]
|
|
node _T_3654 = cat(_T_3653, _T_3646) @[el2_lib.scala 301:130]
|
|
node _T_3655 = xorr(_T_3654) @[el2_lib.scala 301:137]
|
|
node _T_3656 = xor(_T_3640, _T_3655) @[el2_lib.scala 301:125]
|
|
node _T_3657 = bits(_T_3513, 2, 2) @[el2_lib.scala 301:149]
|
|
node _T_3658 = cat(_T_3516[1], _T_3516[0]) @[el2_lib.scala 301:157]
|
|
node _T_3659 = cat(_T_3516[3], _T_3516[2]) @[el2_lib.scala 301:157]
|
|
node _T_3660 = cat(_T_3659, _T_3658) @[el2_lib.scala 301:157]
|
|
node _T_3661 = cat(_T_3516[5], _T_3516[4]) @[el2_lib.scala 301:157]
|
|
node _T_3662 = cat(_T_3516[8], _T_3516[7]) @[el2_lib.scala 301:157]
|
|
node _T_3663 = cat(_T_3662, _T_3516[6]) @[el2_lib.scala 301:157]
|
|
node _T_3664 = cat(_T_3663, _T_3661) @[el2_lib.scala 301:157]
|
|
node _T_3665 = cat(_T_3664, _T_3660) @[el2_lib.scala 301:157]
|
|
node _T_3666 = cat(_T_3516[10], _T_3516[9]) @[el2_lib.scala 301:157]
|
|
node _T_3667 = cat(_T_3516[12], _T_3516[11]) @[el2_lib.scala 301:157]
|
|
node _T_3668 = cat(_T_3667, _T_3666) @[el2_lib.scala 301:157]
|
|
node _T_3669 = cat(_T_3516[14], _T_3516[13]) @[el2_lib.scala 301:157]
|
|
node _T_3670 = cat(_T_3516[17], _T_3516[16]) @[el2_lib.scala 301:157]
|
|
node _T_3671 = cat(_T_3670, _T_3516[15]) @[el2_lib.scala 301:157]
|
|
node _T_3672 = cat(_T_3671, _T_3669) @[el2_lib.scala 301:157]
|
|
node _T_3673 = cat(_T_3672, _T_3668) @[el2_lib.scala 301:157]
|
|
node _T_3674 = cat(_T_3673, _T_3665) @[el2_lib.scala 301:157]
|
|
node _T_3675 = xorr(_T_3674) @[el2_lib.scala 301:164]
|
|
node _T_3676 = xor(_T_3657, _T_3675) @[el2_lib.scala 301:152]
|
|
node _T_3677 = bits(_T_3513, 1, 1) @[el2_lib.scala 301:176]
|
|
node _T_3678 = cat(_T_3515[1], _T_3515[0]) @[el2_lib.scala 301:184]
|
|
node _T_3679 = cat(_T_3515[3], _T_3515[2]) @[el2_lib.scala 301:184]
|
|
node _T_3680 = cat(_T_3679, _T_3678) @[el2_lib.scala 301:184]
|
|
node _T_3681 = cat(_T_3515[5], _T_3515[4]) @[el2_lib.scala 301:184]
|
|
node _T_3682 = cat(_T_3515[8], _T_3515[7]) @[el2_lib.scala 301:184]
|
|
node _T_3683 = cat(_T_3682, _T_3515[6]) @[el2_lib.scala 301:184]
|
|
node _T_3684 = cat(_T_3683, _T_3681) @[el2_lib.scala 301:184]
|
|
node _T_3685 = cat(_T_3684, _T_3680) @[el2_lib.scala 301:184]
|
|
node _T_3686 = cat(_T_3515[10], _T_3515[9]) @[el2_lib.scala 301:184]
|
|
node _T_3687 = cat(_T_3515[12], _T_3515[11]) @[el2_lib.scala 301:184]
|
|
node _T_3688 = cat(_T_3687, _T_3686) @[el2_lib.scala 301:184]
|
|
node _T_3689 = cat(_T_3515[14], _T_3515[13]) @[el2_lib.scala 301:184]
|
|
node _T_3690 = cat(_T_3515[17], _T_3515[16]) @[el2_lib.scala 301:184]
|
|
node _T_3691 = cat(_T_3690, _T_3515[15]) @[el2_lib.scala 301:184]
|
|
node _T_3692 = cat(_T_3691, _T_3689) @[el2_lib.scala 301:184]
|
|
node _T_3693 = cat(_T_3692, _T_3688) @[el2_lib.scala 301:184]
|
|
node _T_3694 = cat(_T_3693, _T_3685) @[el2_lib.scala 301:184]
|
|
node _T_3695 = xorr(_T_3694) @[el2_lib.scala 301:191]
|
|
node _T_3696 = xor(_T_3677, _T_3695) @[el2_lib.scala 301:179]
|
|
node _T_3697 = bits(_T_3513, 0, 0) @[el2_lib.scala 301:203]
|
|
node _T_3698 = cat(_T_3514[1], _T_3514[0]) @[el2_lib.scala 301:211]
|
|
node _T_3699 = cat(_T_3514[3], _T_3514[2]) @[el2_lib.scala 301:211]
|
|
node _T_3700 = cat(_T_3699, _T_3698) @[el2_lib.scala 301:211]
|
|
node _T_3701 = cat(_T_3514[5], _T_3514[4]) @[el2_lib.scala 301:211]
|
|
node _T_3702 = cat(_T_3514[8], _T_3514[7]) @[el2_lib.scala 301:211]
|
|
node _T_3703 = cat(_T_3702, _T_3514[6]) @[el2_lib.scala 301:211]
|
|
node _T_3704 = cat(_T_3703, _T_3701) @[el2_lib.scala 301:211]
|
|
node _T_3705 = cat(_T_3704, _T_3700) @[el2_lib.scala 301:211]
|
|
node _T_3706 = cat(_T_3514[10], _T_3514[9]) @[el2_lib.scala 301:211]
|
|
node _T_3707 = cat(_T_3514[12], _T_3514[11]) @[el2_lib.scala 301:211]
|
|
node _T_3708 = cat(_T_3707, _T_3706) @[el2_lib.scala 301:211]
|
|
node _T_3709 = cat(_T_3514[14], _T_3514[13]) @[el2_lib.scala 301:211]
|
|
node _T_3710 = cat(_T_3514[17], _T_3514[16]) @[el2_lib.scala 301:211]
|
|
node _T_3711 = cat(_T_3710, _T_3514[15]) @[el2_lib.scala 301:211]
|
|
node _T_3712 = cat(_T_3711, _T_3709) @[el2_lib.scala 301:211]
|
|
node _T_3713 = cat(_T_3712, _T_3708) @[el2_lib.scala 301:211]
|
|
node _T_3714 = cat(_T_3713, _T_3705) @[el2_lib.scala 301:211]
|
|
node _T_3715 = xorr(_T_3714) @[el2_lib.scala 301:218]
|
|
node _T_3716 = xor(_T_3697, _T_3715) @[el2_lib.scala 301:206]
|
|
node _T_3717 = cat(_T_3676, _T_3696) @[Cat.scala 29:58]
|
|
node _T_3718 = cat(_T_3717, _T_3716) @[Cat.scala 29:58]
|
|
node _T_3719 = cat(_T_3639, _T_3656) @[Cat.scala 29:58]
|
|
node _T_3720 = cat(_T_3614, _T_3622) @[Cat.scala 29:58]
|
|
node _T_3721 = cat(_T_3720, _T_3719) @[Cat.scala 29:58]
|
|
node _T_3722 = cat(_T_3721, _T_3718) @[Cat.scala 29:58]
|
|
node _T_3723 = neq(_T_3722, UInt<1>("h00")) @[el2_lib.scala 302:44]
|
|
node _T_3724 = and(_T_3511, _T_3723) @[el2_lib.scala 302:32]
|
|
node _T_3725 = bits(_T_3722, 6, 6) @[el2_lib.scala 302:64]
|
|
node _T_3726 = and(_T_3724, _T_3725) @[el2_lib.scala 302:53]
|
|
node _T_3727 = neq(_T_3722, UInt<1>("h00")) @[el2_lib.scala 303:44]
|
|
node _T_3728 = and(_T_3511, _T_3727) @[el2_lib.scala 303:32]
|
|
node _T_3729 = bits(_T_3722, 6, 6) @[el2_lib.scala 303:65]
|
|
node _T_3730 = not(_T_3729) @[el2_lib.scala 303:55]
|
|
node _T_3731 = and(_T_3728, _T_3730) @[el2_lib.scala 303:53]
|
|
wire _T_3732 : UInt<1>[39] @[el2_lib.scala 304:26]
|
|
node _T_3733 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3734 = eq(_T_3733, UInt<1>("h01")) @[el2_lib.scala 307:41]
|
|
_T_3732[0] <= _T_3734 @[el2_lib.scala 307:23]
|
|
node _T_3735 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3736 = eq(_T_3735, UInt<2>("h02")) @[el2_lib.scala 307:41]
|
|
_T_3732[1] <= _T_3736 @[el2_lib.scala 307:23]
|
|
node _T_3737 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3738 = eq(_T_3737, UInt<2>("h03")) @[el2_lib.scala 307:41]
|
|
_T_3732[2] <= _T_3738 @[el2_lib.scala 307:23]
|
|
node _T_3739 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3740 = eq(_T_3739, UInt<3>("h04")) @[el2_lib.scala 307:41]
|
|
_T_3732[3] <= _T_3740 @[el2_lib.scala 307:23]
|
|
node _T_3741 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3742 = eq(_T_3741, UInt<3>("h05")) @[el2_lib.scala 307:41]
|
|
_T_3732[4] <= _T_3742 @[el2_lib.scala 307:23]
|
|
node _T_3743 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3744 = eq(_T_3743, UInt<3>("h06")) @[el2_lib.scala 307:41]
|
|
_T_3732[5] <= _T_3744 @[el2_lib.scala 307:23]
|
|
node _T_3745 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3746 = eq(_T_3745, UInt<3>("h07")) @[el2_lib.scala 307:41]
|
|
_T_3732[6] <= _T_3746 @[el2_lib.scala 307:23]
|
|
node _T_3747 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3748 = eq(_T_3747, UInt<4>("h08")) @[el2_lib.scala 307:41]
|
|
_T_3732[7] <= _T_3748 @[el2_lib.scala 307:23]
|
|
node _T_3749 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3750 = eq(_T_3749, UInt<4>("h09")) @[el2_lib.scala 307:41]
|
|
_T_3732[8] <= _T_3750 @[el2_lib.scala 307:23]
|
|
node _T_3751 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3752 = eq(_T_3751, UInt<4>("h0a")) @[el2_lib.scala 307:41]
|
|
_T_3732[9] <= _T_3752 @[el2_lib.scala 307:23]
|
|
node _T_3753 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3754 = eq(_T_3753, UInt<4>("h0b")) @[el2_lib.scala 307:41]
|
|
_T_3732[10] <= _T_3754 @[el2_lib.scala 307:23]
|
|
node _T_3755 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3756 = eq(_T_3755, UInt<4>("h0c")) @[el2_lib.scala 307:41]
|
|
_T_3732[11] <= _T_3756 @[el2_lib.scala 307:23]
|
|
node _T_3757 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3758 = eq(_T_3757, UInt<4>("h0d")) @[el2_lib.scala 307:41]
|
|
_T_3732[12] <= _T_3758 @[el2_lib.scala 307:23]
|
|
node _T_3759 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3760 = eq(_T_3759, UInt<4>("h0e")) @[el2_lib.scala 307:41]
|
|
_T_3732[13] <= _T_3760 @[el2_lib.scala 307:23]
|
|
node _T_3761 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3762 = eq(_T_3761, UInt<4>("h0f")) @[el2_lib.scala 307:41]
|
|
_T_3732[14] <= _T_3762 @[el2_lib.scala 307:23]
|
|
node _T_3763 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3764 = eq(_T_3763, UInt<5>("h010")) @[el2_lib.scala 307:41]
|
|
_T_3732[15] <= _T_3764 @[el2_lib.scala 307:23]
|
|
node _T_3765 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3766 = eq(_T_3765, UInt<5>("h011")) @[el2_lib.scala 307:41]
|
|
_T_3732[16] <= _T_3766 @[el2_lib.scala 307:23]
|
|
node _T_3767 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3768 = eq(_T_3767, UInt<5>("h012")) @[el2_lib.scala 307:41]
|
|
_T_3732[17] <= _T_3768 @[el2_lib.scala 307:23]
|
|
node _T_3769 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3770 = eq(_T_3769, UInt<5>("h013")) @[el2_lib.scala 307:41]
|
|
_T_3732[18] <= _T_3770 @[el2_lib.scala 307:23]
|
|
node _T_3771 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3772 = eq(_T_3771, UInt<5>("h014")) @[el2_lib.scala 307:41]
|
|
_T_3732[19] <= _T_3772 @[el2_lib.scala 307:23]
|
|
node _T_3773 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3774 = eq(_T_3773, UInt<5>("h015")) @[el2_lib.scala 307:41]
|
|
_T_3732[20] <= _T_3774 @[el2_lib.scala 307:23]
|
|
node _T_3775 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3776 = eq(_T_3775, UInt<5>("h016")) @[el2_lib.scala 307:41]
|
|
_T_3732[21] <= _T_3776 @[el2_lib.scala 307:23]
|
|
node _T_3777 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3778 = eq(_T_3777, UInt<5>("h017")) @[el2_lib.scala 307:41]
|
|
_T_3732[22] <= _T_3778 @[el2_lib.scala 307:23]
|
|
node _T_3779 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3780 = eq(_T_3779, UInt<5>("h018")) @[el2_lib.scala 307:41]
|
|
_T_3732[23] <= _T_3780 @[el2_lib.scala 307:23]
|
|
node _T_3781 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3782 = eq(_T_3781, UInt<5>("h019")) @[el2_lib.scala 307:41]
|
|
_T_3732[24] <= _T_3782 @[el2_lib.scala 307:23]
|
|
node _T_3783 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3784 = eq(_T_3783, UInt<5>("h01a")) @[el2_lib.scala 307:41]
|
|
_T_3732[25] <= _T_3784 @[el2_lib.scala 307:23]
|
|
node _T_3785 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3786 = eq(_T_3785, UInt<5>("h01b")) @[el2_lib.scala 307:41]
|
|
_T_3732[26] <= _T_3786 @[el2_lib.scala 307:23]
|
|
node _T_3787 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3788 = eq(_T_3787, UInt<5>("h01c")) @[el2_lib.scala 307:41]
|
|
_T_3732[27] <= _T_3788 @[el2_lib.scala 307:23]
|
|
node _T_3789 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3790 = eq(_T_3789, UInt<5>("h01d")) @[el2_lib.scala 307:41]
|
|
_T_3732[28] <= _T_3790 @[el2_lib.scala 307:23]
|
|
node _T_3791 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3792 = eq(_T_3791, UInt<5>("h01e")) @[el2_lib.scala 307:41]
|
|
_T_3732[29] <= _T_3792 @[el2_lib.scala 307:23]
|
|
node _T_3793 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3794 = eq(_T_3793, UInt<5>("h01f")) @[el2_lib.scala 307:41]
|
|
_T_3732[30] <= _T_3794 @[el2_lib.scala 307:23]
|
|
node _T_3795 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3796 = eq(_T_3795, UInt<6>("h020")) @[el2_lib.scala 307:41]
|
|
_T_3732[31] <= _T_3796 @[el2_lib.scala 307:23]
|
|
node _T_3797 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3798 = eq(_T_3797, UInt<6>("h021")) @[el2_lib.scala 307:41]
|
|
_T_3732[32] <= _T_3798 @[el2_lib.scala 307:23]
|
|
node _T_3799 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3800 = eq(_T_3799, UInt<6>("h022")) @[el2_lib.scala 307:41]
|
|
_T_3732[33] <= _T_3800 @[el2_lib.scala 307:23]
|
|
node _T_3801 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3802 = eq(_T_3801, UInt<6>("h023")) @[el2_lib.scala 307:41]
|
|
_T_3732[34] <= _T_3802 @[el2_lib.scala 307:23]
|
|
node _T_3803 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3804 = eq(_T_3803, UInt<6>("h024")) @[el2_lib.scala 307:41]
|
|
_T_3732[35] <= _T_3804 @[el2_lib.scala 307:23]
|
|
node _T_3805 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3806 = eq(_T_3805, UInt<6>("h025")) @[el2_lib.scala 307:41]
|
|
_T_3732[36] <= _T_3806 @[el2_lib.scala 307:23]
|
|
node _T_3807 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3808 = eq(_T_3807, UInt<6>("h026")) @[el2_lib.scala 307:41]
|
|
_T_3732[37] <= _T_3808 @[el2_lib.scala 307:23]
|
|
node _T_3809 = bits(_T_3722, 5, 0) @[el2_lib.scala 307:35]
|
|
node _T_3810 = eq(_T_3809, UInt<6>("h027")) @[el2_lib.scala 307:41]
|
|
_T_3732[38] <= _T_3810 @[el2_lib.scala 307:23]
|
|
node _T_3811 = bits(_T_3513, 6, 6) @[el2_lib.scala 309:37]
|
|
node _T_3812 = bits(_T_3512, 31, 26) @[el2_lib.scala 309:45]
|
|
node _T_3813 = bits(_T_3513, 5, 5) @[el2_lib.scala 309:60]
|
|
node _T_3814 = bits(_T_3512, 25, 11) @[el2_lib.scala 309:68]
|
|
node _T_3815 = bits(_T_3513, 4, 4) @[el2_lib.scala 309:83]
|
|
node _T_3816 = bits(_T_3512, 10, 4) @[el2_lib.scala 309:91]
|
|
node _T_3817 = bits(_T_3513, 3, 3) @[el2_lib.scala 309:105]
|
|
node _T_3818 = bits(_T_3512, 3, 1) @[el2_lib.scala 309:113]
|
|
node _T_3819 = bits(_T_3513, 2, 2) @[el2_lib.scala 309:126]
|
|
node _T_3820 = bits(_T_3512, 0, 0) @[el2_lib.scala 309:134]
|
|
node _T_3821 = bits(_T_3513, 1, 0) @[el2_lib.scala 309:145]
|
|
node _T_3822 = cat(_T_3820, _T_3821) @[Cat.scala 29:58]
|
|
node _T_3823 = cat(_T_3817, _T_3818) @[Cat.scala 29:58]
|
|
node _T_3824 = cat(_T_3823, _T_3819) @[Cat.scala 29:58]
|
|
node _T_3825 = cat(_T_3824, _T_3822) @[Cat.scala 29:58]
|
|
node _T_3826 = cat(_T_3814, _T_3815) @[Cat.scala 29:58]
|
|
node _T_3827 = cat(_T_3826, _T_3816) @[Cat.scala 29:58]
|
|
node _T_3828 = cat(_T_3811, _T_3812) @[Cat.scala 29:58]
|
|
node _T_3829 = cat(_T_3828, _T_3813) @[Cat.scala 29:58]
|
|
node _T_3830 = cat(_T_3829, _T_3827) @[Cat.scala 29:58]
|
|
node _T_3831 = cat(_T_3830, _T_3825) @[Cat.scala 29:58]
|
|
node _T_3832 = bits(_T_3726, 0, 0) @[el2_lib.scala 310:49]
|
|
node _T_3833 = cat(_T_3732[1], _T_3732[0]) @[el2_lib.scala 310:69]
|
|
node _T_3834 = cat(_T_3732[3], _T_3732[2]) @[el2_lib.scala 310:69]
|
|
node _T_3835 = cat(_T_3834, _T_3833) @[el2_lib.scala 310:69]
|
|
node _T_3836 = cat(_T_3732[5], _T_3732[4]) @[el2_lib.scala 310:69]
|
|
node _T_3837 = cat(_T_3732[8], _T_3732[7]) @[el2_lib.scala 310:69]
|
|
node _T_3838 = cat(_T_3837, _T_3732[6]) @[el2_lib.scala 310:69]
|
|
node _T_3839 = cat(_T_3838, _T_3836) @[el2_lib.scala 310:69]
|
|
node _T_3840 = cat(_T_3839, _T_3835) @[el2_lib.scala 310:69]
|
|
node _T_3841 = cat(_T_3732[10], _T_3732[9]) @[el2_lib.scala 310:69]
|
|
node _T_3842 = cat(_T_3732[13], _T_3732[12]) @[el2_lib.scala 310:69]
|
|
node _T_3843 = cat(_T_3842, _T_3732[11]) @[el2_lib.scala 310:69]
|
|
node _T_3844 = cat(_T_3843, _T_3841) @[el2_lib.scala 310:69]
|
|
node _T_3845 = cat(_T_3732[15], _T_3732[14]) @[el2_lib.scala 310:69]
|
|
node _T_3846 = cat(_T_3732[18], _T_3732[17]) @[el2_lib.scala 310:69]
|
|
node _T_3847 = cat(_T_3846, _T_3732[16]) @[el2_lib.scala 310:69]
|
|
node _T_3848 = cat(_T_3847, _T_3845) @[el2_lib.scala 310:69]
|
|
node _T_3849 = cat(_T_3848, _T_3844) @[el2_lib.scala 310:69]
|
|
node _T_3850 = cat(_T_3849, _T_3840) @[el2_lib.scala 310:69]
|
|
node _T_3851 = cat(_T_3732[20], _T_3732[19]) @[el2_lib.scala 310:69]
|
|
node _T_3852 = cat(_T_3732[23], _T_3732[22]) @[el2_lib.scala 310:69]
|
|
node _T_3853 = cat(_T_3852, _T_3732[21]) @[el2_lib.scala 310:69]
|
|
node _T_3854 = cat(_T_3853, _T_3851) @[el2_lib.scala 310:69]
|
|
node _T_3855 = cat(_T_3732[25], _T_3732[24]) @[el2_lib.scala 310:69]
|
|
node _T_3856 = cat(_T_3732[28], _T_3732[27]) @[el2_lib.scala 310:69]
|
|
node _T_3857 = cat(_T_3856, _T_3732[26]) @[el2_lib.scala 310:69]
|
|
node _T_3858 = cat(_T_3857, _T_3855) @[el2_lib.scala 310:69]
|
|
node _T_3859 = cat(_T_3858, _T_3854) @[el2_lib.scala 310:69]
|
|
node _T_3860 = cat(_T_3732[30], _T_3732[29]) @[el2_lib.scala 310:69]
|
|
node _T_3861 = cat(_T_3732[33], _T_3732[32]) @[el2_lib.scala 310:69]
|
|
node _T_3862 = cat(_T_3861, _T_3732[31]) @[el2_lib.scala 310:69]
|
|
node _T_3863 = cat(_T_3862, _T_3860) @[el2_lib.scala 310:69]
|
|
node _T_3864 = cat(_T_3732[35], _T_3732[34]) @[el2_lib.scala 310:69]
|
|
node _T_3865 = cat(_T_3732[38], _T_3732[37]) @[el2_lib.scala 310:69]
|
|
node _T_3866 = cat(_T_3865, _T_3732[36]) @[el2_lib.scala 310:69]
|
|
node _T_3867 = cat(_T_3866, _T_3864) @[el2_lib.scala 310:69]
|
|
node _T_3868 = cat(_T_3867, _T_3863) @[el2_lib.scala 310:69]
|
|
node _T_3869 = cat(_T_3868, _T_3859) @[el2_lib.scala 310:69]
|
|
node _T_3870 = cat(_T_3869, _T_3850) @[el2_lib.scala 310:69]
|
|
node _T_3871 = xor(_T_3870, _T_3831) @[el2_lib.scala 310:76]
|
|
node _T_3872 = mux(_T_3832, _T_3871, _T_3831) @[el2_lib.scala 310:31]
|
|
node _T_3873 = bits(_T_3872, 37, 32) @[el2_lib.scala 312:37]
|
|
node _T_3874 = bits(_T_3872, 30, 16) @[el2_lib.scala 312:61]
|
|
node _T_3875 = bits(_T_3872, 14, 8) @[el2_lib.scala 312:86]
|
|
node _T_3876 = bits(_T_3872, 6, 4) @[el2_lib.scala 312:110]
|
|
node _T_3877 = bits(_T_3872, 2, 2) @[el2_lib.scala 312:133]
|
|
node _T_3878 = cat(_T_3876, _T_3877) @[Cat.scala 29:58]
|
|
node _T_3879 = cat(_T_3873, _T_3874) @[Cat.scala 29:58]
|
|
node _T_3880 = cat(_T_3879, _T_3875) @[Cat.scala 29:58]
|
|
node _T_3881 = cat(_T_3880, _T_3878) @[Cat.scala 29:58]
|
|
node _T_3882 = bits(_T_3872, 38, 38) @[el2_lib.scala 313:39]
|
|
node _T_3883 = bits(_T_3722, 6, 0) @[el2_lib.scala 313:56]
|
|
node _T_3884 = eq(_T_3883, UInt<7>("h040")) @[el2_lib.scala 313:62]
|
|
node _T_3885 = xor(_T_3882, _T_3884) @[el2_lib.scala 313:44]
|
|
node _T_3886 = bits(_T_3872, 31, 31) @[el2_lib.scala 313:102]
|
|
node _T_3887 = bits(_T_3872, 15, 15) @[el2_lib.scala 313:124]
|
|
node _T_3888 = bits(_T_3872, 7, 7) @[el2_lib.scala 313:146]
|
|
node _T_3889 = bits(_T_3872, 3, 3) @[el2_lib.scala 313:167]
|
|
node _T_3890 = bits(_T_3872, 1, 0) @[el2_lib.scala 313:188]
|
|
node _T_3891 = cat(_T_3888, _T_3889) @[Cat.scala 29:58]
|
|
node _T_3892 = cat(_T_3891, _T_3890) @[Cat.scala 29:58]
|
|
node _T_3893 = cat(_T_3885, _T_3886) @[Cat.scala 29:58]
|
|
node _T_3894 = cat(_T_3893, _T_3887) @[Cat.scala 29:58]
|
|
node _T_3895 = cat(_T_3894, _T_3892) @[Cat.scala 29:58]
|
|
wire iccm_corrected_ecc : UInt<7>[2] @[el2_ifu_mem_ctl.scala 671:32]
|
|
wire _T_3896 : UInt<7>[2] @[el2_ifu_mem_ctl.scala 672:32]
|
|
_T_3896[0] <= _T_3510 @[el2_ifu_mem_ctl.scala 672:32]
|
|
_T_3896[1] <= _T_3895 @[el2_ifu_mem_ctl.scala 672:32]
|
|
iccm_corrected_ecc[0] <= _T_3896[0] @[el2_ifu_mem_ctl.scala 672:22]
|
|
iccm_corrected_ecc[1] <= _T_3896[1] @[el2_ifu_mem_ctl.scala 672:22]
|
|
wire _T_3897 : UInt<32>[2] @[el2_ifu_mem_ctl.scala 673:33]
|
|
_T_3897[0] <= _T_3496 @[el2_ifu_mem_ctl.scala 673:33]
|
|
_T_3897[1] <= _T_3881 @[el2_ifu_mem_ctl.scala 673:33]
|
|
iccm_corrected_data[0] <= _T_3897[0] @[el2_ifu_mem_ctl.scala 673:23]
|
|
iccm_corrected_data[1] <= _T_3897[1] @[el2_ifu_mem_ctl.scala 673:23]
|
|
node _T_3898 = cat(_T_3341, _T_3726) @[Cat.scala 29:58]
|
|
iccm_single_ecc_error <= _T_3898 @[el2_ifu_mem_ctl.scala 674:25]
|
|
node _T_3899 = cat(_T_3346, _T_3731) @[Cat.scala 29:58]
|
|
iccm_double_ecc_error <= _T_3899 @[el2_ifu_mem_ctl.scala 675:25]
|
|
node _T_3900 = orr(iccm_single_ecc_error) @[el2_ifu_mem_ctl.scala 676:54]
|
|
node _T_3901 = and(_T_3900, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 676:58]
|
|
node _T_3902 = and(_T_3901, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 676:78]
|
|
io.iccm_rd_ecc_single_err <= _T_3902 @[el2_ifu_mem_ctl.scala 676:29]
|
|
node _T_3903 = orr(iccm_double_ecc_error) @[el2_ifu_mem_ctl.scala 677:54]
|
|
node _T_3904 = and(_T_3903, ifc_iccm_access_f) @[el2_ifu_mem_ctl.scala 677:58]
|
|
io.iccm_rd_ecc_double_err <= _T_3904 @[el2_ifu_mem_ctl.scala 677:29]
|
|
node _T_3905 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 678:60]
|
|
node _T_3906 = bits(_T_3905, 0, 0) @[el2_ifu_mem_ctl.scala 678:64]
|
|
node iccm_corrected_data_f_mux = mux(_T_3906, iccm_corrected_data[0], iccm_corrected_data[1]) @[el2_ifu_mem_ctl.scala 678:38]
|
|
node _T_3907 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 679:59]
|
|
node _T_3908 = bits(_T_3907, 0, 0) @[el2_ifu_mem_ctl.scala 679:63]
|
|
node iccm_corrected_ecc_f_mux = mux(_T_3908, iccm_corrected_ecc[0], iccm_corrected_ecc[1]) @[el2_ifu_mem_ctl.scala 679:37]
|
|
wire iccm_rd_ecc_single_err_ff : UInt<1>
|
|
iccm_rd_ecc_single_err_ff <= UInt<1>("h00")
|
|
node _T_3909 = eq(iccm_rd_ecc_single_err_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 681:76]
|
|
node _T_3910 = and(io.iccm_rd_ecc_single_err, _T_3909) @[el2_ifu_mem_ctl.scala 681:74]
|
|
node _T_3911 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 681:106]
|
|
node _T_3912 = and(_T_3910, _T_3911) @[el2_ifu_mem_ctl.scala 681:104]
|
|
node iccm_ecc_write_status = or(_T_3912, io.iccm_dma_sb_error) @[el2_ifu_mem_ctl.scala 681:127]
|
|
node _T_3913 = or(io.iccm_rd_ecc_single_err, iccm_rd_ecc_single_err_ff) @[el2_ifu_mem_ctl.scala 682:67]
|
|
node _T_3914 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 682:98]
|
|
node iccm_rd_ecc_single_err_hold_in = and(_T_3913, _T_3914) @[el2_ifu_mem_ctl.scala 682:96]
|
|
iccm_error_start <= io.iccm_rd_ecc_single_err @[el2_ifu_mem_ctl.scala 683:20]
|
|
wire iccm_rw_addr_f : UInt<14>
|
|
iccm_rw_addr_f <= UInt<1>("h00")
|
|
node _T_3915 = bits(iccm_single_ecc_error, 0, 0) @[el2_ifu_mem_ctl.scala 685:57]
|
|
node _T_3916 = bits(_T_3915, 0, 0) @[el2_ifu_mem_ctl.scala 685:67]
|
|
node _T_3917 = add(iccm_rw_addr_f, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 685:102]
|
|
node _T_3918 = tail(_T_3917, 1) @[el2_ifu_mem_ctl.scala 685:102]
|
|
node iccm_ecc_corr_index_in = mux(_T_3916, iccm_rw_addr_f, _T_3918) @[el2_ifu_mem_ctl.scala 685:35]
|
|
node _T_3919 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_mem_ctl.scala 686:67]
|
|
reg _T_3920 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 686:51]
|
|
_T_3920 <= _T_3919 @[el2_ifu_mem_ctl.scala 686:51]
|
|
iccm_rw_addr_f <= _T_3920 @[el2_ifu_mem_ctl.scala 686:18]
|
|
reg _T_3921 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 687:62]
|
|
_T_3921 <= iccm_rd_ecc_single_err_hold_in @[el2_ifu_mem_ctl.scala 687:62]
|
|
iccm_rd_ecc_single_err_ff <= _T_3921 @[el2_ifu_mem_ctl.scala 687:29]
|
|
node _T_3922 = cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux) @[Cat.scala 29:58]
|
|
node _T_3923 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 688:152]
|
|
reg _T_3924 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3923 : @[Reg.scala 28:19]
|
|
_T_3924 <= _T_3922 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
iccm_ecc_corr_data_ff <= _T_3924 @[el2_ifu_mem_ctl.scala 688:25]
|
|
node _T_3925 = bits(iccm_ecc_write_status, 0, 0) @[el2_ifu_mem_ctl.scala 689:119]
|
|
reg _T_3926 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_3925 : @[Reg.scala 28:19]
|
|
_T_3926 <= iccm_ecc_corr_index_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
iccm_ecc_corr_index_ff <= _T_3926 @[el2_ifu_mem_ctl.scala 689:26]
|
|
node _T_3927 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 690:41]
|
|
node _T_3928 = and(io.ifc_fetch_req_bf, _T_3927) @[el2_ifu_mem_ctl.scala 690:39]
|
|
node _T_3929 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 690:72]
|
|
node _T_3930 = and(_T_3928, _T_3929) @[el2_ifu_mem_ctl.scala 690:70]
|
|
node _T_3931 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 691:19]
|
|
node _T_3932 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:34]
|
|
node _T_3933 = and(_T_3931, _T_3932) @[el2_ifu_mem_ctl.scala 691:32]
|
|
node _T_3934 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 692:19]
|
|
node _T_3935 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 692:39]
|
|
node _T_3936 = and(_T_3934, _T_3935) @[el2_ifu_mem_ctl.scala 692:37]
|
|
node _T_3937 = or(_T_3933, _T_3936) @[el2_ifu_mem_ctl.scala 691:88]
|
|
node _T_3938 = eq(miss_state, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 693:19]
|
|
node _T_3939 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 693:43]
|
|
node _T_3940 = and(_T_3938, _T_3939) @[el2_ifu_mem_ctl.scala 693:41]
|
|
node _T_3941 = or(_T_3937, _T_3940) @[el2_ifu_mem_ctl.scala 692:88]
|
|
node _T_3942 = eq(miss_state, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 694:19]
|
|
node _T_3943 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 694:37]
|
|
node _T_3944 = and(_T_3942, _T_3943) @[el2_ifu_mem_ctl.scala 694:35]
|
|
node _T_3945 = or(_T_3941, _T_3944) @[el2_ifu_mem_ctl.scala 693:88]
|
|
node _T_3946 = eq(miss_state, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 695:19]
|
|
node _T_3947 = eq(miss_state_en, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 695:40]
|
|
node _T_3948 = and(_T_3946, _T_3947) @[el2_ifu_mem_ctl.scala 695:38]
|
|
node _T_3949 = or(_T_3945, _T_3948) @[el2_ifu_mem_ctl.scala 694:88]
|
|
node _T_3950 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 696:19]
|
|
node _T_3951 = and(_T_3950, miss_state_en) @[el2_ifu_mem_ctl.scala 696:37]
|
|
node _T_3952 = eq(miss_nxtstate, UInt<3>("h03")) @[el2_ifu_mem_ctl.scala 696:71]
|
|
node _T_3953 = and(_T_3951, _T_3952) @[el2_ifu_mem_ctl.scala 696:54]
|
|
node _T_3954 = or(_T_3949, _T_3953) @[el2_ifu_mem_ctl.scala 695:57]
|
|
node _T_3955 = eq(_T_3954, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 691:5]
|
|
node _T_3956 = and(_T_3930, _T_3955) @[el2_ifu_mem_ctl.scala 690:96]
|
|
node _T_3957 = and(io.ifc_fetch_req_bf, io.exu_flush_final) @[el2_ifu_mem_ctl.scala 697:28]
|
|
node _T_3958 = eq(io.ifc_fetch_uncacheable_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 697:52]
|
|
node _T_3959 = and(_T_3957, _T_3958) @[el2_ifu_mem_ctl.scala 697:50]
|
|
node _T_3960 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 697:83]
|
|
node _T_3961 = and(_T_3959, _T_3960) @[el2_ifu_mem_ctl.scala 697:81]
|
|
node _T_3962 = or(_T_3956, _T_3961) @[el2_ifu_mem_ctl.scala 696:93]
|
|
io.ic_rd_en <= _T_3962 @[el2_ifu_mem_ctl.scala 690:15]
|
|
wire bus_ic_wr_en : UInt<2>
|
|
bus_ic_wr_en <= UInt<1>("h00")
|
|
node _T_3963 = bits(write_ic_16_bytes, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_3964 = mux(_T_3963, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_3965 = and(bus_ic_wr_en, _T_3964) @[el2_ifu_mem_ctl.scala 699:31]
|
|
io.ic_wr_en <= _T_3965 @[el2_ifu_mem_ctl.scala 699:15]
|
|
node _T_3966 = eq(miss_state, UInt<3>("h01")) @[el2_ifu_mem_ctl.scala 700:59]
|
|
node _T_3967 = eq(miss_state, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 700:91]
|
|
node _T_3968 = or(io.exu_flush_final, ifu_bp_hit_taken_q_f) @[el2_ifu_mem_ctl.scala 700:127]
|
|
node _T_3969 = or(_T_3968, stream_eol_f) @[el2_ifu_mem_ctl.scala 700:151]
|
|
node _T_3970 = eq(_T_3969, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 700:106]
|
|
node _T_3971 = and(_T_3967, _T_3970) @[el2_ifu_mem_ctl.scala 700:104]
|
|
node _T_3972 = or(_T_3966, _T_3971) @[el2_ifu_mem_ctl.scala 700:77]
|
|
node _T_3973 = and(bus_ifu_wr_en_ff, last_beat) @[el2_ifu_mem_ctl.scala 700:191]
|
|
node _T_3974 = eq(uncacheable_miss_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 700:205]
|
|
node _T_3975 = and(_T_3973, _T_3974) @[el2_ifu_mem_ctl.scala 700:203]
|
|
node _T_3976 = eq(_T_3975, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 700:172]
|
|
node _T_3977 = and(_T_3972, _T_3976) @[el2_ifu_mem_ctl.scala 700:170]
|
|
node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 700:44]
|
|
node _T_3979 = and(write_ic_16_bytes, _T_3978) @[el2_ifu_mem_ctl.scala 700:42]
|
|
io.ic_write_stall <= _T_3979 @[el2_ifu_mem_ctl.scala 700:21]
|
|
reg _T_3980 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 701:53]
|
|
_T_3980 <= io.dec_tlu_fence_i_wb @[el2_ifu_mem_ctl.scala 701:53]
|
|
reset_all_tags <= _T_3980 @[el2_ifu_mem_ctl.scala 701:18]
|
|
node _T_3981 = eq(ifu_wr_cumulative_err_data, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 703:20]
|
|
node _T_3982 = or(reset_ic_in, reset_ic_ff) @[el2_ifu_mem_ctl.scala 703:64]
|
|
node _T_3983 = eq(_T_3982, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 703:50]
|
|
node _T_3984 = and(_T_3981, _T_3983) @[el2_ifu_mem_ctl.scala 703:48]
|
|
node _T_3985 = eq(reset_tag_valid_for_miss, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 703:81]
|
|
node ic_valid = and(_T_3984, _T_3985) @[el2_ifu_mem_ctl.scala 703:79]
|
|
node _T_3986 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 704:61]
|
|
node _T_3987 = and(_T_3986, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 704:82]
|
|
node _T_3988 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 704:123]
|
|
node _T_3989 = bits(ifu_status_wr_addr, 11, 5) @[el2_ifu_mem_ctl.scala 705:25]
|
|
node ifu_status_wr_addr_w_debug = mux(_T_3987, _T_3988, _T_3989) @[el2_ifu_mem_ctl.scala 704:41]
|
|
reg ifu_status_wr_addr_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 707:14]
|
|
ifu_status_wr_addr_ff <= ifu_status_wr_addr_w_debug @[el2_ifu_mem_ctl.scala 707:14]
|
|
wire way_status_wr_en : UInt<1>
|
|
way_status_wr_en <= UInt<1>("h00")
|
|
node _T_3990 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 710:74]
|
|
node way_status_wr_en_w_debug = or(way_status_wr_en, _T_3990) @[el2_ifu_mem_ctl.scala 710:53]
|
|
reg way_status_wr_en_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 712:14]
|
|
way_status_wr_en_ff <= way_status_wr_en_w_debug @[el2_ifu_mem_ctl.scala 712:14]
|
|
wire way_status_new : UInt<1>
|
|
way_status_new <= UInt<1>("h00")
|
|
node _T_3991 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 715:56]
|
|
node _T_3992 = bits(io.ic_debug_wr_data, 4, 4) @[el2_ifu_mem_ctl.scala 716:55]
|
|
node way_status_new_w_debug = mux(_T_3991, _T_3992, way_status_new) @[el2_ifu_mem_ctl.scala 715:37]
|
|
io.test <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 718:11]
|
|
reg way_status_new_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 720:14]
|
|
way_status_new_ff <= way_status_new_w_debug @[el2_ifu_mem_ctl.scala 720:14]
|
|
node _T_3993 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_0 = eq(_T_3993, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_3994 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_1 = eq(_T_3994, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_3995 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_2 = eq(_T_3995, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_3996 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_3 = eq(_T_3996, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_3997 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_4 = eq(_T_3997, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_3998 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_5 = eq(_T_3998, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_3999 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_6 = eq(_T_3999, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4000 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_7 = eq(_T_4000, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4001 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_8 = eq(_T_4001, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4002 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_9 = eq(_T_4002, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4003 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_10 = eq(_T_4003, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4004 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_11 = eq(_T_4004, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4005 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_12 = eq(_T_4005, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4006 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_13 = eq(_T_4006, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4007 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_14 = eq(_T_4007, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
node _T_4008 = bits(ifu_status_wr_addr_ff, 6, 3) @[el2_ifu_mem_ctl.scala 722:89]
|
|
node way_status_clken_15 = eq(_T_4008, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 722:132]
|
|
wire way_status_out : UInt<1>[128] @[el2_ifu_mem_ctl.scala 724:30]
|
|
node _T_4009 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4010 = eq(_T_4009, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4011 = and(_T_4010, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4012 = and(_T_4011, way_status_clken_0) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4013 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4012 : @[Reg.scala 28:19]
|
|
_T_4013 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[0] <= _T_4013 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4014 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4015 = eq(_T_4014, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4016 = and(_T_4015, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4017 = and(_T_4016, way_status_clken_0) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4018 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4017 : @[Reg.scala 28:19]
|
|
_T_4018 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[1] <= _T_4018 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4019 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4020 = eq(_T_4019, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4021 = and(_T_4020, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4022 = and(_T_4021, way_status_clken_0) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4023 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4022 : @[Reg.scala 28:19]
|
|
_T_4023 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[2] <= _T_4023 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4024 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4025 = eq(_T_4024, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4026 = and(_T_4025, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4027 = and(_T_4026, way_status_clken_0) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4028 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4027 : @[Reg.scala 28:19]
|
|
_T_4028 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[3] <= _T_4028 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4029 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4030 = eq(_T_4029, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4031 = and(_T_4030, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4032 = and(_T_4031, way_status_clken_0) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4033 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4032 : @[Reg.scala 28:19]
|
|
_T_4033 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[4] <= _T_4033 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4034 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4035 = eq(_T_4034, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4036 = and(_T_4035, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4037 = and(_T_4036, way_status_clken_0) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4038 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4037 : @[Reg.scala 28:19]
|
|
_T_4038 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[5] <= _T_4038 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4039 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4040 = eq(_T_4039, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4041 = and(_T_4040, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4042 = and(_T_4041, way_status_clken_0) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4043 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4042 : @[Reg.scala 28:19]
|
|
_T_4043 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[6] <= _T_4043 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4044 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4045 = eq(_T_4044, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4046 = and(_T_4045, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4047 = and(_T_4046, way_status_clken_0) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4048 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4047 : @[Reg.scala 28:19]
|
|
_T_4048 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[7] <= _T_4048 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4049 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4050 = eq(_T_4049, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4051 = and(_T_4050, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4052 = and(_T_4051, way_status_clken_1) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4053 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4052 : @[Reg.scala 28:19]
|
|
_T_4053 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[8] <= _T_4053 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4054 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4055 = eq(_T_4054, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4056 = and(_T_4055, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4057 = and(_T_4056, way_status_clken_1) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4058 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4057 : @[Reg.scala 28:19]
|
|
_T_4058 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[9] <= _T_4058 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4059 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4060 = eq(_T_4059, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4061 = and(_T_4060, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4062 = and(_T_4061, way_status_clken_1) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4063 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4062 : @[Reg.scala 28:19]
|
|
_T_4063 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[10] <= _T_4063 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4064 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4065 = eq(_T_4064, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4066 = and(_T_4065, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4067 = and(_T_4066, way_status_clken_1) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4068 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4067 : @[Reg.scala 28:19]
|
|
_T_4068 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[11] <= _T_4068 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4069 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4070 = eq(_T_4069, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4071 = and(_T_4070, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4072 = and(_T_4071, way_status_clken_1) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4073 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4072 : @[Reg.scala 28:19]
|
|
_T_4073 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[12] <= _T_4073 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4074 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4075 = eq(_T_4074, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4076 = and(_T_4075, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4077 = and(_T_4076, way_status_clken_1) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4078 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4077 : @[Reg.scala 28:19]
|
|
_T_4078 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[13] <= _T_4078 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4079 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4080 = eq(_T_4079, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4081 = and(_T_4080, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4082 = and(_T_4081, way_status_clken_1) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4083 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4082 : @[Reg.scala 28:19]
|
|
_T_4083 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[14] <= _T_4083 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4084 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4085 = eq(_T_4084, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4086 = and(_T_4085, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4087 = and(_T_4086, way_status_clken_1) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4088 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4087 : @[Reg.scala 28:19]
|
|
_T_4088 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[15] <= _T_4088 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4089 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4090 = eq(_T_4089, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4091 = and(_T_4090, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4092 = and(_T_4091, way_status_clken_2) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4093 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4092 : @[Reg.scala 28:19]
|
|
_T_4093 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[16] <= _T_4093 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4094 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4095 = eq(_T_4094, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4096 = and(_T_4095, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4097 = and(_T_4096, way_status_clken_2) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4098 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4097 : @[Reg.scala 28:19]
|
|
_T_4098 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[17] <= _T_4098 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4099 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4100 = eq(_T_4099, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4101 = and(_T_4100, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4102 = and(_T_4101, way_status_clken_2) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4103 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4102 : @[Reg.scala 28:19]
|
|
_T_4103 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[18] <= _T_4103 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4104 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4105 = eq(_T_4104, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4106 = and(_T_4105, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4107 = and(_T_4106, way_status_clken_2) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4108 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4107 : @[Reg.scala 28:19]
|
|
_T_4108 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[19] <= _T_4108 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4109 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4110 = eq(_T_4109, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4111 = and(_T_4110, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4112 = and(_T_4111, way_status_clken_2) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4113 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4112 : @[Reg.scala 28:19]
|
|
_T_4113 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[20] <= _T_4113 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4114 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4115 = eq(_T_4114, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4116 = and(_T_4115, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4117 = and(_T_4116, way_status_clken_2) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4118 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4117 : @[Reg.scala 28:19]
|
|
_T_4118 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[21] <= _T_4118 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4119 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4120 = eq(_T_4119, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4121 = and(_T_4120, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4122 = and(_T_4121, way_status_clken_2) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4123 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4122 : @[Reg.scala 28:19]
|
|
_T_4123 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[22] <= _T_4123 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4124 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4125 = eq(_T_4124, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4126 = and(_T_4125, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4127 = and(_T_4126, way_status_clken_2) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4128 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4127 : @[Reg.scala 28:19]
|
|
_T_4128 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[23] <= _T_4128 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4129 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4130 = eq(_T_4129, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4131 = and(_T_4130, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4132 = and(_T_4131, way_status_clken_3) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4133 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4132 : @[Reg.scala 28:19]
|
|
_T_4133 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[24] <= _T_4133 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4134 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4135 = eq(_T_4134, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4136 = and(_T_4135, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4137 = and(_T_4136, way_status_clken_3) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4138 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4137 : @[Reg.scala 28:19]
|
|
_T_4138 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[25] <= _T_4138 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4139 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4140 = eq(_T_4139, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4141 = and(_T_4140, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4142 = and(_T_4141, way_status_clken_3) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4143 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4142 : @[Reg.scala 28:19]
|
|
_T_4143 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[26] <= _T_4143 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4144 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4145 = eq(_T_4144, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4146 = and(_T_4145, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4147 = and(_T_4146, way_status_clken_3) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4148 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4147 : @[Reg.scala 28:19]
|
|
_T_4148 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[27] <= _T_4148 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4149 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4150 = eq(_T_4149, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4151 = and(_T_4150, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4152 = and(_T_4151, way_status_clken_3) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4152 : @[Reg.scala 28:19]
|
|
_T_4153 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[28] <= _T_4153 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4154 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4155 = eq(_T_4154, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4156 = and(_T_4155, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4157 = and(_T_4156, way_status_clken_3) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4158 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4157 : @[Reg.scala 28:19]
|
|
_T_4158 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[29] <= _T_4158 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4159 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4160 = eq(_T_4159, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4161 = and(_T_4160, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4162 = and(_T_4161, way_status_clken_3) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4163 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4162 : @[Reg.scala 28:19]
|
|
_T_4163 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[30] <= _T_4163 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4164 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4165 = eq(_T_4164, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4166 = and(_T_4165, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4167 = and(_T_4166, way_status_clken_3) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4167 : @[Reg.scala 28:19]
|
|
_T_4168 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[31] <= _T_4168 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4169 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4170 = eq(_T_4169, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4171 = and(_T_4170, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4172 = and(_T_4171, way_status_clken_4) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4173 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4172 : @[Reg.scala 28:19]
|
|
_T_4173 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[32] <= _T_4173 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4174 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4175 = eq(_T_4174, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4176 = and(_T_4175, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4177 = and(_T_4176, way_status_clken_4) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4178 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4177 : @[Reg.scala 28:19]
|
|
_T_4178 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[33] <= _T_4178 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4179 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4180 = eq(_T_4179, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4181 = and(_T_4180, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4182 = and(_T_4181, way_status_clken_4) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4183 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4182 : @[Reg.scala 28:19]
|
|
_T_4183 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[34] <= _T_4183 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4184 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4185 = eq(_T_4184, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4186 = and(_T_4185, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4187 = and(_T_4186, way_status_clken_4) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4188 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4187 : @[Reg.scala 28:19]
|
|
_T_4188 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[35] <= _T_4188 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4189 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4190 = eq(_T_4189, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4191 = and(_T_4190, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4192 = and(_T_4191, way_status_clken_4) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4193 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4192 : @[Reg.scala 28:19]
|
|
_T_4193 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[36] <= _T_4193 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4194 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4195 = eq(_T_4194, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4196 = and(_T_4195, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4197 = and(_T_4196, way_status_clken_4) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4198 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4197 : @[Reg.scala 28:19]
|
|
_T_4198 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[37] <= _T_4198 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4199 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4200 = eq(_T_4199, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4201 = and(_T_4200, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4202 = and(_T_4201, way_status_clken_4) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4203 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4202 : @[Reg.scala 28:19]
|
|
_T_4203 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[38] <= _T_4203 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4204 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4205 = eq(_T_4204, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4206 = and(_T_4205, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4207 = and(_T_4206, way_status_clken_4) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4208 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4207 : @[Reg.scala 28:19]
|
|
_T_4208 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[39] <= _T_4208 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4209 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4210 = eq(_T_4209, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4211 = and(_T_4210, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4212 = and(_T_4211, way_status_clken_5) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4213 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4212 : @[Reg.scala 28:19]
|
|
_T_4213 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[40] <= _T_4213 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4214 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4215 = eq(_T_4214, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4216 = and(_T_4215, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4217 = and(_T_4216, way_status_clken_5) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4218 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4217 : @[Reg.scala 28:19]
|
|
_T_4218 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[41] <= _T_4218 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4219 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4220 = eq(_T_4219, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4221 = and(_T_4220, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4222 = and(_T_4221, way_status_clken_5) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4223 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4222 : @[Reg.scala 28:19]
|
|
_T_4223 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[42] <= _T_4223 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4224 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4225 = eq(_T_4224, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4226 = and(_T_4225, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4227 = and(_T_4226, way_status_clken_5) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4228 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4227 : @[Reg.scala 28:19]
|
|
_T_4228 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[43] <= _T_4228 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4229 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4230 = eq(_T_4229, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4231 = and(_T_4230, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4232 = and(_T_4231, way_status_clken_5) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4233 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4232 : @[Reg.scala 28:19]
|
|
_T_4233 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[44] <= _T_4233 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4234 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4235 = eq(_T_4234, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4236 = and(_T_4235, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4237 = and(_T_4236, way_status_clken_5) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4238 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4237 : @[Reg.scala 28:19]
|
|
_T_4238 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[45] <= _T_4238 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4239 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4240 = eq(_T_4239, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4241 = and(_T_4240, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4242 = and(_T_4241, way_status_clken_5) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4243 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4242 : @[Reg.scala 28:19]
|
|
_T_4243 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[46] <= _T_4243 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4244 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4245 = eq(_T_4244, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4246 = and(_T_4245, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4247 = and(_T_4246, way_status_clken_5) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4248 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4247 : @[Reg.scala 28:19]
|
|
_T_4248 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[47] <= _T_4248 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4249 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4250 = eq(_T_4249, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4251 = and(_T_4250, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4252 = and(_T_4251, way_status_clken_6) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4253 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4252 : @[Reg.scala 28:19]
|
|
_T_4253 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[48] <= _T_4253 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4254 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4255 = eq(_T_4254, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4256 = and(_T_4255, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4257 = and(_T_4256, way_status_clken_6) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4258 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4257 : @[Reg.scala 28:19]
|
|
_T_4258 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[49] <= _T_4258 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4259 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4260 = eq(_T_4259, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4261 = and(_T_4260, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4262 = and(_T_4261, way_status_clken_6) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4263 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4262 : @[Reg.scala 28:19]
|
|
_T_4263 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[50] <= _T_4263 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4264 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4265 = eq(_T_4264, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4266 = and(_T_4265, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4267 = and(_T_4266, way_status_clken_6) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4268 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4267 : @[Reg.scala 28:19]
|
|
_T_4268 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[51] <= _T_4268 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4269 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4270 = eq(_T_4269, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4271 = and(_T_4270, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4272 = and(_T_4271, way_status_clken_6) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4273 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4272 : @[Reg.scala 28:19]
|
|
_T_4273 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[52] <= _T_4273 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4274 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4275 = eq(_T_4274, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4276 = and(_T_4275, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4277 = and(_T_4276, way_status_clken_6) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4278 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4277 : @[Reg.scala 28:19]
|
|
_T_4278 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[53] <= _T_4278 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4279 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4280 = eq(_T_4279, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4281 = and(_T_4280, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4282 = and(_T_4281, way_status_clken_6) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4283 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4282 : @[Reg.scala 28:19]
|
|
_T_4283 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[54] <= _T_4283 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4284 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4285 = eq(_T_4284, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4286 = and(_T_4285, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4287 = and(_T_4286, way_status_clken_6) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4288 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4287 : @[Reg.scala 28:19]
|
|
_T_4288 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[55] <= _T_4288 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4289 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4290 = eq(_T_4289, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4291 = and(_T_4290, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4292 = and(_T_4291, way_status_clken_7) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4293 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4292 : @[Reg.scala 28:19]
|
|
_T_4293 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[56] <= _T_4293 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4294 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4295 = eq(_T_4294, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4296 = and(_T_4295, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4297 = and(_T_4296, way_status_clken_7) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4298 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4297 : @[Reg.scala 28:19]
|
|
_T_4298 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[57] <= _T_4298 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4299 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4300 = eq(_T_4299, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4301 = and(_T_4300, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4302 = and(_T_4301, way_status_clken_7) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4303 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4302 : @[Reg.scala 28:19]
|
|
_T_4303 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[58] <= _T_4303 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4304 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4305 = eq(_T_4304, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4306 = and(_T_4305, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4307 = and(_T_4306, way_status_clken_7) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4307 : @[Reg.scala 28:19]
|
|
_T_4308 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[59] <= _T_4308 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4309 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4310 = eq(_T_4309, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4311 = and(_T_4310, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4312 = and(_T_4311, way_status_clken_7) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4312 : @[Reg.scala 28:19]
|
|
_T_4313 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[60] <= _T_4313 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4314 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4315 = eq(_T_4314, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4316 = and(_T_4315, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4317 = and(_T_4316, way_status_clken_7) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4318 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4317 : @[Reg.scala 28:19]
|
|
_T_4318 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[61] <= _T_4318 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4319 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4320 = eq(_T_4319, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4321 = and(_T_4320, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4322 = and(_T_4321, way_status_clken_7) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4323 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4322 : @[Reg.scala 28:19]
|
|
_T_4323 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[62] <= _T_4323 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4324 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4325 = eq(_T_4324, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4326 = and(_T_4325, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4327 = and(_T_4326, way_status_clken_7) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4328 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4327 : @[Reg.scala 28:19]
|
|
_T_4328 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[63] <= _T_4328 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4329 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4330 = eq(_T_4329, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4331 = and(_T_4330, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4332 = and(_T_4331, way_status_clken_8) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4333 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4332 : @[Reg.scala 28:19]
|
|
_T_4333 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[64] <= _T_4333 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4334 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4335 = eq(_T_4334, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4336 = and(_T_4335, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4337 = and(_T_4336, way_status_clken_8) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4338 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4337 : @[Reg.scala 28:19]
|
|
_T_4338 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[65] <= _T_4338 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4339 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4340 = eq(_T_4339, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4341 = and(_T_4340, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4342 = and(_T_4341, way_status_clken_8) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4343 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4342 : @[Reg.scala 28:19]
|
|
_T_4343 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[66] <= _T_4343 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4344 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4345 = eq(_T_4344, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4346 = and(_T_4345, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4347 = and(_T_4346, way_status_clken_8) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4348 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4347 : @[Reg.scala 28:19]
|
|
_T_4348 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[67] <= _T_4348 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4349 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4350 = eq(_T_4349, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4351 = and(_T_4350, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4352 = and(_T_4351, way_status_clken_8) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4353 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4352 : @[Reg.scala 28:19]
|
|
_T_4353 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[68] <= _T_4353 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4354 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4355 = eq(_T_4354, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4356 = and(_T_4355, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4357 = and(_T_4356, way_status_clken_8) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4358 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4357 : @[Reg.scala 28:19]
|
|
_T_4358 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[69] <= _T_4358 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4359 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4360 = eq(_T_4359, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4361 = and(_T_4360, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4362 = and(_T_4361, way_status_clken_8) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4363 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4362 : @[Reg.scala 28:19]
|
|
_T_4363 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[70] <= _T_4363 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4364 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4365 = eq(_T_4364, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4366 = and(_T_4365, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4367 = and(_T_4366, way_status_clken_8) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4368 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4367 : @[Reg.scala 28:19]
|
|
_T_4368 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[71] <= _T_4368 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4369 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4370 = eq(_T_4369, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4371 = and(_T_4370, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4372 = and(_T_4371, way_status_clken_9) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4373 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4372 : @[Reg.scala 28:19]
|
|
_T_4373 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[72] <= _T_4373 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4374 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4375 = eq(_T_4374, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4376 = and(_T_4375, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4377 = and(_T_4376, way_status_clken_9) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4378 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4377 : @[Reg.scala 28:19]
|
|
_T_4378 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[73] <= _T_4378 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4379 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4380 = eq(_T_4379, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4381 = and(_T_4380, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4382 = and(_T_4381, way_status_clken_9) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4383 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4382 : @[Reg.scala 28:19]
|
|
_T_4383 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[74] <= _T_4383 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4384 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4385 = eq(_T_4384, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4386 = and(_T_4385, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4387 = and(_T_4386, way_status_clken_9) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4388 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4387 : @[Reg.scala 28:19]
|
|
_T_4388 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[75] <= _T_4388 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4389 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4390 = eq(_T_4389, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4391 = and(_T_4390, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4392 = and(_T_4391, way_status_clken_9) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4393 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4392 : @[Reg.scala 28:19]
|
|
_T_4393 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[76] <= _T_4393 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4394 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4395 = eq(_T_4394, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4396 = and(_T_4395, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4397 = and(_T_4396, way_status_clken_9) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4398 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4397 : @[Reg.scala 28:19]
|
|
_T_4398 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[77] <= _T_4398 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4399 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4400 = eq(_T_4399, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4401 = and(_T_4400, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4402 = and(_T_4401, way_status_clken_9) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4403 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4402 : @[Reg.scala 28:19]
|
|
_T_4403 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[78] <= _T_4403 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4404 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4405 = eq(_T_4404, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4406 = and(_T_4405, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4407 = and(_T_4406, way_status_clken_9) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4408 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4407 : @[Reg.scala 28:19]
|
|
_T_4408 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[79] <= _T_4408 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4409 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4410 = eq(_T_4409, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4411 = and(_T_4410, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4412 = and(_T_4411, way_status_clken_10) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4413 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4412 : @[Reg.scala 28:19]
|
|
_T_4413 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[80] <= _T_4413 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4414 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4415 = eq(_T_4414, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4416 = and(_T_4415, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4417 = and(_T_4416, way_status_clken_10) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4418 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4417 : @[Reg.scala 28:19]
|
|
_T_4418 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[81] <= _T_4418 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4419 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4420 = eq(_T_4419, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4421 = and(_T_4420, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4422 = and(_T_4421, way_status_clken_10) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4423 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4422 : @[Reg.scala 28:19]
|
|
_T_4423 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[82] <= _T_4423 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4424 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4425 = eq(_T_4424, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4426 = and(_T_4425, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4427 = and(_T_4426, way_status_clken_10) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4428 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4427 : @[Reg.scala 28:19]
|
|
_T_4428 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[83] <= _T_4428 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4429 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4430 = eq(_T_4429, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4431 = and(_T_4430, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4432 = and(_T_4431, way_status_clken_10) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4433 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4432 : @[Reg.scala 28:19]
|
|
_T_4433 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[84] <= _T_4433 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4434 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4435 = eq(_T_4434, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4436 = and(_T_4435, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4437 = and(_T_4436, way_status_clken_10) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4438 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4437 : @[Reg.scala 28:19]
|
|
_T_4438 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[85] <= _T_4438 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4439 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4440 = eq(_T_4439, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4441 = and(_T_4440, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4442 = and(_T_4441, way_status_clken_10) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4443 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4442 : @[Reg.scala 28:19]
|
|
_T_4443 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[86] <= _T_4443 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4444 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4445 = eq(_T_4444, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4446 = and(_T_4445, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4447 = and(_T_4446, way_status_clken_10) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4448 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4447 : @[Reg.scala 28:19]
|
|
_T_4448 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[87] <= _T_4448 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4449 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4450 = eq(_T_4449, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4451 = and(_T_4450, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4452 = and(_T_4451, way_status_clken_11) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4453 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4452 : @[Reg.scala 28:19]
|
|
_T_4453 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[88] <= _T_4453 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4454 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4455 = eq(_T_4454, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4456 = and(_T_4455, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4457 = and(_T_4456, way_status_clken_11) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4458 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4457 : @[Reg.scala 28:19]
|
|
_T_4458 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[89] <= _T_4458 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4459 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4460 = eq(_T_4459, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4461 = and(_T_4460, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4462 = and(_T_4461, way_status_clken_11) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4463 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4462 : @[Reg.scala 28:19]
|
|
_T_4463 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[90] <= _T_4463 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4464 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4465 = eq(_T_4464, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4466 = and(_T_4465, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4467 = and(_T_4466, way_status_clken_11) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4468 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4467 : @[Reg.scala 28:19]
|
|
_T_4468 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[91] <= _T_4468 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4469 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4470 = eq(_T_4469, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4471 = and(_T_4470, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4472 = and(_T_4471, way_status_clken_11) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4473 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4472 : @[Reg.scala 28:19]
|
|
_T_4473 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[92] <= _T_4473 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4474 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4475 = eq(_T_4474, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4476 = and(_T_4475, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4477 = and(_T_4476, way_status_clken_11) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4478 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4477 : @[Reg.scala 28:19]
|
|
_T_4478 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[93] <= _T_4478 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4479 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4480 = eq(_T_4479, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4481 = and(_T_4480, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4482 = and(_T_4481, way_status_clken_11) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4483 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4482 : @[Reg.scala 28:19]
|
|
_T_4483 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[94] <= _T_4483 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4484 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4485 = eq(_T_4484, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4486 = and(_T_4485, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4487 = and(_T_4486, way_status_clken_11) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4488 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4487 : @[Reg.scala 28:19]
|
|
_T_4488 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[95] <= _T_4488 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4489 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4490 = eq(_T_4489, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4491 = and(_T_4490, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4492 = and(_T_4491, way_status_clken_12) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4493 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4492 : @[Reg.scala 28:19]
|
|
_T_4493 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[96] <= _T_4493 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4494 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4495 = eq(_T_4494, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4496 = and(_T_4495, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4497 = and(_T_4496, way_status_clken_12) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4498 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4497 : @[Reg.scala 28:19]
|
|
_T_4498 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[97] <= _T_4498 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4499 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4500 = eq(_T_4499, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4501 = and(_T_4500, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4502 = and(_T_4501, way_status_clken_12) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4503 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4502 : @[Reg.scala 28:19]
|
|
_T_4503 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[98] <= _T_4503 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4504 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4505 = eq(_T_4504, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4506 = and(_T_4505, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4507 = and(_T_4506, way_status_clken_12) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4508 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4507 : @[Reg.scala 28:19]
|
|
_T_4508 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[99] <= _T_4508 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4509 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4510 = eq(_T_4509, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4511 = and(_T_4510, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4512 = and(_T_4511, way_status_clken_12) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4513 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4512 : @[Reg.scala 28:19]
|
|
_T_4513 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[100] <= _T_4513 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4514 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4515 = eq(_T_4514, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4516 = and(_T_4515, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4517 = and(_T_4516, way_status_clken_12) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4518 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4517 : @[Reg.scala 28:19]
|
|
_T_4518 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[101] <= _T_4518 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4519 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4520 = eq(_T_4519, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4521 = and(_T_4520, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4522 = and(_T_4521, way_status_clken_12) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4523 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4522 : @[Reg.scala 28:19]
|
|
_T_4523 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[102] <= _T_4523 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4524 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4525 = eq(_T_4524, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4526 = and(_T_4525, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4527 = and(_T_4526, way_status_clken_12) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4528 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4527 : @[Reg.scala 28:19]
|
|
_T_4528 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[103] <= _T_4528 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4529 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4530 = eq(_T_4529, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4531 = and(_T_4530, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4532 = and(_T_4531, way_status_clken_13) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4533 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4532 : @[Reg.scala 28:19]
|
|
_T_4533 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[104] <= _T_4533 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4534 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4535 = eq(_T_4534, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4536 = and(_T_4535, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4537 = and(_T_4536, way_status_clken_13) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4538 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4537 : @[Reg.scala 28:19]
|
|
_T_4538 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[105] <= _T_4538 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4539 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4540 = eq(_T_4539, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4541 = and(_T_4540, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4542 = and(_T_4541, way_status_clken_13) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4543 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4542 : @[Reg.scala 28:19]
|
|
_T_4543 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[106] <= _T_4543 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4544 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4545 = eq(_T_4544, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4546 = and(_T_4545, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4547 = and(_T_4546, way_status_clken_13) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4548 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4547 : @[Reg.scala 28:19]
|
|
_T_4548 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[107] <= _T_4548 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4549 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4550 = eq(_T_4549, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4551 = and(_T_4550, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4552 = and(_T_4551, way_status_clken_13) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4553 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4552 : @[Reg.scala 28:19]
|
|
_T_4553 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[108] <= _T_4553 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4554 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4555 = eq(_T_4554, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4556 = and(_T_4555, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4557 = and(_T_4556, way_status_clken_13) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4558 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4557 : @[Reg.scala 28:19]
|
|
_T_4558 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[109] <= _T_4558 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4559 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4560 = eq(_T_4559, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4561 = and(_T_4560, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4562 = and(_T_4561, way_status_clken_13) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4563 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4562 : @[Reg.scala 28:19]
|
|
_T_4563 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[110] <= _T_4563 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4564 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4565 = eq(_T_4564, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4566 = and(_T_4565, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4567 = and(_T_4566, way_status_clken_13) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4568 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4567 : @[Reg.scala 28:19]
|
|
_T_4568 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[111] <= _T_4568 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4569 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4570 = eq(_T_4569, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4571 = and(_T_4570, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4572 = and(_T_4571, way_status_clken_14) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4573 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4572 : @[Reg.scala 28:19]
|
|
_T_4573 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[112] <= _T_4573 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4574 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4575 = eq(_T_4574, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4576 = and(_T_4575, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4577 = and(_T_4576, way_status_clken_14) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4578 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4577 : @[Reg.scala 28:19]
|
|
_T_4578 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[113] <= _T_4578 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4579 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4580 = eq(_T_4579, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4581 = and(_T_4580, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4582 = and(_T_4581, way_status_clken_14) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4583 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4582 : @[Reg.scala 28:19]
|
|
_T_4583 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[114] <= _T_4583 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4584 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4585 = eq(_T_4584, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4586 = and(_T_4585, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4587 = and(_T_4586, way_status_clken_14) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4588 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4587 : @[Reg.scala 28:19]
|
|
_T_4588 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[115] <= _T_4588 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4589 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4590 = eq(_T_4589, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4591 = and(_T_4590, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4592 = and(_T_4591, way_status_clken_14) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4593 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4592 : @[Reg.scala 28:19]
|
|
_T_4593 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[116] <= _T_4593 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4594 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4595 = eq(_T_4594, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4596 = and(_T_4595, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4597 = and(_T_4596, way_status_clken_14) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4598 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4597 : @[Reg.scala 28:19]
|
|
_T_4598 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[117] <= _T_4598 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4599 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4600 = eq(_T_4599, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4601 = and(_T_4600, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4602 = and(_T_4601, way_status_clken_14) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4603 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4602 : @[Reg.scala 28:19]
|
|
_T_4603 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[118] <= _T_4603 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4604 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4605 = eq(_T_4604, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4606 = and(_T_4605, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4607 = and(_T_4606, way_status_clken_14) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4608 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4607 : @[Reg.scala 28:19]
|
|
_T_4608 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[119] <= _T_4608 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4609 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4610 = eq(_T_4609, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4611 = and(_T_4610, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4612 = and(_T_4611, way_status_clken_15) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4613 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4612 : @[Reg.scala 28:19]
|
|
_T_4613 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[120] <= _T_4613 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4614 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4615 = eq(_T_4614, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4616 = and(_T_4615, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4617 = and(_T_4616, way_status_clken_15) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4618 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4617 : @[Reg.scala 28:19]
|
|
_T_4618 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[121] <= _T_4618 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4619 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4620 = eq(_T_4619, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4621 = and(_T_4620, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4622 = and(_T_4621, way_status_clken_15) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4623 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4622 : @[Reg.scala 28:19]
|
|
_T_4623 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[122] <= _T_4623 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4624 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4625 = eq(_T_4624, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4626 = and(_T_4625, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4627 = and(_T_4626, way_status_clken_15) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4628 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4627 : @[Reg.scala 28:19]
|
|
_T_4628 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[123] <= _T_4628 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4629 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4630 = eq(_T_4629, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4631 = and(_T_4630, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4632 = and(_T_4631, way_status_clken_15) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4633 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4632 : @[Reg.scala 28:19]
|
|
_T_4633 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[124] <= _T_4633 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4634 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4635 = eq(_T_4634, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4636 = and(_T_4635, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4637 = and(_T_4636, way_status_clken_15) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4638 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4637 : @[Reg.scala 28:19]
|
|
_T_4638 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[125] <= _T_4638 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4639 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4640 = eq(_T_4639, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4641 = and(_T_4640, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4642 = and(_T_4641, way_status_clken_15) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4643 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4642 : @[Reg.scala 28:19]
|
|
_T_4643 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[126] <= _T_4643 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4644 = bits(ifu_status_wr_addr_ff, 2, 0) @[el2_ifu_mem_ctl.scala 726:95]
|
|
node _T_4645 = eq(_T_4644, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 726:100]
|
|
node _T_4646 = and(_T_4645, way_status_wr_en_ff) @[el2_ifu_mem_ctl.scala 726:108]
|
|
node _T_4647 = and(_T_4646, way_status_clken_15) @[el2_ifu_mem_ctl.scala 726:131]
|
|
reg _T_4648 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_4647 : @[Reg.scala 28:19]
|
|
_T_4648 <= way_status_new_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
way_status_out[127] <= _T_4648 @[el2_ifu_mem_ctl.scala 726:35]
|
|
node _T_4649 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4650 = bits(_T_4649, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4651 = mux(_T_4650, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4652 = and(_T_4651, way_status_out[0]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4653 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4654 = bits(_T_4653, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4655 = mux(_T_4654, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4656 = and(_T_4655, way_status_out[1]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4657 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4658 = bits(_T_4657, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4659 = mux(_T_4658, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4660 = and(_T_4659, way_status_out[2]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4661 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4662 = bits(_T_4661, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4663 = mux(_T_4662, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4664 = and(_T_4663, way_status_out[3]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4665 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4666 = bits(_T_4665, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4667 = mux(_T_4666, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4668 = and(_T_4667, way_status_out[4]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4669 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4670 = bits(_T_4669, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4671 = mux(_T_4670, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4672 = and(_T_4671, way_status_out[5]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4673 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4674 = bits(_T_4673, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4675 = mux(_T_4674, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4676 = and(_T_4675, way_status_out[6]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4677 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4678 = bits(_T_4677, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4679 = mux(_T_4678, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4680 = and(_T_4679, way_status_out[7]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4681 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4682 = bits(_T_4681, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4683 = mux(_T_4682, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4684 = and(_T_4683, way_status_out[8]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4685 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4686 = bits(_T_4685, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4687 = mux(_T_4686, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4688 = and(_T_4687, way_status_out[9]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4689 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4690 = bits(_T_4689, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4691 = mux(_T_4690, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4692 = and(_T_4691, way_status_out[10]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4693 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4694 = bits(_T_4693, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4695 = mux(_T_4694, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4696 = and(_T_4695, way_status_out[11]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4697 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4698 = bits(_T_4697, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4699 = mux(_T_4698, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4700 = and(_T_4699, way_status_out[12]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4701 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4702 = bits(_T_4701, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4703 = mux(_T_4702, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4704 = and(_T_4703, way_status_out[13]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4705 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4706 = bits(_T_4705, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4707 = mux(_T_4706, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4708 = and(_T_4707, way_status_out[14]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4709 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4710 = bits(_T_4709, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4711 = mux(_T_4710, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4712 = and(_T_4711, way_status_out[15]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4713 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4714 = bits(_T_4713, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4715 = mux(_T_4714, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4716 = and(_T_4715, way_status_out[16]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4717 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4718 = bits(_T_4717, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4719 = mux(_T_4718, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4720 = and(_T_4719, way_status_out[17]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4721 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4722 = bits(_T_4721, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4723 = mux(_T_4722, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4724 = and(_T_4723, way_status_out[18]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4725 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4726 = bits(_T_4725, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4727 = mux(_T_4726, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4728 = and(_T_4727, way_status_out[19]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4729 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4730 = bits(_T_4729, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4731 = mux(_T_4730, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4732 = and(_T_4731, way_status_out[20]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4733 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4734 = bits(_T_4733, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4735 = mux(_T_4734, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4736 = and(_T_4735, way_status_out[21]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4737 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4738 = bits(_T_4737, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4739 = mux(_T_4738, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4740 = and(_T_4739, way_status_out[22]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4741 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4742 = bits(_T_4741, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4743 = mux(_T_4742, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4744 = and(_T_4743, way_status_out[23]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4745 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4746 = bits(_T_4745, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4747 = mux(_T_4746, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4748 = and(_T_4747, way_status_out[24]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4749 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4750 = bits(_T_4749, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4751 = mux(_T_4750, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4752 = and(_T_4751, way_status_out[25]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4753 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4754 = bits(_T_4753, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4755 = mux(_T_4754, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4756 = and(_T_4755, way_status_out[26]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4757 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4758 = bits(_T_4757, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4759 = mux(_T_4758, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4760 = and(_T_4759, way_status_out[27]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4761 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4762 = bits(_T_4761, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4763 = mux(_T_4762, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4764 = and(_T_4763, way_status_out[28]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4765 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4766 = bits(_T_4765, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4767 = mux(_T_4766, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4768 = and(_T_4767, way_status_out[29]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4769 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4770 = bits(_T_4769, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4771 = mux(_T_4770, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4772 = and(_T_4771, way_status_out[30]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4773 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4774 = bits(_T_4773, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4775 = mux(_T_4774, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4776 = and(_T_4775, way_status_out[31]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4777 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4778 = bits(_T_4777, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4779 = mux(_T_4778, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4780 = and(_T_4779, way_status_out[32]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4781 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4782 = bits(_T_4781, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4783 = mux(_T_4782, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4784 = and(_T_4783, way_status_out[33]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4785 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4786 = bits(_T_4785, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4787 = mux(_T_4786, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4788 = and(_T_4787, way_status_out[34]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4789 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4790 = bits(_T_4789, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4791 = mux(_T_4790, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4792 = and(_T_4791, way_status_out[35]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4793 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4794 = bits(_T_4793, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4795 = mux(_T_4794, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4796 = and(_T_4795, way_status_out[36]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4797 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4798 = bits(_T_4797, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4799 = mux(_T_4798, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4800 = and(_T_4799, way_status_out[37]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4801 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4802 = bits(_T_4801, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4803 = mux(_T_4802, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4804 = and(_T_4803, way_status_out[38]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4805 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4806 = bits(_T_4805, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4807 = mux(_T_4806, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4808 = and(_T_4807, way_status_out[39]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4809 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4810 = bits(_T_4809, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4811 = mux(_T_4810, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4812 = and(_T_4811, way_status_out[40]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4813 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4814 = bits(_T_4813, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4815 = mux(_T_4814, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4816 = and(_T_4815, way_status_out[41]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4817 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4818 = bits(_T_4817, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4819 = mux(_T_4818, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4820 = and(_T_4819, way_status_out[42]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4821 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4822 = bits(_T_4821, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4823 = mux(_T_4822, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4824 = and(_T_4823, way_status_out[43]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4825 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4826 = bits(_T_4825, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4827 = mux(_T_4826, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4828 = and(_T_4827, way_status_out[44]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4829 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4830 = bits(_T_4829, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4831 = mux(_T_4830, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4832 = and(_T_4831, way_status_out[45]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4833 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4834 = bits(_T_4833, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4835 = mux(_T_4834, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4836 = and(_T_4835, way_status_out[46]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4837 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4838 = bits(_T_4837, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4839 = mux(_T_4838, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4840 = and(_T_4839, way_status_out[47]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4841 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4842 = bits(_T_4841, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4843 = mux(_T_4842, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4844 = and(_T_4843, way_status_out[48]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4845 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4846 = bits(_T_4845, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4847 = mux(_T_4846, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4848 = and(_T_4847, way_status_out[49]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4849 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4850 = bits(_T_4849, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4851 = mux(_T_4850, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4852 = and(_T_4851, way_status_out[50]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4853 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4854 = bits(_T_4853, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4855 = mux(_T_4854, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4856 = and(_T_4855, way_status_out[51]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4857 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4858 = bits(_T_4857, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4859 = mux(_T_4858, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4860 = and(_T_4859, way_status_out[52]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4861 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4862 = bits(_T_4861, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4863 = mux(_T_4862, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4864 = and(_T_4863, way_status_out[53]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4865 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4866 = bits(_T_4865, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4867 = mux(_T_4866, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4868 = and(_T_4867, way_status_out[54]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4869 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4870 = bits(_T_4869, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4871 = mux(_T_4870, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4872 = and(_T_4871, way_status_out[55]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4873 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4874 = bits(_T_4873, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4875 = mux(_T_4874, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4876 = and(_T_4875, way_status_out[56]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4877 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4878 = bits(_T_4877, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4879 = mux(_T_4878, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4880 = and(_T_4879, way_status_out[57]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4881 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4882 = bits(_T_4881, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4883 = mux(_T_4882, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4884 = and(_T_4883, way_status_out[58]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4885 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4886 = bits(_T_4885, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4887 = mux(_T_4886, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4888 = and(_T_4887, way_status_out[59]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4889 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4890 = bits(_T_4889, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4891 = mux(_T_4890, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4892 = and(_T_4891, way_status_out[60]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4893 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4894 = bits(_T_4893, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4895 = mux(_T_4894, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4896 = and(_T_4895, way_status_out[61]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4897 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4898 = bits(_T_4897, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4899 = mux(_T_4898, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4900 = and(_T_4899, way_status_out[62]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4901 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4902 = bits(_T_4901, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4903 = mux(_T_4902, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4904 = and(_T_4903, way_status_out[63]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4905 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4906 = bits(_T_4905, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4907 = mux(_T_4906, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4908 = and(_T_4907, way_status_out[64]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4909 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4910 = bits(_T_4909, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4911 = mux(_T_4910, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4912 = and(_T_4911, way_status_out[65]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4913 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4914 = bits(_T_4913, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4915 = mux(_T_4914, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4916 = and(_T_4915, way_status_out[66]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4917 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4918 = bits(_T_4917, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4919 = mux(_T_4918, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4920 = and(_T_4919, way_status_out[67]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4921 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4922 = bits(_T_4921, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4923 = mux(_T_4922, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4924 = and(_T_4923, way_status_out[68]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4925 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4926 = bits(_T_4925, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4927 = mux(_T_4926, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4928 = and(_T_4927, way_status_out[69]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4929 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4930 = bits(_T_4929, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4931 = mux(_T_4930, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4932 = and(_T_4931, way_status_out[70]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4933 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4934 = bits(_T_4933, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4935 = mux(_T_4934, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4936 = and(_T_4935, way_status_out[71]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4937 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4938 = bits(_T_4937, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4939 = mux(_T_4938, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4940 = and(_T_4939, way_status_out[72]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4941 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4942 = bits(_T_4941, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4943 = mux(_T_4942, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4944 = and(_T_4943, way_status_out[73]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4945 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4946 = bits(_T_4945, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4947 = mux(_T_4946, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4948 = and(_T_4947, way_status_out[74]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4949 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4950 = bits(_T_4949, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4951 = mux(_T_4950, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4952 = and(_T_4951, way_status_out[75]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4953 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4954 = bits(_T_4953, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4955 = mux(_T_4954, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4956 = and(_T_4955, way_status_out[76]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4957 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4958 = bits(_T_4957, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4959 = mux(_T_4958, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4960 = and(_T_4959, way_status_out[77]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4961 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4962 = bits(_T_4961, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4963 = mux(_T_4962, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4964 = and(_T_4963, way_status_out[78]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4965 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4966 = bits(_T_4965, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4967 = mux(_T_4966, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4968 = and(_T_4967, way_status_out[79]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4969 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4970 = bits(_T_4969, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4971 = mux(_T_4970, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4972 = and(_T_4971, way_status_out[80]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4973 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4974 = bits(_T_4973, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4975 = mux(_T_4974, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4976 = and(_T_4975, way_status_out[81]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4977 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4978 = bits(_T_4977, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4979 = mux(_T_4978, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4980 = and(_T_4979, way_status_out[82]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4981 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4982 = bits(_T_4981, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4983 = mux(_T_4982, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4984 = and(_T_4983, way_status_out[83]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4985 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4986 = bits(_T_4985, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4987 = mux(_T_4986, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4988 = and(_T_4987, way_status_out[84]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4989 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4990 = bits(_T_4989, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4991 = mux(_T_4990, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4992 = and(_T_4991, way_status_out[85]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4993 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4994 = bits(_T_4993, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4995 = mux(_T_4994, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_4996 = and(_T_4995, way_status_out[86]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_4997 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_4998 = bits(_T_4997, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_4999 = mux(_T_4998, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5000 = and(_T_4999, way_status_out[87]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5001 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5002 = bits(_T_5001, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5003 = mux(_T_5002, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5004 = and(_T_5003, way_status_out[88]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5005 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5006 = bits(_T_5005, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5007 = mux(_T_5006, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5008 = and(_T_5007, way_status_out[89]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5009 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5010 = bits(_T_5009, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5011 = mux(_T_5010, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5012 = and(_T_5011, way_status_out[90]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5013 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5014 = bits(_T_5013, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5015 = mux(_T_5014, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5016 = and(_T_5015, way_status_out[91]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5017 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5018 = bits(_T_5017, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5019 = mux(_T_5018, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5020 = and(_T_5019, way_status_out[92]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5021 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5022 = bits(_T_5021, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5023 = mux(_T_5022, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5024 = and(_T_5023, way_status_out[93]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5025 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5026 = bits(_T_5025, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5027 = mux(_T_5026, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5028 = and(_T_5027, way_status_out[94]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5029 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5030 = bits(_T_5029, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5031 = mux(_T_5030, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5032 = and(_T_5031, way_status_out[95]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5033 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5034 = bits(_T_5033, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5035 = mux(_T_5034, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5036 = and(_T_5035, way_status_out[96]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5037 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5038 = bits(_T_5037, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5039 = mux(_T_5038, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5040 = and(_T_5039, way_status_out[97]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5041 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5042 = bits(_T_5041, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5043 = mux(_T_5042, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5044 = and(_T_5043, way_status_out[98]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5045 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5046 = bits(_T_5045, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5047 = mux(_T_5046, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5048 = and(_T_5047, way_status_out[99]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5049 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5050 = bits(_T_5049, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5051 = mux(_T_5050, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5052 = and(_T_5051, way_status_out[100]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5053 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5054 = bits(_T_5053, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5055 = mux(_T_5054, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5056 = and(_T_5055, way_status_out[101]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5057 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5058 = bits(_T_5057, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5059 = mux(_T_5058, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5060 = and(_T_5059, way_status_out[102]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5061 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5062 = bits(_T_5061, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5063 = mux(_T_5062, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5064 = and(_T_5063, way_status_out[103]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5065 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5066 = bits(_T_5065, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5067 = mux(_T_5066, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5068 = and(_T_5067, way_status_out[104]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5069 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5070 = bits(_T_5069, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5071 = mux(_T_5070, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5072 = and(_T_5071, way_status_out[105]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5073 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5074 = bits(_T_5073, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5075 = mux(_T_5074, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5076 = and(_T_5075, way_status_out[106]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5077 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5078 = bits(_T_5077, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5079 = mux(_T_5078, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5080 = and(_T_5079, way_status_out[107]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5081 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5082 = bits(_T_5081, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5083 = mux(_T_5082, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5084 = and(_T_5083, way_status_out[108]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5085 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5086 = bits(_T_5085, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5087 = mux(_T_5086, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5088 = and(_T_5087, way_status_out[109]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5089 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5090 = bits(_T_5089, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5091 = mux(_T_5090, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5092 = and(_T_5091, way_status_out[110]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5093 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5094 = bits(_T_5093, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5095 = mux(_T_5094, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5096 = and(_T_5095, way_status_out[111]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5097 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5098 = bits(_T_5097, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5099 = mux(_T_5098, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5100 = and(_T_5099, way_status_out[112]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5101 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5102 = bits(_T_5101, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5103 = mux(_T_5102, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5104 = and(_T_5103, way_status_out[113]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5105 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5106 = bits(_T_5105, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5107 = mux(_T_5106, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5108 = and(_T_5107, way_status_out[114]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5109 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5110 = bits(_T_5109, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5111 = mux(_T_5110, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5112 = and(_T_5111, way_status_out[115]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5113 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5114 = bits(_T_5113, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5115 = mux(_T_5114, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5116 = and(_T_5115, way_status_out[116]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5117 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5118 = bits(_T_5117, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5119 = mux(_T_5118, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5120 = and(_T_5119, way_status_out[117]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5121 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5122 = bits(_T_5121, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5123 = mux(_T_5122, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5124 = and(_T_5123, way_status_out[118]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5125 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5126 = bits(_T_5125, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5127 = mux(_T_5126, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5128 = and(_T_5127, way_status_out[119]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5129 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5130 = bits(_T_5129, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5131 = mux(_T_5130, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5132 = and(_T_5131, way_status_out[120]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5133 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5134 = bits(_T_5133, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5135 = mux(_T_5134, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5136 = and(_T_5135, way_status_out[121]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5137 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5138 = bits(_T_5137, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5139 = mux(_T_5138, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5140 = and(_T_5139, way_status_out[122]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5141 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5142 = bits(_T_5141, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5143 = mux(_T_5142, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5144 = and(_T_5143, way_status_out[123]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5145 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5146 = bits(_T_5145, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5147 = mux(_T_5146, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5148 = and(_T_5147, way_status_out[124]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5149 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5150 = bits(_T_5149, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5151 = mux(_T_5150, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5152 = and(_T_5151, way_status_out[125]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5153 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5154 = bits(_T_5153, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5155 = mux(_T_5154, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5156 = and(_T_5155, way_status_out[126]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5157 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 727:121]
|
|
node _T_5158 = bits(_T_5157, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_5159 = mux(_T_5158, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_5160 = and(_T_5159, way_status_out[127]) @[el2_ifu_mem_ctl.scala 727:130]
|
|
node _T_5161 = cat(_T_5160, _T_5156) @[Cat.scala 29:58]
|
|
node _T_5162 = cat(_T_5161, _T_5152) @[Cat.scala 29:58]
|
|
node _T_5163 = cat(_T_5162, _T_5148) @[Cat.scala 29:58]
|
|
node _T_5164 = cat(_T_5163, _T_5144) @[Cat.scala 29:58]
|
|
node _T_5165 = cat(_T_5164, _T_5140) @[Cat.scala 29:58]
|
|
node _T_5166 = cat(_T_5165, _T_5136) @[Cat.scala 29:58]
|
|
node _T_5167 = cat(_T_5166, _T_5132) @[Cat.scala 29:58]
|
|
node _T_5168 = cat(_T_5167, _T_5128) @[Cat.scala 29:58]
|
|
node _T_5169 = cat(_T_5168, _T_5124) @[Cat.scala 29:58]
|
|
node _T_5170 = cat(_T_5169, _T_5120) @[Cat.scala 29:58]
|
|
node _T_5171 = cat(_T_5170, _T_5116) @[Cat.scala 29:58]
|
|
node _T_5172 = cat(_T_5171, _T_5112) @[Cat.scala 29:58]
|
|
node _T_5173 = cat(_T_5172, _T_5108) @[Cat.scala 29:58]
|
|
node _T_5174 = cat(_T_5173, _T_5104) @[Cat.scala 29:58]
|
|
node _T_5175 = cat(_T_5174, _T_5100) @[Cat.scala 29:58]
|
|
node _T_5176 = cat(_T_5175, _T_5096) @[Cat.scala 29:58]
|
|
node _T_5177 = cat(_T_5176, _T_5092) @[Cat.scala 29:58]
|
|
node _T_5178 = cat(_T_5177, _T_5088) @[Cat.scala 29:58]
|
|
node _T_5179 = cat(_T_5178, _T_5084) @[Cat.scala 29:58]
|
|
node _T_5180 = cat(_T_5179, _T_5080) @[Cat.scala 29:58]
|
|
node _T_5181 = cat(_T_5180, _T_5076) @[Cat.scala 29:58]
|
|
node _T_5182 = cat(_T_5181, _T_5072) @[Cat.scala 29:58]
|
|
node _T_5183 = cat(_T_5182, _T_5068) @[Cat.scala 29:58]
|
|
node _T_5184 = cat(_T_5183, _T_5064) @[Cat.scala 29:58]
|
|
node _T_5185 = cat(_T_5184, _T_5060) @[Cat.scala 29:58]
|
|
node _T_5186 = cat(_T_5185, _T_5056) @[Cat.scala 29:58]
|
|
node _T_5187 = cat(_T_5186, _T_5052) @[Cat.scala 29:58]
|
|
node _T_5188 = cat(_T_5187, _T_5048) @[Cat.scala 29:58]
|
|
node _T_5189 = cat(_T_5188, _T_5044) @[Cat.scala 29:58]
|
|
node _T_5190 = cat(_T_5189, _T_5040) @[Cat.scala 29:58]
|
|
node _T_5191 = cat(_T_5190, _T_5036) @[Cat.scala 29:58]
|
|
node _T_5192 = cat(_T_5191, _T_5032) @[Cat.scala 29:58]
|
|
node _T_5193 = cat(_T_5192, _T_5028) @[Cat.scala 29:58]
|
|
node _T_5194 = cat(_T_5193, _T_5024) @[Cat.scala 29:58]
|
|
node _T_5195 = cat(_T_5194, _T_5020) @[Cat.scala 29:58]
|
|
node _T_5196 = cat(_T_5195, _T_5016) @[Cat.scala 29:58]
|
|
node _T_5197 = cat(_T_5196, _T_5012) @[Cat.scala 29:58]
|
|
node _T_5198 = cat(_T_5197, _T_5008) @[Cat.scala 29:58]
|
|
node _T_5199 = cat(_T_5198, _T_5004) @[Cat.scala 29:58]
|
|
node _T_5200 = cat(_T_5199, _T_5000) @[Cat.scala 29:58]
|
|
node _T_5201 = cat(_T_5200, _T_4996) @[Cat.scala 29:58]
|
|
node _T_5202 = cat(_T_5201, _T_4992) @[Cat.scala 29:58]
|
|
node _T_5203 = cat(_T_5202, _T_4988) @[Cat.scala 29:58]
|
|
node _T_5204 = cat(_T_5203, _T_4984) @[Cat.scala 29:58]
|
|
node _T_5205 = cat(_T_5204, _T_4980) @[Cat.scala 29:58]
|
|
node _T_5206 = cat(_T_5205, _T_4976) @[Cat.scala 29:58]
|
|
node _T_5207 = cat(_T_5206, _T_4972) @[Cat.scala 29:58]
|
|
node _T_5208 = cat(_T_5207, _T_4968) @[Cat.scala 29:58]
|
|
node _T_5209 = cat(_T_5208, _T_4964) @[Cat.scala 29:58]
|
|
node _T_5210 = cat(_T_5209, _T_4960) @[Cat.scala 29:58]
|
|
node _T_5211 = cat(_T_5210, _T_4956) @[Cat.scala 29:58]
|
|
node _T_5212 = cat(_T_5211, _T_4952) @[Cat.scala 29:58]
|
|
node _T_5213 = cat(_T_5212, _T_4948) @[Cat.scala 29:58]
|
|
node _T_5214 = cat(_T_5213, _T_4944) @[Cat.scala 29:58]
|
|
node _T_5215 = cat(_T_5214, _T_4940) @[Cat.scala 29:58]
|
|
node _T_5216 = cat(_T_5215, _T_4936) @[Cat.scala 29:58]
|
|
node _T_5217 = cat(_T_5216, _T_4932) @[Cat.scala 29:58]
|
|
node _T_5218 = cat(_T_5217, _T_4928) @[Cat.scala 29:58]
|
|
node _T_5219 = cat(_T_5218, _T_4924) @[Cat.scala 29:58]
|
|
node _T_5220 = cat(_T_5219, _T_4920) @[Cat.scala 29:58]
|
|
node _T_5221 = cat(_T_5220, _T_4916) @[Cat.scala 29:58]
|
|
node _T_5222 = cat(_T_5221, _T_4912) @[Cat.scala 29:58]
|
|
node _T_5223 = cat(_T_5222, _T_4908) @[Cat.scala 29:58]
|
|
node _T_5224 = cat(_T_5223, _T_4904) @[Cat.scala 29:58]
|
|
node _T_5225 = cat(_T_5224, _T_4900) @[Cat.scala 29:58]
|
|
node _T_5226 = cat(_T_5225, _T_4896) @[Cat.scala 29:58]
|
|
node _T_5227 = cat(_T_5226, _T_4892) @[Cat.scala 29:58]
|
|
node _T_5228 = cat(_T_5227, _T_4888) @[Cat.scala 29:58]
|
|
node _T_5229 = cat(_T_5228, _T_4884) @[Cat.scala 29:58]
|
|
node _T_5230 = cat(_T_5229, _T_4880) @[Cat.scala 29:58]
|
|
node _T_5231 = cat(_T_5230, _T_4876) @[Cat.scala 29:58]
|
|
node _T_5232 = cat(_T_5231, _T_4872) @[Cat.scala 29:58]
|
|
node _T_5233 = cat(_T_5232, _T_4868) @[Cat.scala 29:58]
|
|
node _T_5234 = cat(_T_5233, _T_4864) @[Cat.scala 29:58]
|
|
node _T_5235 = cat(_T_5234, _T_4860) @[Cat.scala 29:58]
|
|
node _T_5236 = cat(_T_5235, _T_4856) @[Cat.scala 29:58]
|
|
node _T_5237 = cat(_T_5236, _T_4852) @[Cat.scala 29:58]
|
|
node _T_5238 = cat(_T_5237, _T_4848) @[Cat.scala 29:58]
|
|
node _T_5239 = cat(_T_5238, _T_4844) @[Cat.scala 29:58]
|
|
node _T_5240 = cat(_T_5239, _T_4840) @[Cat.scala 29:58]
|
|
node _T_5241 = cat(_T_5240, _T_4836) @[Cat.scala 29:58]
|
|
node _T_5242 = cat(_T_5241, _T_4832) @[Cat.scala 29:58]
|
|
node _T_5243 = cat(_T_5242, _T_4828) @[Cat.scala 29:58]
|
|
node _T_5244 = cat(_T_5243, _T_4824) @[Cat.scala 29:58]
|
|
node _T_5245 = cat(_T_5244, _T_4820) @[Cat.scala 29:58]
|
|
node _T_5246 = cat(_T_5245, _T_4816) @[Cat.scala 29:58]
|
|
node _T_5247 = cat(_T_5246, _T_4812) @[Cat.scala 29:58]
|
|
node _T_5248 = cat(_T_5247, _T_4808) @[Cat.scala 29:58]
|
|
node _T_5249 = cat(_T_5248, _T_4804) @[Cat.scala 29:58]
|
|
node _T_5250 = cat(_T_5249, _T_4800) @[Cat.scala 29:58]
|
|
node _T_5251 = cat(_T_5250, _T_4796) @[Cat.scala 29:58]
|
|
node _T_5252 = cat(_T_5251, _T_4792) @[Cat.scala 29:58]
|
|
node _T_5253 = cat(_T_5252, _T_4788) @[Cat.scala 29:58]
|
|
node _T_5254 = cat(_T_5253, _T_4784) @[Cat.scala 29:58]
|
|
node _T_5255 = cat(_T_5254, _T_4780) @[Cat.scala 29:58]
|
|
node _T_5256 = cat(_T_5255, _T_4776) @[Cat.scala 29:58]
|
|
node _T_5257 = cat(_T_5256, _T_4772) @[Cat.scala 29:58]
|
|
node _T_5258 = cat(_T_5257, _T_4768) @[Cat.scala 29:58]
|
|
node _T_5259 = cat(_T_5258, _T_4764) @[Cat.scala 29:58]
|
|
node _T_5260 = cat(_T_5259, _T_4760) @[Cat.scala 29:58]
|
|
node _T_5261 = cat(_T_5260, _T_4756) @[Cat.scala 29:58]
|
|
node _T_5262 = cat(_T_5261, _T_4752) @[Cat.scala 29:58]
|
|
node _T_5263 = cat(_T_5262, _T_4748) @[Cat.scala 29:58]
|
|
node _T_5264 = cat(_T_5263, _T_4744) @[Cat.scala 29:58]
|
|
node _T_5265 = cat(_T_5264, _T_4740) @[Cat.scala 29:58]
|
|
node _T_5266 = cat(_T_5265, _T_4736) @[Cat.scala 29:58]
|
|
node _T_5267 = cat(_T_5266, _T_4732) @[Cat.scala 29:58]
|
|
node _T_5268 = cat(_T_5267, _T_4728) @[Cat.scala 29:58]
|
|
node _T_5269 = cat(_T_5268, _T_4724) @[Cat.scala 29:58]
|
|
node _T_5270 = cat(_T_5269, _T_4720) @[Cat.scala 29:58]
|
|
node _T_5271 = cat(_T_5270, _T_4716) @[Cat.scala 29:58]
|
|
node _T_5272 = cat(_T_5271, _T_4712) @[Cat.scala 29:58]
|
|
node _T_5273 = cat(_T_5272, _T_4708) @[Cat.scala 29:58]
|
|
node _T_5274 = cat(_T_5273, _T_4704) @[Cat.scala 29:58]
|
|
node _T_5275 = cat(_T_5274, _T_4700) @[Cat.scala 29:58]
|
|
node _T_5276 = cat(_T_5275, _T_4696) @[Cat.scala 29:58]
|
|
node _T_5277 = cat(_T_5276, _T_4692) @[Cat.scala 29:58]
|
|
node _T_5278 = cat(_T_5277, _T_4688) @[Cat.scala 29:58]
|
|
node _T_5279 = cat(_T_5278, _T_4684) @[Cat.scala 29:58]
|
|
node _T_5280 = cat(_T_5279, _T_4680) @[Cat.scala 29:58]
|
|
node _T_5281 = cat(_T_5280, _T_4676) @[Cat.scala 29:58]
|
|
node _T_5282 = cat(_T_5281, _T_4672) @[Cat.scala 29:58]
|
|
node _T_5283 = cat(_T_5282, _T_4668) @[Cat.scala 29:58]
|
|
node _T_5284 = cat(_T_5283, _T_4664) @[Cat.scala 29:58]
|
|
node _T_5285 = cat(_T_5284, _T_4660) @[Cat.scala 29:58]
|
|
node _T_5286 = cat(_T_5285, _T_4656) @[Cat.scala 29:58]
|
|
node _T_5287 = cat(_T_5286, _T_4652) @[Cat.scala 29:58]
|
|
way_status <= _T_5287 @[el2_ifu_mem_ctl.scala 727:16]
|
|
node _T_5288 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 728:61]
|
|
node _T_5289 = and(_T_5288, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 728:82]
|
|
node _T_5290 = bits(io.ic_debug_addr, 9, 3) @[el2_ifu_mem_ctl.scala 729:23]
|
|
node _T_5291 = bits(ifu_ic_rw_int_addr, 11, 5) @[el2_ifu_mem_ctl.scala 729:89]
|
|
node ifu_ic_rw_int_addr_w_debug = mux(_T_5289, _T_5290, _T_5291) @[el2_ifu_mem_ctl.scala 728:41]
|
|
reg _T_5292 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 731:14]
|
|
_T_5292 <= ifu_ic_rw_int_addr_w_debug @[el2_ifu_mem_ctl.scala 731:14]
|
|
ifu_ic_rw_int_addr_ff <= _T_5292 @[el2_ifu_mem_ctl.scala 730:27]
|
|
wire ifu_tag_wren : UInt<2>
|
|
ifu_tag_wren <= UInt<1>("h00")
|
|
wire ic_debug_tag_wr_en : UInt<2>
|
|
ic_debug_tag_wr_en <= UInt<1>("h00")
|
|
node ifu_tag_wren_w_debug = or(ifu_tag_wren, ic_debug_tag_wr_en) @[el2_ifu_mem_ctl.scala 735:45]
|
|
reg ifu_tag_wren_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 737:14]
|
|
ifu_tag_wren_ff <= ifu_tag_wren_w_debug @[el2_ifu_mem_ctl.scala 737:14]
|
|
node _T_5293 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 739:50]
|
|
node _T_5294 = bits(io.ic_debug_wr_data, 0, 0) @[el2_ifu_mem_ctl.scala 739:94]
|
|
node ic_valid_w_debug = mux(_T_5293, _T_5294, ic_valid) @[el2_ifu_mem_ctl.scala 739:31]
|
|
reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 741:14]
|
|
ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 741:14]
|
|
node _T_5295 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 745:35]
|
|
node _T_5296 = eq(_T_5295, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 745:78]
|
|
node _T_5297 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 745:104]
|
|
node _T_5298 = and(_T_5296, _T_5297) @[el2_ifu_mem_ctl.scala 745:87]
|
|
node _T_5299 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 746:27]
|
|
node _T_5300 = eq(_T_5299, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 746:70]
|
|
node _T_5301 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 746:97]
|
|
node _T_5302 = and(_T_5300, _T_5301) @[el2_ifu_mem_ctl.scala 746:79]
|
|
node _T_5303 = or(_T_5298, _T_5302) @[el2_ifu_mem_ctl.scala 745:109]
|
|
node _T_5304 = or(_T_5303, reset_all_tags) @[el2_ifu_mem_ctl.scala 746:102]
|
|
node _T_5305 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 745:35]
|
|
node _T_5306 = eq(_T_5305, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 745:78]
|
|
node _T_5307 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 745:104]
|
|
node _T_5308 = and(_T_5306, _T_5307) @[el2_ifu_mem_ctl.scala 745:87]
|
|
node _T_5309 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 746:27]
|
|
node _T_5310 = eq(_T_5309, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 746:70]
|
|
node _T_5311 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 746:97]
|
|
node _T_5312 = and(_T_5310, _T_5311) @[el2_ifu_mem_ctl.scala 746:79]
|
|
node _T_5313 = or(_T_5308, _T_5312) @[el2_ifu_mem_ctl.scala 745:109]
|
|
node _T_5314 = or(_T_5313, reset_all_tags) @[el2_ifu_mem_ctl.scala 746:102]
|
|
node tag_valid_clken_0 = cat(_T_5314, _T_5304) @[Cat.scala 29:58]
|
|
node _T_5315 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 745:35]
|
|
node _T_5316 = eq(_T_5315, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 745:78]
|
|
node _T_5317 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 745:104]
|
|
node _T_5318 = and(_T_5316, _T_5317) @[el2_ifu_mem_ctl.scala 745:87]
|
|
node _T_5319 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 746:27]
|
|
node _T_5320 = eq(_T_5319, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 746:70]
|
|
node _T_5321 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 746:97]
|
|
node _T_5322 = and(_T_5320, _T_5321) @[el2_ifu_mem_ctl.scala 746:79]
|
|
node _T_5323 = or(_T_5318, _T_5322) @[el2_ifu_mem_ctl.scala 745:109]
|
|
node _T_5324 = or(_T_5323, reset_all_tags) @[el2_ifu_mem_ctl.scala 746:102]
|
|
node _T_5325 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 745:35]
|
|
node _T_5326 = eq(_T_5325, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 745:78]
|
|
node _T_5327 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 745:104]
|
|
node _T_5328 = and(_T_5326, _T_5327) @[el2_ifu_mem_ctl.scala 745:87]
|
|
node _T_5329 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 746:27]
|
|
node _T_5330 = eq(_T_5329, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 746:70]
|
|
node _T_5331 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 746:97]
|
|
node _T_5332 = and(_T_5330, _T_5331) @[el2_ifu_mem_ctl.scala 746:79]
|
|
node _T_5333 = or(_T_5328, _T_5332) @[el2_ifu_mem_ctl.scala 745:109]
|
|
node _T_5334 = or(_T_5333, reset_all_tags) @[el2_ifu_mem_ctl.scala 746:102]
|
|
node tag_valid_clken_1 = cat(_T_5334, _T_5324) @[Cat.scala 29:58]
|
|
node _T_5335 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 745:35]
|
|
node _T_5336 = eq(_T_5335, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 745:78]
|
|
node _T_5337 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 745:104]
|
|
node _T_5338 = and(_T_5336, _T_5337) @[el2_ifu_mem_ctl.scala 745:87]
|
|
node _T_5339 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 746:27]
|
|
node _T_5340 = eq(_T_5339, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 746:70]
|
|
node _T_5341 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 746:97]
|
|
node _T_5342 = and(_T_5340, _T_5341) @[el2_ifu_mem_ctl.scala 746:79]
|
|
node _T_5343 = or(_T_5338, _T_5342) @[el2_ifu_mem_ctl.scala 745:109]
|
|
node _T_5344 = or(_T_5343, reset_all_tags) @[el2_ifu_mem_ctl.scala 746:102]
|
|
node _T_5345 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 745:35]
|
|
node _T_5346 = eq(_T_5345, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 745:78]
|
|
node _T_5347 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 745:104]
|
|
node _T_5348 = and(_T_5346, _T_5347) @[el2_ifu_mem_ctl.scala 745:87]
|
|
node _T_5349 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 746:27]
|
|
node _T_5350 = eq(_T_5349, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 746:70]
|
|
node _T_5351 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 746:97]
|
|
node _T_5352 = and(_T_5350, _T_5351) @[el2_ifu_mem_ctl.scala 746:79]
|
|
node _T_5353 = or(_T_5348, _T_5352) @[el2_ifu_mem_ctl.scala 745:109]
|
|
node _T_5354 = or(_T_5353, reset_all_tags) @[el2_ifu_mem_ctl.scala 746:102]
|
|
node tag_valid_clken_2 = cat(_T_5354, _T_5344) @[Cat.scala 29:58]
|
|
node _T_5355 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 745:35]
|
|
node _T_5356 = eq(_T_5355, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 745:78]
|
|
node _T_5357 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 745:104]
|
|
node _T_5358 = and(_T_5356, _T_5357) @[el2_ifu_mem_ctl.scala 745:87]
|
|
node _T_5359 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 746:27]
|
|
node _T_5360 = eq(_T_5359, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 746:70]
|
|
node _T_5361 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 746:97]
|
|
node _T_5362 = and(_T_5360, _T_5361) @[el2_ifu_mem_ctl.scala 746:79]
|
|
node _T_5363 = or(_T_5358, _T_5362) @[el2_ifu_mem_ctl.scala 745:109]
|
|
node _T_5364 = or(_T_5363, reset_all_tags) @[el2_ifu_mem_ctl.scala 746:102]
|
|
node _T_5365 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 745:35]
|
|
node _T_5366 = eq(_T_5365, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 745:78]
|
|
node _T_5367 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 745:104]
|
|
node _T_5368 = and(_T_5366, _T_5367) @[el2_ifu_mem_ctl.scala 745:87]
|
|
node _T_5369 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 746:27]
|
|
node _T_5370 = eq(_T_5369, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 746:70]
|
|
node _T_5371 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 746:97]
|
|
node _T_5372 = and(_T_5370, _T_5371) @[el2_ifu_mem_ctl.scala 746:79]
|
|
node _T_5373 = or(_T_5368, _T_5372) @[el2_ifu_mem_ctl.scala 745:109]
|
|
node _T_5374 = or(_T_5373, reset_all_tags) @[el2_ifu_mem_ctl.scala 746:102]
|
|
node tag_valid_clken_3 = cat(_T_5374, _T_5364) @[Cat.scala 29:58]
|
|
wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 749:32]
|
|
node _T_5375 = cat(ic_tag_valid_out[1][127], ic_tag_valid_out[1][126]) @[Cat.scala 29:58]
|
|
node _T_5376 = cat(_T_5375, ic_tag_valid_out[1][125]) @[Cat.scala 29:58]
|
|
node _T_5377 = cat(_T_5376, ic_tag_valid_out[1][124]) @[Cat.scala 29:58]
|
|
node _T_5378 = cat(_T_5377, ic_tag_valid_out[1][123]) @[Cat.scala 29:58]
|
|
node _T_5379 = cat(_T_5378, ic_tag_valid_out[1][122]) @[Cat.scala 29:58]
|
|
node _T_5380 = cat(_T_5379, ic_tag_valid_out[1][121]) @[Cat.scala 29:58]
|
|
node _T_5381 = cat(_T_5380, ic_tag_valid_out[1][120]) @[Cat.scala 29:58]
|
|
node _T_5382 = cat(_T_5381, ic_tag_valid_out[1][119]) @[Cat.scala 29:58]
|
|
node _T_5383 = cat(_T_5382, ic_tag_valid_out[1][118]) @[Cat.scala 29:58]
|
|
node _T_5384 = cat(_T_5383, ic_tag_valid_out[1][117]) @[Cat.scala 29:58]
|
|
node _T_5385 = cat(_T_5384, ic_tag_valid_out[1][116]) @[Cat.scala 29:58]
|
|
node _T_5386 = cat(_T_5385, ic_tag_valid_out[1][115]) @[Cat.scala 29:58]
|
|
node _T_5387 = cat(_T_5386, ic_tag_valid_out[1][114]) @[Cat.scala 29:58]
|
|
node _T_5388 = cat(_T_5387, ic_tag_valid_out[1][113]) @[Cat.scala 29:58]
|
|
node _T_5389 = cat(_T_5388, ic_tag_valid_out[1][112]) @[Cat.scala 29:58]
|
|
node _T_5390 = cat(_T_5389, ic_tag_valid_out[1][111]) @[Cat.scala 29:58]
|
|
node _T_5391 = cat(_T_5390, ic_tag_valid_out[1][110]) @[Cat.scala 29:58]
|
|
node _T_5392 = cat(_T_5391, ic_tag_valid_out[1][109]) @[Cat.scala 29:58]
|
|
node _T_5393 = cat(_T_5392, ic_tag_valid_out[1][108]) @[Cat.scala 29:58]
|
|
node _T_5394 = cat(_T_5393, ic_tag_valid_out[1][107]) @[Cat.scala 29:58]
|
|
node _T_5395 = cat(_T_5394, ic_tag_valid_out[1][106]) @[Cat.scala 29:58]
|
|
node _T_5396 = cat(_T_5395, ic_tag_valid_out[1][105]) @[Cat.scala 29:58]
|
|
node _T_5397 = cat(_T_5396, ic_tag_valid_out[1][104]) @[Cat.scala 29:58]
|
|
node _T_5398 = cat(_T_5397, ic_tag_valid_out[1][103]) @[Cat.scala 29:58]
|
|
node _T_5399 = cat(_T_5398, ic_tag_valid_out[1][102]) @[Cat.scala 29:58]
|
|
node _T_5400 = cat(_T_5399, ic_tag_valid_out[1][101]) @[Cat.scala 29:58]
|
|
node _T_5401 = cat(_T_5400, ic_tag_valid_out[1][100]) @[Cat.scala 29:58]
|
|
node _T_5402 = cat(_T_5401, ic_tag_valid_out[1][99]) @[Cat.scala 29:58]
|
|
node _T_5403 = cat(_T_5402, ic_tag_valid_out[1][98]) @[Cat.scala 29:58]
|
|
node _T_5404 = cat(_T_5403, ic_tag_valid_out[1][97]) @[Cat.scala 29:58]
|
|
node _T_5405 = cat(_T_5404, ic_tag_valid_out[1][96]) @[Cat.scala 29:58]
|
|
node _T_5406 = cat(_T_5405, ic_tag_valid_out[1][95]) @[Cat.scala 29:58]
|
|
node _T_5407 = cat(_T_5406, ic_tag_valid_out[1][94]) @[Cat.scala 29:58]
|
|
node _T_5408 = cat(_T_5407, ic_tag_valid_out[1][93]) @[Cat.scala 29:58]
|
|
node _T_5409 = cat(_T_5408, ic_tag_valid_out[1][92]) @[Cat.scala 29:58]
|
|
node _T_5410 = cat(_T_5409, ic_tag_valid_out[1][91]) @[Cat.scala 29:58]
|
|
node _T_5411 = cat(_T_5410, ic_tag_valid_out[1][90]) @[Cat.scala 29:58]
|
|
node _T_5412 = cat(_T_5411, ic_tag_valid_out[1][89]) @[Cat.scala 29:58]
|
|
node _T_5413 = cat(_T_5412, ic_tag_valid_out[1][88]) @[Cat.scala 29:58]
|
|
node _T_5414 = cat(_T_5413, ic_tag_valid_out[1][87]) @[Cat.scala 29:58]
|
|
node _T_5415 = cat(_T_5414, ic_tag_valid_out[1][86]) @[Cat.scala 29:58]
|
|
node _T_5416 = cat(_T_5415, ic_tag_valid_out[1][85]) @[Cat.scala 29:58]
|
|
node _T_5417 = cat(_T_5416, ic_tag_valid_out[1][84]) @[Cat.scala 29:58]
|
|
node _T_5418 = cat(_T_5417, ic_tag_valid_out[1][83]) @[Cat.scala 29:58]
|
|
node _T_5419 = cat(_T_5418, ic_tag_valid_out[1][82]) @[Cat.scala 29:58]
|
|
node _T_5420 = cat(_T_5419, ic_tag_valid_out[1][81]) @[Cat.scala 29:58]
|
|
node _T_5421 = cat(_T_5420, ic_tag_valid_out[1][80]) @[Cat.scala 29:58]
|
|
node _T_5422 = cat(_T_5421, ic_tag_valid_out[1][79]) @[Cat.scala 29:58]
|
|
node _T_5423 = cat(_T_5422, ic_tag_valid_out[1][78]) @[Cat.scala 29:58]
|
|
node _T_5424 = cat(_T_5423, ic_tag_valid_out[1][77]) @[Cat.scala 29:58]
|
|
node _T_5425 = cat(_T_5424, ic_tag_valid_out[1][76]) @[Cat.scala 29:58]
|
|
node _T_5426 = cat(_T_5425, ic_tag_valid_out[1][75]) @[Cat.scala 29:58]
|
|
node _T_5427 = cat(_T_5426, ic_tag_valid_out[1][74]) @[Cat.scala 29:58]
|
|
node _T_5428 = cat(_T_5427, ic_tag_valid_out[1][73]) @[Cat.scala 29:58]
|
|
node _T_5429 = cat(_T_5428, ic_tag_valid_out[1][72]) @[Cat.scala 29:58]
|
|
node _T_5430 = cat(_T_5429, ic_tag_valid_out[1][71]) @[Cat.scala 29:58]
|
|
node _T_5431 = cat(_T_5430, ic_tag_valid_out[1][70]) @[Cat.scala 29:58]
|
|
node _T_5432 = cat(_T_5431, ic_tag_valid_out[1][69]) @[Cat.scala 29:58]
|
|
node _T_5433 = cat(_T_5432, ic_tag_valid_out[1][68]) @[Cat.scala 29:58]
|
|
node _T_5434 = cat(_T_5433, ic_tag_valid_out[1][67]) @[Cat.scala 29:58]
|
|
node _T_5435 = cat(_T_5434, ic_tag_valid_out[1][66]) @[Cat.scala 29:58]
|
|
node _T_5436 = cat(_T_5435, ic_tag_valid_out[1][65]) @[Cat.scala 29:58]
|
|
node _T_5437 = cat(_T_5436, ic_tag_valid_out[1][64]) @[Cat.scala 29:58]
|
|
node _T_5438 = cat(_T_5437, ic_tag_valid_out[1][63]) @[Cat.scala 29:58]
|
|
node _T_5439 = cat(_T_5438, ic_tag_valid_out[1][62]) @[Cat.scala 29:58]
|
|
node _T_5440 = cat(_T_5439, ic_tag_valid_out[1][61]) @[Cat.scala 29:58]
|
|
node _T_5441 = cat(_T_5440, ic_tag_valid_out[1][60]) @[Cat.scala 29:58]
|
|
node _T_5442 = cat(_T_5441, ic_tag_valid_out[1][59]) @[Cat.scala 29:58]
|
|
node _T_5443 = cat(_T_5442, ic_tag_valid_out[1][58]) @[Cat.scala 29:58]
|
|
node _T_5444 = cat(_T_5443, ic_tag_valid_out[1][57]) @[Cat.scala 29:58]
|
|
node _T_5445 = cat(_T_5444, ic_tag_valid_out[1][56]) @[Cat.scala 29:58]
|
|
node _T_5446 = cat(_T_5445, ic_tag_valid_out[1][55]) @[Cat.scala 29:58]
|
|
node _T_5447 = cat(_T_5446, ic_tag_valid_out[1][54]) @[Cat.scala 29:58]
|
|
node _T_5448 = cat(_T_5447, ic_tag_valid_out[1][53]) @[Cat.scala 29:58]
|
|
node _T_5449 = cat(_T_5448, ic_tag_valid_out[1][52]) @[Cat.scala 29:58]
|
|
node _T_5450 = cat(_T_5449, ic_tag_valid_out[1][51]) @[Cat.scala 29:58]
|
|
node _T_5451 = cat(_T_5450, ic_tag_valid_out[1][50]) @[Cat.scala 29:58]
|
|
node _T_5452 = cat(_T_5451, ic_tag_valid_out[1][49]) @[Cat.scala 29:58]
|
|
node _T_5453 = cat(_T_5452, ic_tag_valid_out[1][48]) @[Cat.scala 29:58]
|
|
node _T_5454 = cat(_T_5453, ic_tag_valid_out[1][47]) @[Cat.scala 29:58]
|
|
node _T_5455 = cat(_T_5454, ic_tag_valid_out[1][46]) @[Cat.scala 29:58]
|
|
node _T_5456 = cat(_T_5455, ic_tag_valid_out[1][45]) @[Cat.scala 29:58]
|
|
node _T_5457 = cat(_T_5456, ic_tag_valid_out[1][44]) @[Cat.scala 29:58]
|
|
node _T_5458 = cat(_T_5457, ic_tag_valid_out[1][43]) @[Cat.scala 29:58]
|
|
node _T_5459 = cat(_T_5458, ic_tag_valid_out[1][42]) @[Cat.scala 29:58]
|
|
node _T_5460 = cat(_T_5459, ic_tag_valid_out[1][41]) @[Cat.scala 29:58]
|
|
node _T_5461 = cat(_T_5460, ic_tag_valid_out[1][40]) @[Cat.scala 29:58]
|
|
node _T_5462 = cat(_T_5461, ic_tag_valid_out[1][39]) @[Cat.scala 29:58]
|
|
node _T_5463 = cat(_T_5462, ic_tag_valid_out[1][38]) @[Cat.scala 29:58]
|
|
node _T_5464 = cat(_T_5463, ic_tag_valid_out[1][37]) @[Cat.scala 29:58]
|
|
node _T_5465 = cat(_T_5464, ic_tag_valid_out[1][36]) @[Cat.scala 29:58]
|
|
node _T_5466 = cat(_T_5465, ic_tag_valid_out[1][35]) @[Cat.scala 29:58]
|
|
node _T_5467 = cat(_T_5466, ic_tag_valid_out[1][34]) @[Cat.scala 29:58]
|
|
node _T_5468 = cat(_T_5467, ic_tag_valid_out[1][33]) @[Cat.scala 29:58]
|
|
node _T_5469 = cat(_T_5468, ic_tag_valid_out[1][32]) @[Cat.scala 29:58]
|
|
node _T_5470 = cat(_T_5469, ic_tag_valid_out[1][31]) @[Cat.scala 29:58]
|
|
node _T_5471 = cat(_T_5470, ic_tag_valid_out[1][30]) @[Cat.scala 29:58]
|
|
node _T_5472 = cat(_T_5471, ic_tag_valid_out[1][29]) @[Cat.scala 29:58]
|
|
node _T_5473 = cat(_T_5472, ic_tag_valid_out[1][28]) @[Cat.scala 29:58]
|
|
node _T_5474 = cat(_T_5473, ic_tag_valid_out[1][27]) @[Cat.scala 29:58]
|
|
node _T_5475 = cat(_T_5474, ic_tag_valid_out[1][26]) @[Cat.scala 29:58]
|
|
node _T_5476 = cat(_T_5475, ic_tag_valid_out[1][25]) @[Cat.scala 29:58]
|
|
node _T_5477 = cat(_T_5476, ic_tag_valid_out[1][24]) @[Cat.scala 29:58]
|
|
node _T_5478 = cat(_T_5477, ic_tag_valid_out[1][23]) @[Cat.scala 29:58]
|
|
node _T_5479 = cat(_T_5478, ic_tag_valid_out[1][22]) @[Cat.scala 29:58]
|
|
node _T_5480 = cat(_T_5479, ic_tag_valid_out[1][21]) @[Cat.scala 29:58]
|
|
node _T_5481 = cat(_T_5480, ic_tag_valid_out[1][20]) @[Cat.scala 29:58]
|
|
node _T_5482 = cat(_T_5481, ic_tag_valid_out[1][19]) @[Cat.scala 29:58]
|
|
node _T_5483 = cat(_T_5482, ic_tag_valid_out[1][18]) @[Cat.scala 29:58]
|
|
node _T_5484 = cat(_T_5483, ic_tag_valid_out[1][17]) @[Cat.scala 29:58]
|
|
node _T_5485 = cat(_T_5484, ic_tag_valid_out[1][16]) @[Cat.scala 29:58]
|
|
node _T_5486 = cat(_T_5485, ic_tag_valid_out[1][15]) @[Cat.scala 29:58]
|
|
node _T_5487 = cat(_T_5486, ic_tag_valid_out[1][14]) @[Cat.scala 29:58]
|
|
node _T_5488 = cat(_T_5487, ic_tag_valid_out[1][13]) @[Cat.scala 29:58]
|
|
node _T_5489 = cat(_T_5488, ic_tag_valid_out[1][12]) @[Cat.scala 29:58]
|
|
node _T_5490 = cat(_T_5489, ic_tag_valid_out[1][11]) @[Cat.scala 29:58]
|
|
node _T_5491 = cat(_T_5490, ic_tag_valid_out[1][10]) @[Cat.scala 29:58]
|
|
node _T_5492 = cat(_T_5491, ic_tag_valid_out[1][9]) @[Cat.scala 29:58]
|
|
node _T_5493 = cat(_T_5492, ic_tag_valid_out[1][8]) @[Cat.scala 29:58]
|
|
node _T_5494 = cat(_T_5493, ic_tag_valid_out[1][7]) @[Cat.scala 29:58]
|
|
node _T_5495 = cat(_T_5494, ic_tag_valid_out[1][6]) @[Cat.scala 29:58]
|
|
node _T_5496 = cat(_T_5495, ic_tag_valid_out[1][5]) @[Cat.scala 29:58]
|
|
node _T_5497 = cat(_T_5496, ic_tag_valid_out[1][4]) @[Cat.scala 29:58]
|
|
node _T_5498 = cat(_T_5497, ic_tag_valid_out[1][3]) @[Cat.scala 29:58]
|
|
node _T_5499 = cat(_T_5498, ic_tag_valid_out[1][2]) @[Cat.scala 29:58]
|
|
node _T_5500 = cat(_T_5499, ic_tag_valid_out[1][1]) @[Cat.scala 29:58]
|
|
node _T_5501 = cat(_T_5500, ic_tag_valid_out[1][0]) @[Cat.scala 29:58]
|
|
node _T_5502 = cat(ic_tag_valid_out[0][127], ic_tag_valid_out[0][126]) @[Cat.scala 29:58]
|
|
node _T_5503 = cat(_T_5502, ic_tag_valid_out[0][125]) @[Cat.scala 29:58]
|
|
node _T_5504 = cat(_T_5503, ic_tag_valid_out[0][124]) @[Cat.scala 29:58]
|
|
node _T_5505 = cat(_T_5504, ic_tag_valid_out[0][123]) @[Cat.scala 29:58]
|
|
node _T_5506 = cat(_T_5505, ic_tag_valid_out[0][122]) @[Cat.scala 29:58]
|
|
node _T_5507 = cat(_T_5506, ic_tag_valid_out[0][121]) @[Cat.scala 29:58]
|
|
node _T_5508 = cat(_T_5507, ic_tag_valid_out[0][120]) @[Cat.scala 29:58]
|
|
node _T_5509 = cat(_T_5508, ic_tag_valid_out[0][119]) @[Cat.scala 29:58]
|
|
node _T_5510 = cat(_T_5509, ic_tag_valid_out[0][118]) @[Cat.scala 29:58]
|
|
node _T_5511 = cat(_T_5510, ic_tag_valid_out[0][117]) @[Cat.scala 29:58]
|
|
node _T_5512 = cat(_T_5511, ic_tag_valid_out[0][116]) @[Cat.scala 29:58]
|
|
node _T_5513 = cat(_T_5512, ic_tag_valid_out[0][115]) @[Cat.scala 29:58]
|
|
node _T_5514 = cat(_T_5513, ic_tag_valid_out[0][114]) @[Cat.scala 29:58]
|
|
node _T_5515 = cat(_T_5514, ic_tag_valid_out[0][113]) @[Cat.scala 29:58]
|
|
node _T_5516 = cat(_T_5515, ic_tag_valid_out[0][112]) @[Cat.scala 29:58]
|
|
node _T_5517 = cat(_T_5516, ic_tag_valid_out[0][111]) @[Cat.scala 29:58]
|
|
node _T_5518 = cat(_T_5517, ic_tag_valid_out[0][110]) @[Cat.scala 29:58]
|
|
node _T_5519 = cat(_T_5518, ic_tag_valid_out[0][109]) @[Cat.scala 29:58]
|
|
node _T_5520 = cat(_T_5519, ic_tag_valid_out[0][108]) @[Cat.scala 29:58]
|
|
node _T_5521 = cat(_T_5520, ic_tag_valid_out[0][107]) @[Cat.scala 29:58]
|
|
node _T_5522 = cat(_T_5521, ic_tag_valid_out[0][106]) @[Cat.scala 29:58]
|
|
node _T_5523 = cat(_T_5522, ic_tag_valid_out[0][105]) @[Cat.scala 29:58]
|
|
node _T_5524 = cat(_T_5523, ic_tag_valid_out[0][104]) @[Cat.scala 29:58]
|
|
node _T_5525 = cat(_T_5524, ic_tag_valid_out[0][103]) @[Cat.scala 29:58]
|
|
node _T_5526 = cat(_T_5525, ic_tag_valid_out[0][102]) @[Cat.scala 29:58]
|
|
node _T_5527 = cat(_T_5526, ic_tag_valid_out[0][101]) @[Cat.scala 29:58]
|
|
node _T_5528 = cat(_T_5527, ic_tag_valid_out[0][100]) @[Cat.scala 29:58]
|
|
node _T_5529 = cat(_T_5528, ic_tag_valid_out[0][99]) @[Cat.scala 29:58]
|
|
node _T_5530 = cat(_T_5529, ic_tag_valid_out[0][98]) @[Cat.scala 29:58]
|
|
node _T_5531 = cat(_T_5530, ic_tag_valid_out[0][97]) @[Cat.scala 29:58]
|
|
node _T_5532 = cat(_T_5531, ic_tag_valid_out[0][96]) @[Cat.scala 29:58]
|
|
node _T_5533 = cat(_T_5532, ic_tag_valid_out[0][95]) @[Cat.scala 29:58]
|
|
node _T_5534 = cat(_T_5533, ic_tag_valid_out[0][94]) @[Cat.scala 29:58]
|
|
node _T_5535 = cat(_T_5534, ic_tag_valid_out[0][93]) @[Cat.scala 29:58]
|
|
node _T_5536 = cat(_T_5535, ic_tag_valid_out[0][92]) @[Cat.scala 29:58]
|
|
node _T_5537 = cat(_T_5536, ic_tag_valid_out[0][91]) @[Cat.scala 29:58]
|
|
node _T_5538 = cat(_T_5537, ic_tag_valid_out[0][90]) @[Cat.scala 29:58]
|
|
node _T_5539 = cat(_T_5538, ic_tag_valid_out[0][89]) @[Cat.scala 29:58]
|
|
node _T_5540 = cat(_T_5539, ic_tag_valid_out[0][88]) @[Cat.scala 29:58]
|
|
node _T_5541 = cat(_T_5540, ic_tag_valid_out[0][87]) @[Cat.scala 29:58]
|
|
node _T_5542 = cat(_T_5541, ic_tag_valid_out[0][86]) @[Cat.scala 29:58]
|
|
node _T_5543 = cat(_T_5542, ic_tag_valid_out[0][85]) @[Cat.scala 29:58]
|
|
node _T_5544 = cat(_T_5543, ic_tag_valid_out[0][84]) @[Cat.scala 29:58]
|
|
node _T_5545 = cat(_T_5544, ic_tag_valid_out[0][83]) @[Cat.scala 29:58]
|
|
node _T_5546 = cat(_T_5545, ic_tag_valid_out[0][82]) @[Cat.scala 29:58]
|
|
node _T_5547 = cat(_T_5546, ic_tag_valid_out[0][81]) @[Cat.scala 29:58]
|
|
node _T_5548 = cat(_T_5547, ic_tag_valid_out[0][80]) @[Cat.scala 29:58]
|
|
node _T_5549 = cat(_T_5548, ic_tag_valid_out[0][79]) @[Cat.scala 29:58]
|
|
node _T_5550 = cat(_T_5549, ic_tag_valid_out[0][78]) @[Cat.scala 29:58]
|
|
node _T_5551 = cat(_T_5550, ic_tag_valid_out[0][77]) @[Cat.scala 29:58]
|
|
node _T_5552 = cat(_T_5551, ic_tag_valid_out[0][76]) @[Cat.scala 29:58]
|
|
node _T_5553 = cat(_T_5552, ic_tag_valid_out[0][75]) @[Cat.scala 29:58]
|
|
node _T_5554 = cat(_T_5553, ic_tag_valid_out[0][74]) @[Cat.scala 29:58]
|
|
node _T_5555 = cat(_T_5554, ic_tag_valid_out[0][73]) @[Cat.scala 29:58]
|
|
node _T_5556 = cat(_T_5555, ic_tag_valid_out[0][72]) @[Cat.scala 29:58]
|
|
node _T_5557 = cat(_T_5556, ic_tag_valid_out[0][71]) @[Cat.scala 29:58]
|
|
node _T_5558 = cat(_T_5557, ic_tag_valid_out[0][70]) @[Cat.scala 29:58]
|
|
node _T_5559 = cat(_T_5558, ic_tag_valid_out[0][69]) @[Cat.scala 29:58]
|
|
node _T_5560 = cat(_T_5559, ic_tag_valid_out[0][68]) @[Cat.scala 29:58]
|
|
node _T_5561 = cat(_T_5560, ic_tag_valid_out[0][67]) @[Cat.scala 29:58]
|
|
node _T_5562 = cat(_T_5561, ic_tag_valid_out[0][66]) @[Cat.scala 29:58]
|
|
node _T_5563 = cat(_T_5562, ic_tag_valid_out[0][65]) @[Cat.scala 29:58]
|
|
node _T_5564 = cat(_T_5563, ic_tag_valid_out[0][64]) @[Cat.scala 29:58]
|
|
node _T_5565 = cat(_T_5564, ic_tag_valid_out[0][63]) @[Cat.scala 29:58]
|
|
node _T_5566 = cat(_T_5565, ic_tag_valid_out[0][62]) @[Cat.scala 29:58]
|
|
node _T_5567 = cat(_T_5566, ic_tag_valid_out[0][61]) @[Cat.scala 29:58]
|
|
node _T_5568 = cat(_T_5567, ic_tag_valid_out[0][60]) @[Cat.scala 29:58]
|
|
node _T_5569 = cat(_T_5568, ic_tag_valid_out[0][59]) @[Cat.scala 29:58]
|
|
node _T_5570 = cat(_T_5569, ic_tag_valid_out[0][58]) @[Cat.scala 29:58]
|
|
node _T_5571 = cat(_T_5570, ic_tag_valid_out[0][57]) @[Cat.scala 29:58]
|
|
node _T_5572 = cat(_T_5571, ic_tag_valid_out[0][56]) @[Cat.scala 29:58]
|
|
node _T_5573 = cat(_T_5572, ic_tag_valid_out[0][55]) @[Cat.scala 29:58]
|
|
node _T_5574 = cat(_T_5573, ic_tag_valid_out[0][54]) @[Cat.scala 29:58]
|
|
node _T_5575 = cat(_T_5574, ic_tag_valid_out[0][53]) @[Cat.scala 29:58]
|
|
node _T_5576 = cat(_T_5575, ic_tag_valid_out[0][52]) @[Cat.scala 29:58]
|
|
node _T_5577 = cat(_T_5576, ic_tag_valid_out[0][51]) @[Cat.scala 29:58]
|
|
node _T_5578 = cat(_T_5577, ic_tag_valid_out[0][50]) @[Cat.scala 29:58]
|
|
node _T_5579 = cat(_T_5578, ic_tag_valid_out[0][49]) @[Cat.scala 29:58]
|
|
node _T_5580 = cat(_T_5579, ic_tag_valid_out[0][48]) @[Cat.scala 29:58]
|
|
node _T_5581 = cat(_T_5580, ic_tag_valid_out[0][47]) @[Cat.scala 29:58]
|
|
node _T_5582 = cat(_T_5581, ic_tag_valid_out[0][46]) @[Cat.scala 29:58]
|
|
node _T_5583 = cat(_T_5582, ic_tag_valid_out[0][45]) @[Cat.scala 29:58]
|
|
node _T_5584 = cat(_T_5583, ic_tag_valid_out[0][44]) @[Cat.scala 29:58]
|
|
node _T_5585 = cat(_T_5584, ic_tag_valid_out[0][43]) @[Cat.scala 29:58]
|
|
node _T_5586 = cat(_T_5585, ic_tag_valid_out[0][42]) @[Cat.scala 29:58]
|
|
node _T_5587 = cat(_T_5586, ic_tag_valid_out[0][41]) @[Cat.scala 29:58]
|
|
node _T_5588 = cat(_T_5587, ic_tag_valid_out[0][40]) @[Cat.scala 29:58]
|
|
node _T_5589 = cat(_T_5588, ic_tag_valid_out[0][39]) @[Cat.scala 29:58]
|
|
node _T_5590 = cat(_T_5589, ic_tag_valid_out[0][38]) @[Cat.scala 29:58]
|
|
node _T_5591 = cat(_T_5590, ic_tag_valid_out[0][37]) @[Cat.scala 29:58]
|
|
node _T_5592 = cat(_T_5591, ic_tag_valid_out[0][36]) @[Cat.scala 29:58]
|
|
node _T_5593 = cat(_T_5592, ic_tag_valid_out[0][35]) @[Cat.scala 29:58]
|
|
node _T_5594 = cat(_T_5593, ic_tag_valid_out[0][34]) @[Cat.scala 29:58]
|
|
node _T_5595 = cat(_T_5594, ic_tag_valid_out[0][33]) @[Cat.scala 29:58]
|
|
node _T_5596 = cat(_T_5595, ic_tag_valid_out[0][32]) @[Cat.scala 29:58]
|
|
node _T_5597 = cat(_T_5596, ic_tag_valid_out[0][31]) @[Cat.scala 29:58]
|
|
node _T_5598 = cat(_T_5597, ic_tag_valid_out[0][30]) @[Cat.scala 29:58]
|
|
node _T_5599 = cat(_T_5598, ic_tag_valid_out[0][29]) @[Cat.scala 29:58]
|
|
node _T_5600 = cat(_T_5599, ic_tag_valid_out[0][28]) @[Cat.scala 29:58]
|
|
node _T_5601 = cat(_T_5600, ic_tag_valid_out[0][27]) @[Cat.scala 29:58]
|
|
node _T_5602 = cat(_T_5601, ic_tag_valid_out[0][26]) @[Cat.scala 29:58]
|
|
node _T_5603 = cat(_T_5602, ic_tag_valid_out[0][25]) @[Cat.scala 29:58]
|
|
node _T_5604 = cat(_T_5603, ic_tag_valid_out[0][24]) @[Cat.scala 29:58]
|
|
node _T_5605 = cat(_T_5604, ic_tag_valid_out[0][23]) @[Cat.scala 29:58]
|
|
node _T_5606 = cat(_T_5605, ic_tag_valid_out[0][22]) @[Cat.scala 29:58]
|
|
node _T_5607 = cat(_T_5606, ic_tag_valid_out[0][21]) @[Cat.scala 29:58]
|
|
node _T_5608 = cat(_T_5607, ic_tag_valid_out[0][20]) @[Cat.scala 29:58]
|
|
node _T_5609 = cat(_T_5608, ic_tag_valid_out[0][19]) @[Cat.scala 29:58]
|
|
node _T_5610 = cat(_T_5609, ic_tag_valid_out[0][18]) @[Cat.scala 29:58]
|
|
node _T_5611 = cat(_T_5610, ic_tag_valid_out[0][17]) @[Cat.scala 29:58]
|
|
node _T_5612 = cat(_T_5611, ic_tag_valid_out[0][16]) @[Cat.scala 29:58]
|
|
node _T_5613 = cat(_T_5612, ic_tag_valid_out[0][15]) @[Cat.scala 29:58]
|
|
node _T_5614 = cat(_T_5613, ic_tag_valid_out[0][14]) @[Cat.scala 29:58]
|
|
node _T_5615 = cat(_T_5614, ic_tag_valid_out[0][13]) @[Cat.scala 29:58]
|
|
node _T_5616 = cat(_T_5615, ic_tag_valid_out[0][12]) @[Cat.scala 29:58]
|
|
node _T_5617 = cat(_T_5616, ic_tag_valid_out[0][11]) @[Cat.scala 29:58]
|
|
node _T_5618 = cat(_T_5617, ic_tag_valid_out[0][10]) @[Cat.scala 29:58]
|
|
node _T_5619 = cat(_T_5618, ic_tag_valid_out[0][9]) @[Cat.scala 29:58]
|
|
node _T_5620 = cat(_T_5619, ic_tag_valid_out[0][8]) @[Cat.scala 29:58]
|
|
node _T_5621 = cat(_T_5620, ic_tag_valid_out[0][7]) @[Cat.scala 29:58]
|
|
node _T_5622 = cat(_T_5621, ic_tag_valid_out[0][6]) @[Cat.scala 29:58]
|
|
node _T_5623 = cat(_T_5622, ic_tag_valid_out[0][5]) @[Cat.scala 29:58]
|
|
node _T_5624 = cat(_T_5623, ic_tag_valid_out[0][4]) @[Cat.scala 29:58]
|
|
node _T_5625 = cat(_T_5624, ic_tag_valid_out[0][3]) @[Cat.scala 29:58]
|
|
node _T_5626 = cat(_T_5625, ic_tag_valid_out[0][2]) @[Cat.scala 29:58]
|
|
node _T_5627 = cat(_T_5626, ic_tag_valid_out[0][1]) @[Cat.scala 29:58]
|
|
node _T_5628 = cat(_T_5627, ic_tag_valid_out[0][0]) @[Cat.scala 29:58]
|
|
node _T_5629 = cat(_T_5501, _T_5628) @[Cat.scala 29:58]
|
|
io.valids <= _T_5629 @[el2_ifu_mem_ctl.scala 750:15]
|
|
node _T_5630 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5631 = eq(_T_5630, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5632 = and(ic_valid_ff, _T_5631) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5633 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5634 = and(_T_5632, _T_5633) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5635 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5636 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5637 = and(_T_5635, _T_5636) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5638 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5639 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5640 = and(_T_5638, _T_5639) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5641 = or(_T_5637, _T_5640) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5642 = or(_T_5641, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5643 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5644 = and(_T_5642, _T_5643) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5645 = bits(_T_5644, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5646 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5645 : @[Reg.scala 28:19]
|
|
_T_5646 <= _T_5634 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][0] <= _T_5646 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5647 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5648 = eq(_T_5647, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5649 = and(ic_valid_ff, _T_5648) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5650 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5651 = and(_T_5649, _T_5650) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5652 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5653 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5654 = and(_T_5652, _T_5653) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5655 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5656 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5657 = and(_T_5655, _T_5656) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5658 = or(_T_5654, _T_5657) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5659 = or(_T_5658, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5660 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5661 = and(_T_5659, _T_5660) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5662 = bits(_T_5661, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5663 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5662 : @[Reg.scala 28:19]
|
|
_T_5663 <= _T_5651 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][1] <= _T_5663 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5664 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5665 = eq(_T_5664, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5666 = and(ic_valid_ff, _T_5665) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5667 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5668 = and(_T_5666, _T_5667) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5669 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5670 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5671 = and(_T_5669, _T_5670) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5672 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5673 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5674 = and(_T_5672, _T_5673) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5675 = or(_T_5671, _T_5674) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5676 = or(_T_5675, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5677 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5678 = and(_T_5676, _T_5677) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5679 = bits(_T_5678, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5680 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5679 : @[Reg.scala 28:19]
|
|
_T_5680 <= _T_5668 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][2] <= _T_5680 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5681 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5682 = eq(_T_5681, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5683 = and(ic_valid_ff, _T_5682) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5684 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5685 = and(_T_5683, _T_5684) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5686 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5687 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5688 = and(_T_5686, _T_5687) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5689 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5690 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5691 = and(_T_5689, _T_5690) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5692 = or(_T_5688, _T_5691) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5693 = or(_T_5692, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5694 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5695 = and(_T_5693, _T_5694) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5696 = bits(_T_5695, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5697 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5696 : @[Reg.scala 28:19]
|
|
_T_5697 <= _T_5685 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][3] <= _T_5697 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5698 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5699 = eq(_T_5698, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5700 = and(ic_valid_ff, _T_5699) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5701 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5702 = and(_T_5700, _T_5701) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5703 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5704 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5705 = and(_T_5703, _T_5704) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5706 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5707 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5708 = and(_T_5706, _T_5707) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5709 = or(_T_5705, _T_5708) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5710 = or(_T_5709, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5711 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5712 = and(_T_5710, _T_5711) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5713 = bits(_T_5712, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5714 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5713 : @[Reg.scala 28:19]
|
|
_T_5714 <= _T_5702 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][4] <= _T_5714 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5715 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5716 = eq(_T_5715, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5717 = and(ic_valid_ff, _T_5716) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5718 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5719 = and(_T_5717, _T_5718) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5720 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5721 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5722 = and(_T_5720, _T_5721) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5723 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5724 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5725 = and(_T_5723, _T_5724) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5726 = or(_T_5722, _T_5725) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5727 = or(_T_5726, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5728 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5729 = and(_T_5727, _T_5728) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5730 = bits(_T_5729, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5731 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5730 : @[Reg.scala 28:19]
|
|
_T_5731 <= _T_5719 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][5] <= _T_5731 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5732 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5733 = eq(_T_5732, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5734 = and(ic_valid_ff, _T_5733) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5735 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5736 = and(_T_5734, _T_5735) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5737 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5738 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5739 = and(_T_5737, _T_5738) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5740 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5741 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5742 = and(_T_5740, _T_5741) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5743 = or(_T_5739, _T_5742) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5744 = or(_T_5743, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5745 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5746 = and(_T_5744, _T_5745) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5747 = bits(_T_5746, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5748 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5747 : @[Reg.scala 28:19]
|
|
_T_5748 <= _T_5736 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][6] <= _T_5748 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5749 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5750 = eq(_T_5749, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5751 = and(ic_valid_ff, _T_5750) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5752 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5753 = and(_T_5751, _T_5752) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5754 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5755 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5756 = and(_T_5754, _T_5755) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5757 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5758 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5759 = and(_T_5757, _T_5758) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5760 = or(_T_5756, _T_5759) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5761 = or(_T_5760, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5762 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5763 = and(_T_5761, _T_5762) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5764 = bits(_T_5763, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5765 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5764 : @[Reg.scala 28:19]
|
|
_T_5765 <= _T_5753 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][7] <= _T_5765 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5766 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5767 = eq(_T_5766, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5768 = and(ic_valid_ff, _T_5767) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5769 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5770 = and(_T_5768, _T_5769) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5771 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5772 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5773 = and(_T_5771, _T_5772) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5774 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5775 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5776 = and(_T_5774, _T_5775) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5777 = or(_T_5773, _T_5776) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5778 = or(_T_5777, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5779 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5780 = and(_T_5778, _T_5779) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5781 = bits(_T_5780, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5782 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5781 : @[Reg.scala 28:19]
|
|
_T_5782 <= _T_5770 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][8] <= _T_5782 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5783 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5784 = eq(_T_5783, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5785 = and(ic_valid_ff, _T_5784) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5786 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5787 = and(_T_5785, _T_5786) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5788 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5789 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5790 = and(_T_5788, _T_5789) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5791 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5792 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5793 = and(_T_5791, _T_5792) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5794 = or(_T_5790, _T_5793) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5795 = or(_T_5794, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5796 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5797 = and(_T_5795, _T_5796) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5798 = bits(_T_5797, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5799 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5798 : @[Reg.scala 28:19]
|
|
_T_5799 <= _T_5787 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][9] <= _T_5799 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5800 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5801 = eq(_T_5800, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5802 = and(ic_valid_ff, _T_5801) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5803 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5804 = and(_T_5802, _T_5803) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5805 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5806 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5807 = and(_T_5805, _T_5806) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5808 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5809 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5810 = and(_T_5808, _T_5809) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5811 = or(_T_5807, _T_5810) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5812 = or(_T_5811, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5813 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5814 = and(_T_5812, _T_5813) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5815 = bits(_T_5814, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5816 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5815 : @[Reg.scala 28:19]
|
|
_T_5816 <= _T_5804 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][10] <= _T_5816 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5817 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5818 = eq(_T_5817, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5819 = and(ic_valid_ff, _T_5818) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5820 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5821 = and(_T_5819, _T_5820) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5822 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5823 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5824 = and(_T_5822, _T_5823) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5825 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5826 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5827 = and(_T_5825, _T_5826) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5828 = or(_T_5824, _T_5827) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5829 = or(_T_5828, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5830 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5831 = and(_T_5829, _T_5830) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5832 = bits(_T_5831, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5833 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5832 : @[Reg.scala 28:19]
|
|
_T_5833 <= _T_5821 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][11] <= _T_5833 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5834 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5835 = eq(_T_5834, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5836 = and(ic_valid_ff, _T_5835) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5837 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5838 = and(_T_5836, _T_5837) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5839 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5840 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5841 = and(_T_5839, _T_5840) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5842 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5843 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5844 = and(_T_5842, _T_5843) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5845 = or(_T_5841, _T_5844) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5846 = or(_T_5845, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5847 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5848 = and(_T_5846, _T_5847) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5849 = bits(_T_5848, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5850 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5849 : @[Reg.scala 28:19]
|
|
_T_5850 <= _T_5838 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][12] <= _T_5850 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5851 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5852 = eq(_T_5851, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5853 = and(ic_valid_ff, _T_5852) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5854 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5855 = and(_T_5853, _T_5854) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5856 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5857 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5858 = and(_T_5856, _T_5857) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5859 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5860 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5861 = and(_T_5859, _T_5860) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5862 = or(_T_5858, _T_5861) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5863 = or(_T_5862, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5864 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5865 = and(_T_5863, _T_5864) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5866 = bits(_T_5865, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5867 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5866 : @[Reg.scala 28:19]
|
|
_T_5867 <= _T_5855 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][13] <= _T_5867 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5868 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5869 = eq(_T_5868, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5870 = and(ic_valid_ff, _T_5869) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5871 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5872 = and(_T_5870, _T_5871) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5873 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5874 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5875 = and(_T_5873, _T_5874) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5876 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5877 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5878 = and(_T_5876, _T_5877) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5879 = or(_T_5875, _T_5878) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5880 = or(_T_5879, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5881 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5882 = and(_T_5880, _T_5881) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5883 = bits(_T_5882, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5884 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5883 : @[Reg.scala 28:19]
|
|
_T_5884 <= _T_5872 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][14] <= _T_5884 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5885 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5886 = eq(_T_5885, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5887 = and(ic_valid_ff, _T_5886) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5888 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5889 = and(_T_5887, _T_5888) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5890 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5891 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5892 = and(_T_5890, _T_5891) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5893 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5894 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5895 = and(_T_5893, _T_5894) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5896 = or(_T_5892, _T_5895) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5897 = or(_T_5896, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5898 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5899 = and(_T_5897, _T_5898) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5900 = bits(_T_5899, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5901 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5900 : @[Reg.scala 28:19]
|
|
_T_5901 <= _T_5889 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][15] <= _T_5901 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5902 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5903 = eq(_T_5902, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5904 = and(ic_valid_ff, _T_5903) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5905 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5906 = and(_T_5904, _T_5905) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5907 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5908 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5909 = and(_T_5907, _T_5908) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5910 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5911 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5912 = and(_T_5910, _T_5911) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5913 = or(_T_5909, _T_5912) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5914 = or(_T_5913, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5915 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5916 = and(_T_5914, _T_5915) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5917 = bits(_T_5916, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5918 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5917 : @[Reg.scala 28:19]
|
|
_T_5918 <= _T_5906 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][16] <= _T_5918 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5919 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5920 = eq(_T_5919, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5921 = and(ic_valid_ff, _T_5920) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5922 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5923 = and(_T_5921, _T_5922) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5924 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5925 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5926 = and(_T_5924, _T_5925) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5927 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5928 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5929 = and(_T_5927, _T_5928) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5930 = or(_T_5926, _T_5929) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5931 = or(_T_5930, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5932 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5933 = and(_T_5931, _T_5932) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5934 = bits(_T_5933, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5935 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5934 : @[Reg.scala 28:19]
|
|
_T_5935 <= _T_5923 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][17] <= _T_5935 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5936 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5937 = eq(_T_5936, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5938 = and(ic_valid_ff, _T_5937) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5939 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5940 = and(_T_5938, _T_5939) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5941 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5942 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5943 = and(_T_5941, _T_5942) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5944 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5945 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5946 = and(_T_5944, _T_5945) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5947 = or(_T_5943, _T_5946) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5948 = or(_T_5947, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5949 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5950 = and(_T_5948, _T_5949) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5951 = bits(_T_5950, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5952 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5951 : @[Reg.scala 28:19]
|
|
_T_5952 <= _T_5940 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][18] <= _T_5952 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5953 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5954 = eq(_T_5953, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5955 = and(ic_valid_ff, _T_5954) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5956 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5957 = and(_T_5955, _T_5956) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5958 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5959 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5960 = and(_T_5958, _T_5959) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5961 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5962 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5963 = and(_T_5961, _T_5962) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5964 = or(_T_5960, _T_5963) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5965 = or(_T_5964, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5966 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5967 = and(_T_5965, _T_5966) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5968 = bits(_T_5967, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5969 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5968 : @[Reg.scala 28:19]
|
|
_T_5969 <= _T_5957 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][19] <= _T_5969 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5970 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5971 = eq(_T_5970, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5972 = and(ic_valid_ff, _T_5971) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5973 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5974 = and(_T_5972, _T_5973) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5975 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5976 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5977 = and(_T_5975, _T_5976) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5978 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5979 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5980 = and(_T_5978, _T_5979) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5981 = or(_T_5977, _T_5980) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5982 = or(_T_5981, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_5983 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_5984 = and(_T_5982, _T_5983) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_5985 = bits(_T_5984, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_5986 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_5985 : @[Reg.scala 28:19]
|
|
_T_5986 <= _T_5974 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][20] <= _T_5986 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_5987 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_5988 = eq(_T_5987, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_5989 = and(ic_valid_ff, _T_5988) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_5990 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_5991 = and(_T_5989, _T_5990) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_5992 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_5993 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_5994 = and(_T_5992, _T_5993) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_5995 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_5996 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_5997 = and(_T_5995, _T_5996) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_5998 = or(_T_5994, _T_5997) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_5999 = or(_T_5998, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6000 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6001 = and(_T_5999, _T_6000) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6002 = bits(_T_6001, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6003 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6002 : @[Reg.scala 28:19]
|
|
_T_6003 <= _T_5991 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][21] <= _T_6003 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6004 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6005 = eq(_T_6004, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6006 = and(ic_valid_ff, _T_6005) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6007 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6008 = and(_T_6006, _T_6007) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6009 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6010 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6011 = and(_T_6009, _T_6010) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6012 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6013 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6014 = and(_T_6012, _T_6013) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6015 = or(_T_6011, _T_6014) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6016 = or(_T_6015, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6017 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6018 = and(_T_6016, _T_6017) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6019 = bits(_T_6018, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6020 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6019 : @[Reg.scala 28:19]
|
|
_T_6020 <= _T_6008 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][22] <= _T_6020 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6021 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6022 = eq(_T_6021, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6023 = and(ic_valid_ff, _T_6022) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6024 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6025 = and(_T_6023, _T_6024) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6026 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6027 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6028 = and(_T_6026, _T_6027) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6029 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6030 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6031 = and(_T_6029, _T_6030) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6032 = or(_T_6028, _T_6031) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6033 = or(_T_6032, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6034 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6035 = and(_T_6033, _T_6034) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6036 = bits(_T_6035, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6037 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6036 : @[Reg.scala 28:19]
|
|
_T_6037 <= _T_6025 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][23] <= _T_6037 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6038 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6039 = eq(_T_6038, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6040 = and(ic_valid_ff, _T_6039) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6041 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6042 = and(_T_6040, _T_6041) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6043 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6044 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6045 = and(_T_6043, _T_6044) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6046 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6047 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6048 = and(_T_6046, _T_6047) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6049 = or(_T_6045, _T_6048) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6050 = or(_T_6049, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6051 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6052 = and(_T_6050, _T_6051) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6053 = bits(_T_6052, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6054 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6053 : @[Reg.scala 28:19]
|
|
_T_6054 <= _T_6042 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][24] <= _T_6054 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6055 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6056 = eq(_T_6055, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6057 = and(ic_valid_ff, _T_6056) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6058 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6059 = and(_T_6057, _T_6058) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6060 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6061 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6062 = and(_T_6060, _T_6061) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6063 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6064 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6065 = and(_T_6063, _T_6064) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6066 = or(_T_6062, _T_6065) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6067 = or(_T_6066, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6068 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6069 = and(_T_6067, _T_6068) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6070 = bits(_T_6069, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6071 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6070 : @[Reg.scala 28:19]
|
|
_T_6071 <= _T_6059 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][25] <= _T_6071 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6072 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6073 = eq(_T_6072, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6074 = and(ic_valid_ff, _T_6073) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6075 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6076 = and(_T_6074, _T_6075) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6077 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6078 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6079 = and(_T_6077, _T_6078) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6080 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6081 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6082 = and(_T_6080, _T_6081) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6083 = or(_T_6079, _T_6082) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6084 = or(_T_6083, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6085 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6086 = and(_T_6084, _T_6085) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6087 = bits(_T_6086, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6088 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6087 : @[Reg.scala 28:19]
|
|
_T_6088 <= _T_6076 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][26] <= _T_6088 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6089 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6090 = eq(_T_6089, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6091 = and(ic_valid_ff, _T_6090) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6092 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6093 = and(_T_6091, _T_6092) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6094 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6095 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6096 = and(_T_6094, _T_6095) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6097 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6098 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6099 = and(_T_6097, _T_6098) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6100 = or(_T_6096, _T_6099) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6101 = or(_T_6100, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6102 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6103 = and(_T_6101, _T_6102) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6104 = bits(_T_6103, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6105 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6104 : @[Reg.scala 28:19]
|
|
_T_6105 <= _T_6093 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][27] <= _T_6105 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6106 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6107 = eq(_T_6106, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6108 = and(ic_valid_ff, _T_6107) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6109 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6110 = and(_T_6108, _T_6109) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6111 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6112 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6113 = and(_T_6111, _T_6112) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6114 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6115 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6116 = and(_T_6114, _T_6115) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6117 = or(_T_6113, _T_6116) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6118 = or(_T_6117, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6119 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6120 = and(_T_6118, _T_6119) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6121 = bits(_T_6120, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6122 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6121 : @[Reg.scala 28:19]
|
|
_T_6122 <= _T_6110 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][28] <= _T_6122 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6123 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6124 = eq(_T_6123, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6125 = and(ic_valid_ff, _T_6124) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6126 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6127 = and(_T_6125, _T_6126) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6128 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6129 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6130 = and(_T_6128, _T_6129) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6131 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6132 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6133 = and(_T_6131, _T_6132) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6134 = or(_T_6130, _T_6133) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6135 = or(_T_6134, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6136 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6137 = and(_T_6135, _T_6136) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6138 = bits(_T_6137, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6139 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6138 : @[Reg.scala 28:19]
|
|
_T_6139 <= _T_6127 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][29] <= _T_6139 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6140 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6141 = eq(_T_6140, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6142 = and(ic_valid_ff, _T_6141) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6143 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6144 = and(_T_6142, _T_6143) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6145 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6146 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6147 = and(_T_6145, _T_6146) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6148 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6149 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6150 = and(_T_6148, _T_6149) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6151 = or(_T_6147, _T_6150) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6152 = or(_T_6151, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6153 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6154 = and(_T_6152, _T_6153) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6155 = bits(_T_6154, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6156 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6155 : @[Reg.scala 28:19]
|
|
_T_6156 <= _T_6144 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][30] <= _T_6156 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6157 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6158 = eq(_T_6157, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6159 = and(ic_valid_ff, _T_6158) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6160 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6161 = and(_T_6159, _T_6160) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6162 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6163 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6164 = and(_T_6162, _T_6163) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6165 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6166 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6167 = and(_T_6165, _T_6166) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6168 = or(_T_6164, _T_6167) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6169 = or(_T_6168, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6170 = bits(tag_valid_clken_0, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6171 = and(_T_6169, _T_6170) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6172 = bits(_T_6171, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6173 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6172 : @[Reg.scala 28:19]
|
|
_T_6173 <= _T_6161 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][31] <= _T_6173 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6174 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6175 = eq(_T_6174, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6176 = and(ic_valid_ff, _T_6175) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6177 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6178 = and(_T_6176, _T_6177) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6179 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6180 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6181 = and(_T_6179, _T_6180) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6182 = eq(perr_ic_index_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6183 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6184 = and(_T_6182, _T_6183) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6185 = or(_T_6181, _T_6184) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6186 = or(_T_6185, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6187 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6188 = and(_T_6186, _T_6187) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6189 = bits(_T_6188, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6190 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6189 : @[Reg.scala 28:19]
|
|
_T_6190 <= _T_6178 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][0] <= _T_6190 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6191 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6192 = eq(_T_6191, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6193 = and(ic_valid_ff, _T_6192) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6194 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6195 = and(_T_6193, _T_6194) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6196 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6197 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6198 = and(_T_6196, _T_6197) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6199 = eq(perr_ic_index_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6200 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6201 = and(_T_6199, _T_6200) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6202 = or(_T_6198, _T_6201) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6203 = or(_T_6202, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6204 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6205 = and(_T_6203, _T_6204) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6206 = bits(_T_6205, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6207 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6206 : @[Reg.scala 28:19]
|
|
_T_6207 <= _T_6195 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][1] <= _T_6207 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6208 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6209 = eq(_T_6208, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6210 = and(ic_valid_ff, _T_6209) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6211 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6212 = and(_T_6210, _T_6211) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6213 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6214 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6215 = and(_T_6213, _T_6214) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6216 = eq(perr_ic_index_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6217 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6218 = and(_T_6216, _T_6217) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6219 = or(_T_6215, _T_6218) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6220 = or(_T_6219, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6221 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6222 = and(_T_6220, _T_6221) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6223 = bits(_T_6222, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6224 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6223 : @[Reg.scala 28:19]
|
|
_T_6224 <= _T_6212 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][2] <= _T_6224 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6225 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6226 = eq(_T_6225, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6227 = and(ic_valid_ff, _T_6226) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6228 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6229 = and(_T_6227, _T_6228) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6230 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6231 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6232 = and(_T_6230, _T_6231) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6233 = eq(perr_ic_index_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6234 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6235 = and(_T_6233, _T_6234) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6236 = or(_T_6232, _T_6235) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6237 = or(_T_6236, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6238 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6239 = and(_T_6237, _T_6238) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6240 = bits(_T_6239, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6241 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6240 : @[Reg.scala 28:19]
|
|
_T_6241 <= _T_6229 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][3] <= _T_6241 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6242 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6243 = eq(_T_6242, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6244 = and(ic_valid_ff, _T_6243) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6245 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6246 = and(_T_6244, _T_6245) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6247 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6248 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6249 = and(_T_6247, _T_6248) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6250 = eq(perr_ic_index_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6251 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6252 = and(_T_6250, _T_6251) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6253 = or(_T_6249, _T_6252) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6254 = or(_T_6253, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6255 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6256 = and(_T_6254, _T_6255) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6257 = bits(_T_6256, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6258 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6257 : @[Reg.scala 28:19]
|
|
_T_6258 <= _T_6246 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][4] <= _T_6258 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6259 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6260 = eq(_T_6259, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6261 = and(ic_valid_ff, _T_6260) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6262 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6263 = and(_T_6261, _T_6262) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6264 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6265 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6266 = and(_T_6264, _T_6265) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6267 = eq(perr_ic_index_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6268 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6269 = and(_T_6267, _T_6268) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6270 = or(_T_6266, _T_6269) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6271 = or(_T_6270, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6272 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6273 = and(_T_6271, _T_6272) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6274 = bits(_T_6273, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6275 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6274 : @[Reg.scala 28:19]
|
|
_T_6275 <= _T_6263 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][5] <= _T_6275 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6276 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6277 = eq(_T_6276, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6278 = and(ic_valid_ff, _T_6277) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6279 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6280 = and(_T_6278, _T_6279) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6281 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6282 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6283 = and(_T_6281, _T_6282) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6284 = eq(perr_ic_index_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6285 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6286 = and(_T_6284, _T_6285) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6287 = or(_T_6283, _T_6286) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6288 = or(_T_6287, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6289 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6290 = and(_T_6288, _T_6289) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6291 = bits(_T_6290, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6292 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6291 : @[Reg.scala 28:19]
|
|
_T_6292 <= _T_6280 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][6] <= _T_6292 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6293 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6294 = eq(_T_6293, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6295 = and(ic_valid_ff, _T_6294) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6296 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6297 = and(_T_6295, _T_6296) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6298 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6299 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6300 = and(_T_6298, _T_6299) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6301 = eq(perr_ic_index_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6302 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6303 = and(_T_6301, _T_6302) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6304 = or(_T_6300, _T_6303) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6305 = or(_T_6304, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6306 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6307 = and(_T_6305, _T_6306) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6308 = bits(_T_6307, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6309 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6308 : @[Reg.scala 28:19]
|
|
_T_6309 <= _T_6297 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][7] <= _T_6309 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6310 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6311 = eq(_T_6310, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6312 = and(ic_valid_ff, _T_6311) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6313 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6314 = and(_T_6312, _T_6313) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6315 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6316 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6317 = and(_T_6315, _T_6316) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6318 = eq(perr_ic_index_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6319 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6320 = and(_T_6318, _T_6319) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6321 = or(_T_6317, _T_6320) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6322 = or(_T_6321, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6323 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6324 = and(_T_6322, _T_6323) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6325 = bits(_T_6324, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6326 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6325 : @[Reg.scala 28:19]
|
|
_T_6326 <= _T_6314 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][8] <= _T_6326 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6327 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6328 = eq(_T_6327, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6329 = and(ic_valid_ff, _T_6328) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6330 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6331 = and(_T_6329, _T_6330) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6332 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6333 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6334 = and(_T_6332, _T_6333) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6335 = eq(perr_ic_index_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6336 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6337 = and(_T_6335, _T_6336) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6338 = or(_T_6334, _T_6337) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6339 = or(_T_6338, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6340 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6341 = and(_T_6339, _T_6340) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6342 = bits(_T_6341, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6343 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6342 : @[Reg.scala 28:19]
|
|
_T_6343 <= _T_6331 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][9] <= _T_6343 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6344 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6345 = eq(_T_6344, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6346 = and(ic_valid_ff, _T_6345) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6347 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6348 = and(_T_6346, _T_6347) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6349 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6350 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6351 = and(_T_6349, _T_6350) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6352 = eq(perr_ic_index_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6353 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6354 = and(_T_6352, _T_6353) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6355 = or(_T_6351, _T_6354) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6356 = or(_T_6355, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6357 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6358 = and(_T_6356, _T_6357) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6359 = bits(_T_6358, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6360 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6359 : @[Reg.scala 28:19]
|
|
_T_6360 <= _T_6348 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][10] <= _T_6360 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6361 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6362 = eq(_T_6361, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6363 = and(ic_valid_ff, _T_6362) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6364 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6365 = and(_T_6363, _T_6364) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6366 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6367 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6368 = and(_T_6366, _T_6367) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6369 = eq(perr_ic_index_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6370 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6371 = and(_T_6369, _T_6370) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6372 = or(_T_6368, _T_6371) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6373 = or(_T_6372, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6374 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6375 = and(_T_6373, _T_6374) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6376 = bits(_T_6375, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6377 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6376 : @[Reg.scala 28:19]
|
|
_T_6377 <= _T_6365 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][11] <= _T_6377 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6378 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6379 = eq(_T_6378, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6380 = and(ic_valid_ff, _T_6379) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6381 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6382 = and(_T_6380, _T_6381) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6383 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6384 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6385 = and(_T_6383, _T_6384) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6386 = eq(perr_ic_index_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6387 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6388 = and(_T_6386, _T_6387) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6389 = or(_T_6385, _T_6388) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6390 = or(_T_6389, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6391 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6392 = and(_T_6390, _T_6391) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6393 = bits(_T_6392, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6394 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6393 : @[Reg.scala 28:19]
|
|
_T_6394 <= _T_6382 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][12] <= _T_6394 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6395 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6396 = eq(_T_6395, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6397 = and(ic_valid_ff, _T_6396) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6398 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6399 = and(_T_6397, _T_6398) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6400 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6401 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6402 = and(_T_6400, _T_6401) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6403 = eq(perr_ic_index_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6404 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6405 = and(_T_6403, _T_6404) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6406 = or(_T_6402, _T_6405) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6407 = or(_T_6406, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6408 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6409 = and(_T_6407, _T_6408) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6410 = bits(_T_6409, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6411 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6410 : @[Reg.scala 28:19]
|
|
_T_6411 <= _T_6399 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][13] <= _T_6411 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6412 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6413 = eq(_T_6412, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6414 = and(ic_valid_ff, _T_6413) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6415 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6416 = and(_T_6414, _T_6415) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6417 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6418 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6419 = and(_T_6417, _T_6418) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6420 = eq(perr_ic_index_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6421 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6422 = and(_T_6420, _T_6421) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6423 = or(_T_6419, _T_6422) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6424 = or(_T_6423, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6425 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6426 = and(_T_6424, _T_6425) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6427 = bits(_T_6426, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6428 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6427 : @[Reg.scala 28:19]
|
|
_T_6428 <= _T_6416 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][14] <= _T_6428 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6429 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6430 = eq(_T_6429, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6431 = and(ic_valid_ff, _T_6430) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6432 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6433 = and(_T_6431, _T_6432) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6434 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6435 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6436 = and(_T_6434, _T_6435) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6437 = eq(perr_ic_index_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6438 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6439 = and(_T_6437, _T_6438) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6440 = or(_T_6436, _T_6439) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6441 = or(_T_6440, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6442 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6443 = and(_T_6441, _T_6442) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6444 = bits(_T_6443, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6445 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6444 : @[Reg.scala 28:19]
|
|
_T_6445 <= _T_6433 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][15] <= _T_6445 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6446 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6447 = eq(_T_6446, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6448 = and(ic_valid_ff, _T_6447) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6449 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6450 = and(_T_6448, _T_6449) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6451 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6452 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6453 = and(_T_6451, _T_6452) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6454 = eq(perr_ic_index_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6455 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6456 = and(_T_6454, _T_6455) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6457 = or(_T_6453, _T_6456) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6458 = or(_T_6457, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6459 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6460 = and(_T_6458, _T_6459) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6461 = bits(_T_6460, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6462 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6461 : @[Reg.scala 28:19]
|
|
_T_6462 <= _T_6450 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][16] <= _T_6462 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6463 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6464 = eq(_T_6463, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6465 = and(ic_valid_ff, _T_6464) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6466 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6467 = and(_T_6465, _T_6466) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6468 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6469 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6470 = and(_T_6468, _T_6469) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6471 = eq(perr_ic_index_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6472 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6473 = and(_T_6471, _T_6472) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6474 = or(_T_6470, _T_6473) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6475 = or(_T_6474, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6476 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6477 = and(_T_6475, _T_6476) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6478 = bits(_T_6477, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6479 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6478 : @[Reg.scala 28:19]
|
|
_T_6479 <= _T_6467 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][17] <= _T_6479 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6480 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6481 = eq(_T_6480, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6482 = and(ic_valid_ff, _T_6481) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6483 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6484 = and(_T_6482, _T_6483) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6485 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6486 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6487 = and(_T_6485, _T_6486) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6488 = eq(perr_ic_index_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6489 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6490 = and(_T_6488, _T_6489) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6491 = or(_T_6487, _T_6490) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6492 = or(_T_6491, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6493 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6494 = and(_T_6492, _T_6493) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6495 = bits(_T_6494, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6496 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6495 : @[Reg.scala 28:19]
|
|
_T_6496 <= _T_6484 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][18] <= _T_6496 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6497 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6498 = eq(_T_6497, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6499 = and(ic_valid_ff, _T_6498) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6500 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6501 = and(_T_6499, _T_6500) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6502 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6503 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6504 = and(_T_6502, _T_6503) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6505 = eq(perr_ic_index_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6506 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6507 = and(_T_6505, _T_6506) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6508 = or(_T_6504, _T_6507) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6509 = or(_T_6508, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6510 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6511 = and(_T_6509, _T_6510) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6512 = bits(_T_6511, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6513 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6512 : @[Reg.scala 28:19]
|
|
_T_6513 <= _T_6501 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][19] <= _T_6513 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6514 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6515 = eq(_T_6514, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6516 = and(ic_valid_ff, _T_6515) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6517 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6518 = and(_T_6516, _T_6517) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6519 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6520 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6521 = and(_T_6519, _T_6520) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6522 = eq(perr_ic_index_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6523 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6524 = and(_T_6522, _T_6523) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6525 = or(_T_6521, _T_6524) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6526 = or(_T_6525, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6527 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6528 = and(_T_6526, _T_6527) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6529 = bits(_T_6528, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6530 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6529 : @[Reg.scala 28:19]
|
|
_T_6530 <= _T_6518 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][20] <= _T_6530 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6531 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6532 = eq(_T_6531, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6533 = and(ic_valid_ff, _T_6532) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6534 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6535 = and(_T_6533, _T_6534) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6536 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6537 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6538 = and(_T_6536, _T_6537) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6539 = eq(perr_ic_index_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6540 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6541 = and(_T_6539, _T_6540) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6542 = or(_T_6538, _T_6541) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6543 = or(_T_6542, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6544 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6545 = and(_T_6543, _T_6544) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6546 = bits(_T_6545, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6547 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6546 : @[Reg.scala 28:19]
|
|
_T_6547 <= _T_6535 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][21] <= _T_6547 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6548 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6549 = eq(_T_6548, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6550 = and(ic_valid_ff, _T_6549) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6551 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6552 = and(_T_6550, _T_6551) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6553 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6554 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6555 = and(_T_6553, _T_6554) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6556 = eq(perr_ic_index_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6557 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6558 = and(_T_6556, _T_6557) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6559 = or(_T_6555, _T_6558) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6560 = or(_T_6559, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6561 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6562 = and(_T_6560, _T_6561) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6563 = bits(_T_6562, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6564 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6563 : @[Reg.scala 28:19]
|
|
_T_6564 <= _T_6552 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][22] <= _T_6564 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6565 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6566 = eq(_T_6565, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6567 = and(ic_valid_ff, _T_6566) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6568 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6569 = and(_T_6567, _T_6568) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6570 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6571 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6572 = and(_T_6570, _T_6571) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6573 = eq(perr_ic_index_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6574 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6575 = and(_T_6573, _T_6574) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6576 = or(_T_6572, _T_6575) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6577 = or(_T_6576, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6578 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6579 = and(_T_6577, _T_6578) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6580 = bits(_T_6579, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6581 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6580 : @[Reg.scala 28:19]
|
|
_T_6581 <= _T_6569 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][23] <= _T_6581 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6582 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6583 = eq(_T_6582, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6584 = and(ic_valid_ff, _T_6583) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6585 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6586 = and(_T_6584, _T_6585) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6587 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6588 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6589 = and(_T_6587, _T_6588) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6590 = eq(perr_ic_index_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6591 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6592 = and(_T_6590, _T_6591) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6593 = or(_T_6589, _T_6592) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6594 = or(_T_6593, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6595 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6596 = and(_T_6594, _T_6595) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6597 = bits(_T_6596, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6598 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6597 : @[Reg.scala 28:19]
|
|
_T_6598 <= _T_6586 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][24] <= _T_6598 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6599 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6600 = eq(_T_6599, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6601 = and(ic_valid_ff, _T_6600) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6602 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6603 = and(_T_6601, _T_6602) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6604 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6605 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6606 = and(_T_6604, _T_6605) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6607 = eq(perr_ic_index_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6608 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6609 = and(_T_6607, _T_6608) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6610 = or(_T_6606, _T_6609) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6611 = or(_T_6610, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6612 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6613 = and(_T_6611, _T_6612) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6614 = bits(_T_6613, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6615 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6614 : @[Reg.scala 28:19]
|
|
_T_6615 <= _T_6603 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][25] <= _T_6615 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6616 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6617 = eq(_T_6616, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6618 = and(ic_valid_ff, _T_6617) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6619 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6620 = and(_T_6618, _T_6619) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6621 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6622 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6623 = and(_T_6621, _T_6622) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6624 = eq(perr_ic_index_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6625 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6626 = and(_T_6624, _T_6625) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6627 = or(_T_6623, _T_6626) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6628 = or(_T_6627, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6629 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6630 = and(_T_6628, _T_6629) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6631 = bits(_T_6630, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6632 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6631 : @[Reg.scala 28:19]
|
|
_T_6632 <= _T_6620 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][26] <= _T_6632 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6633 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6634 = eq(_T_6633, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6635 = and(ic_valid_ff, _T_6634) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6636 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6637 = and(_T_6635, _T_6636) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6638 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6639 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6640 = and(_T_6638, _T_6639) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6641 = eq(perr_ic_index_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6642 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6643 = and(_T_6641, _T_6642) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6644 = or(_T_6640, _T_6643) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6645 = or(_T_6644, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6646 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6647 = and(_T_6645, _T_6646) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6648 = bits(_T_6647, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6649 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6648 : @[Reg.scala 28:19]
|
|
_T_6649 <= _T_6637 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][27] <= _T_6649 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6650 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6651 = eq(_T_6650, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6652 = and(ic_valid_ff, _T_6651) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6653 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6654 = and(_T_6652, _T_6653) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6655 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6656 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6657 = and(_T_6655, _T_6656) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6658 = eq(perr_ic_index_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6659 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6660 = and(_T_6658, _T_6659) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6661 = or(_T_6657, _T_6660) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6662 = or(_T_6661, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6663 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6664 = and(_T_6662, _T_6663) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6665 = bits(_T_6664, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6666 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6665 : @[Reg.scala 28:19]
|
|
_T_6666 <= _T_6654 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][28] <= _T_6666 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6667 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6668 = eq(_T_6667, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6669 = and(ic_valid_ff, _T_6668) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6670 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6671 = and(_T_6669, _T_6670) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6672 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6673 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6674 = and(_T_6672, _T_6673) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6675 = eq(perr_ic_index_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6676 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6677 = and(_T_6675, _T_6676) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6678 = or(_T_6674, _T_6677) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6679 = or(_T_6678, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6680 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6681 = and(_T_6679, _T_6680) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6682 = bits(_T_6681, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6683 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6682 : @[Reg.scala 28:19]
|
|
_T_6683 <= _T_6671 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][29] <= _T_6683 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6684 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6685 = eq(_T_6684, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6686 = and(ic_valid_ff, _T_6685) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6687 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6688 = and(_T_6686, _T_6687) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6689 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6690 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6691 = and(_T_6689, _T_6690) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6692 = eq(perr_ic_index_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6693 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6694 = and(_T_6692, _T_6693) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6695 = or(_T_6691, _T_6694) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6696 = or(_T_6695, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6697 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6698 = and(_T_6696, _T_6697) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6699 = bits(_T_6698, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6700 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6699 : @[Reg.scala 28:19]
|
|
_T_6700 <= _T_6688 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][30] <= _T_6700 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6701 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6702 = eq(_T_6701, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6703 = and(ic_valid_ff, _T_6702) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6704 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6705 = and(_T_6703, _T_6704) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6706 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6707 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6708 = and(_T_6706, _T_6707) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6709 = eq(perr_ic_index_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6710 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6711 = and(_T_6709, _T_6710) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6712 = or(_T_6708, _T_6711) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6713 = or(_T_6712, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6714 = bits(tag_valid_clken_0, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6715 = and(_T_6713, _T_6714) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6716 = bits(_T_6715, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6717 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6716 : @[Reg.scala 28:19]
|
|
_T_6717 <= _T_6705 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][31] <= _T_6717 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6718 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6719 = eq(_T_6718, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6720 = and(ic_valid_ff, _T_6719) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6721 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6722 = and(_T_6720, _T_6721) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6723 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6724 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6725 = and(_T_6723, _T_6724) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6726 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6727 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6728 = and(_T_6726, _T_6727) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6729 = or(_T_6725, _T_6728) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6730 = or(_T_6729, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6731 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6732 = and(_T_6730, _T_6731) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6733 = bits(_T_6732, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6734 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6733 : @[Reg.scala 28:19]
|
|
_T_6734 <= _T_6722 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][32] <= _T_6734 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6735 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6736 = eq(_T_6735, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6737 = and(ic_valid_ff, _T_6736) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6738 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6739 = and(_T_6737, _T_6738) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6740 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6741 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6742 = and(_T_6740, _T_6741) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6743 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6744 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6745 = and(_T_6743, _T_6744) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6746 = or(_T_6742, _T_6745) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6747 = or(_T_6746, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6748 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6749 = and(_T_6747, _T_6748) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6750 = bits(_T_6749, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6751 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6750 : @[Reg.scala 28:19]
|
|
_T_6751 <= _T_6739 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][33] <= _T_6751 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6752 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6753 = eq(_T_6752, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6754 = and(ic_valid_ff, _T_6753) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6755 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6756 = and(_T_6754, _T_6755) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6757 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6758 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6759 = and(_T_6757, _T_6758) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6760 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6761 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6762 = and(_T_6760, _T_6761) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6763 = or(_T_6759, _T_6762) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6764 = or(_T_6763, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6765 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6766 = and(_T_6764, _T_6765) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6767 = bits(_T_6766, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6768 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6767 : @[Reg.scala 28:19]
|
|
_T_6768 <= _T_6756 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][34] <= _T_6768 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6769 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6770 = eq(_T_6769, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6771 = and(ic_valid_ff, _T_6770) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6772 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6773 = and(_T_6771, _T_6772) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6774 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6775 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6776 = and(_T_6774, _T_6775) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6777 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6778 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6779 = and(_T_6777, _T_6778) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6780 = or(_T_6776, _T_6779) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6781 = or(_T_6780, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6782 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6783 = and(_T_6781, _T_6782) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6784 = bits(_T_6783, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6785 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6784 : @[Reg.scala 28:19]
|
|
_T_6785 <= _T_6773 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][35] <= _T_6785 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6786 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6787 = eq(_T_6786, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6788 = and(ic_valid_ff, _T_6787) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6789 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6790 = and(_T_6788, _T_6789) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6791 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6792 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6793 = and(_T_6791, _T_6792) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6794 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6795 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6796 = and(_T_6794, _T_6795) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6797 = or(_T_6793, _T_6796) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6798 = or(_T_6797, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6799 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6800 = and(_T_6798, _T_6799) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6801 = bits(_T_6800, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6802 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6801 : @[Reg.scala 28:19]
|
|
_T_6802 <= _T_6790 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][36] <= _T_6802 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6803 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6804 = eq(_T_6803, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6805 = and(ic_valid_ff, _T_6804) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6806 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6807 = and(_T_6805, _T_6806) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6808 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6809 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6810 = and(_T_6808, _T_6809) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6811 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6812 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6813 = and(_T_6811, _T_6812) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6814 = or(_T_6810, _T_6813) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6815 = or(_T_6814, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6816 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6817 = and(_T_6815, _T_6816) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6818 = bits(_T_6817, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6819 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6818 : @[Reg.scala 28:19]
|
|
_T_6819 <= _T_6807 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][37] <= _T_6819 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6820 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6821 = eq(_T_6820, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6822 = and(ic_valid_ff, _T_6821) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6823 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6824 = and(_T_6822, _T_6823) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6825 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6826 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6827 = and(_T_6825, _T_6826) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6828 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6829 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6830 = and(_T_6828, _T_6829) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6831 = or(_T_6827, _T_6830) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6832 = or(_T_6831, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6833 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6834 = and(_T_6832, _T_6833) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6835 = bits(_T_6834, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6836 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6835 : @[Reg.scala 28:19]
|
|
_T_6836 <= _T_6824 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][38] <= _T_6836 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6837 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6838 = eq(_T_6837, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6839 = and(ic_valid_ff, _T_6838) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6840 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6841 = and(_T_6839, _T_6840) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6842 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6843 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6844 = and(_T_6842, _T_6843) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6845 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6846 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6847 = and(_T_6845, _T_6846) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6848 = or(_T_6844, _T_6847) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6849 = or(_T_6848, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6850 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6851 = and(_T_6849, _T_6850) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6852 = bits(_T_6851, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6853 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6852 : @[Reg.scala 28:19]
|
|
_T_6853 <= _T_6841 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][39] <= _T_6853 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6854 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6855 = eq(_T_6854, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6856 = and(ic_valid_ff, _T_6855) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6857 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6858 = and(_T_6856, _T_6857) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6859 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6860 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6861 = and(_T_6859, _T_6860) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6862 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6863 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6864 = and(_T_6862, _T_6863) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6865 = or(_T_6861, _T_6864) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6866 = or(_T_6865, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6867 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6868 = and(_T_6866, _T_6867) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6869 = bits(_T_6868, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6870 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6869 : @[Reg.scala 28:19]
|
|
_T_6870 <= _T_6858 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][40] <= _T_6870 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6871 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6872 = eq(_T_6871, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6873 = and(ic_valid_ff, _T_6872) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6874 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6875 = and(_T_6873, _T_6874) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6876 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6877 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6878 = and(_T_6876, _T_6877) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6879 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6880 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6881 = and(_T_6879, _T_6880) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6882 = or(_T_6878, _T_6881) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6883 = or(_T_6882, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6884 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6885 = and(_T_6883, _T_6884) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6886 = bits(_T_6885, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6887 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6886 : @[Reg.scala 28:19]
|
|
_T_6887 <= _T_6875 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][41] <= _T_6887 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6888 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6889 = eq(_T_6888, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6890 = and(ic_valid_ff, _T_6889) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6891 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6892 = and(_T_6890, _T_6891) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6893 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6894 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6895 = and(_T_6893, _T_6894) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6896 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6897 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6898 = and(_T_6896, _T_6897) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6899 = or(_T_6895, _T_6898) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6900 = or(_T_6899, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6901 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6902 = and(_T_6900, _T_6901) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6903 = bits(_T_6902, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6904 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6903 : @[Reg.scala 28:19]
|
|
_T_6904 <= _T_6892 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][42] <= _T_6904 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6905 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6906 = eq(_T_6905, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6907 = and(ic_valid_ff, _T_6906) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6908 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6909 = and(_T_6907, _T_6908) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6910 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6911 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6912 = and(_T_6910, _T_6911) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6913 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6914 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6915 = and(_T_6913, _T_6914) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6916 = or(_T_6912, _T_6915) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6917 = or(_T_6916, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6918 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6919 = and(_T_6917, _T_6918) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6920 = bits(_T_6919, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6921 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6920 : @[Reg.scala 28:19]
|
|
_T_6921 <= _T_6909 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][43] <= _T_6921 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6922 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6923 = eq(_T_6922, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6924 = and(ic_valid_ff, _T_6923) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6925 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6926 = and(_T_6924, _T_6925) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6927 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6928 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6929 = and(_T_6927, _T_6928) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6930 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6931 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6932 = and(_T_6930, _T_6931) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6933 = or(_T_6929, _T_6932) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6934 = or(_T_6933, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6935 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6936 = and(_T_6934, _T_6935) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6937 = bits(_T_6936, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6938 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6937 : @[Reg.scala 28:19]
|
|
_T_6938 <= _T_6926 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][44] <= _T_6938 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6939 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6940 = eq(_T_6939, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6941 = and(ic_valid_ff, _T_6940) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6942 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6943 = and(_T_6941, _T_6942) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6944 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6945 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6946 = and(_T_6944, _T_6945) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6947 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6948 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6949 = and(_T_6947, _T_6948) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6950 = or(_T_6946, _T_6949) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6951 = or(_T_6950, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6952 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6953 = and(_T_6951, _T_6952) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6954 = bits(_T_6953, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6955 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6954 : @[Reg.scala 28:19]
|
|
_T_6955 <= _T_6943 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][45] <= _T_6955 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6956 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6957 = eq(_T_6956, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6958 = and(ic_valid_ff, _T_6957) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6959 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6960 = and(_T_6958, _T_6959) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6961 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6962 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6963 = and(_T_6961, _T_6962) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6964 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6965 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6966 = and(_T_6964, _T_6965) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6967 = or(_T_6963, _T_6966) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6968 = or(_T_6967, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6969 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6970 = and(_T_6968, _T_6969) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6971 = bits(_T_6970, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6972 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6971 : @[Reg.scala 28:19]
|
|
_T_6972 <= _T_6960 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][46] <= _T_6972 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6973 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6974 = eq(_T_6973, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6975 = and(ic_valid_ff, _T_6974) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6976 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6977 = and(_T_6975, _T_6976) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6978 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6979 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6980 = and(_T_6978, _T_6979) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6981 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6982 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_6983 = and(_T_6981, _T_6982) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_6984 = or(_T_6980, _T_6983) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_6985 = or(_T_6984, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_6986 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_6987 = and(_T_6985, _T_6986) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_6988 = bits(_T_6987, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_6989 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_6988 : @[Reg.scala 28:19]
|
|
_T_6989 <= _T_6977 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][47] <= _T_6989 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_6990 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_6991 = eq(_T_6990, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_6992 = and(ic_valid_ff, _T_6991) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_6993 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_6994 = and(_T_6992, _T_6993) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_6995 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_6996 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_6997 = and(_T_6995, _T_6996) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_6998 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_6999 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7000 = and(_T_6998, _T_6999) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7001 = or(_T_6997, _T_7000) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7002 = or(_T_7001, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7003 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7004 = and(_T_7002, _T_7003) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7005 = bits(_T_7004, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7006 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7005 : @[Reg.scala 28:19]
|
|
_T_7006 <= _T_6994 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][48] <= _T_7006 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7007 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7008 = eq(_T_7007, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7009 = and(ic_valid_ff, _T_7008) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7010 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7011 = and(_T_7009, _T_7010) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7012 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7013 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7014 = and(_T_7012, _T_7013) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7015 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7016 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7017 = and(_T_7015, _T_7016) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7018 = or(_T_7014, _T_7017) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7019 = or(_T_7018, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7020 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7021 = and(_T_7019, _T_7020) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7022 = bits(_T_7021, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7023 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7022 : @[Reg.scala 28:19]
|
|
_T_7023 <= _T_7011 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][49] <= _T_7023 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7024 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7025 = eq(_T_7024, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7026 = and(ic_valid_ff, _T_7025) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7027 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7028 = and(_T_7026, _T_7027) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7029 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7030 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7031 = and(_T_7029, _T_7030) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7032 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7033 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7034 = and(_T_7032, _T_7033) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7035 = or(_T_7031, _T_7034) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7036 = or(_T_7035, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7037 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7038 = and(_T_7036, _T_7037) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7039 = bits(_T_7038, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7040 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7039 : @[Reg.scala 28:19]
|
|
_T_7040 <= _T_7028 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][50] <= _T_7040 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7041 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7042 = eq(_T_7041, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7043 = and(ic_valid_ff, _T_7042) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7044 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7045 = and(_T_7043, _T_7044) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7046 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7047 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7048 = and(_T_7046, _T_7047) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7049 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7050 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7051 = and(_T_7049, _T_7050) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7052 = or(_T_7048, _T_7051) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7053 = or(_T_7052, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7054 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7055 = and(_T_7053, _T_7054) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7056 = bits(_T_7055, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7057 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7056 : @[Reg.scala 28:19]
|
|
_T_7057 <= _T_7045 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][51] <= _T_7057 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7058 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7059 = eq(_T_7058, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7060 = and(ic_valid_ff, _T_7059) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7061 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7062 = and(_T_7060, _T_7061) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7063 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7064 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7065 = and(_T_7063, _T_7064) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7066 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7067 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7068 = and(_T_7066, _T_7067) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7069 = or(_T_7065, _T_7068) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7070 = or(_T_7069, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7071 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7072 = and(_T_7070, _T_7071) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7073 = bits(_T_7072, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7074 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7073 : @[Reg.scala 28:19]
|
|
_T_7074 <= _T_7062 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][52] <= _T_7074 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7075 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7076 = eq(_T_7075, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7077 = and(ic_valid_ff, _T_7076) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7078 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7079 = and(_T_7077, _T_7078) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7080 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7081 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7082 = and(_T_7080, _T_7081) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7083 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7084 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7085 = and(_T_7083, _T_7084) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7086 = or(_T_7082, _T_7085) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7087 = or(_T_7086, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7088 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7089 = and(_T_7087, _T_7088) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7090 = bits(_T_7089, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7091 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7090 : @[Reg.scala 28:19]
|
|
_T_7091 <= _T_7079 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][53] <= _T_7091 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7092 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7093 = eq(_T_7092, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7094 = and(ic_valid_ff, _T_7093) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7095 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7096 = and(_T_7094, _T_7095) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7097 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7098 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7099 = and(_T_7097, _T_7098) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7100 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7101 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7102 = and(_T_7100, _T_7101) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7103 = or(_T_7099, _T_7102) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7104 = or(_T_7103, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7105 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7106 = and(_T_7104, _T_7105) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7107 = bits(_T_7106, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7108 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7107 : @[Reg.scala 28:19]
|
|
_T_7108 <= _T_7096 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][54] <= _T_7108 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7109 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7110 = eq(_T_7109, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7111 = and(ic_valid_ff, _T_7110) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7112 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7113 = and(_T_7111, _T_7112) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7114 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7115 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7116 = and(_T_7114, _T_7115) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7117 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7118 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7119 = and(_T_7117, _T_7118) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7120 = or(_T_7116, _T_7119) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7121 = or(_T_7120, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7122 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7123 = and(_T_7121, _T_7122) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7124 = bits(_T_7123, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7125 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7124 : @[Reg.scala 28:19]
|
|
_T_7125 <= _T_7113 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][55] <= _T_7125 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7126 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7127 = eq(_T_7126, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7128 = and(ic_valid_ff, _T_7127) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7129 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7130 = and(_T_7128, _T_7129) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7131 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7132 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7133 = and(_T_7131, _T_7132) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7134 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7135 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7136 = and(_T_7134, _T_7135) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7137 = or(_T_7133, _T_7136) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7138 = or(_T_7137, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7139 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7140 = and(_T_7138, _T_7139) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7141 = bits(_T_7140, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7142 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7141 : @[Reg.scala 28:19]
|
|
_T_7142 <= _T_7130 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][56] <= _T_7142 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7143 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7144 = eq(_T_7143, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7145 = and(ic_valid_ff, _T_7144) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7146 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7147 = and(_T_7145, _T_7146) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7148 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7149 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7150 = and(_T_7148, _T_7149) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7151 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7152 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7153 = and(_T_7151, _T_7152) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7154 = or(_T_7150, _T_7153) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7155 = or(_T_7154, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7156 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7157 = and(_T_7155, _T_7156) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7158 = bits(_T_7157, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7159 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7158 : @[Reg.scala 28:19]
|
|
_T_7159 <= _T_7147 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][57] <= _T_7159 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7160 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7161 = eq(_T_7160, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7162 = and(ic_valid_ff, _T_7161) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7163 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7164 = and(_T_7162, _T_7163) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7165 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7166 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7167 = and(_T_7165, _T_7166) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7168 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7169 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7170 = and(_T_7168, _T_7169) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7171 = or(_T_7167, _T_7170) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7172 = or(_T_7171, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7173 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7174 = and(_T_7172, _T_7173) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7175 = bits(_T_7174, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7176 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7175 : @[Reg.scala 28:19]
|
|
_T_7176 <= _T_7164 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][58] <= _T_7176 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7177 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7178 = eq(_T_7177, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7179 = and(ic_valid_ff, _T_7178) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7180 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7181 = and(_T_7179, _T_7180) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7182 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7183 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7184 = and(_T_7182, _T_7183) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7185 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7186 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7187 = and(_T_7185, _T_7186) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7188 = or(_T_7184, _T_7187) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7189 = or(_T_7188, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7190 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7191 = and(_T_7189, _T_7190) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7192 = bits(_T_7191, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7193 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7192 : @[Reg.scala 28:19]
|
|
_T_7193 <= _T_7181 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][59] <= _T_7193 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7194 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7195 = eq(_T_7194, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7196 = and(ic_valid_ff, _T_7195) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7197 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7198 = and(_T_7196, _T_7197) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7199 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7200 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7201 = and(_T_7199, _T_7200) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7202 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7203 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7204 = and(_T_7202, _T_7203) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7205 = or(_T_7201, _T_7204) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7206 = or(_T_7205, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7207 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7208 = and(_T_7206, _T_7207) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7209 = bits(_T_7208, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7210 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7209 : @[Reg.scala 28:19]
|
|
_T_7210 <= _T_7198 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][60] <= _T_7210 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7211 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7212 = eq(_T_7211, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7213 = and(ic_valid_ff, _T_7212) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7214 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7215 = and(_T_7213, _T_7214) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7216 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7217 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7218 = and(_T_7216, _T_7217) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7219 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7220 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7221 = and(_T_7219, _T_7220) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7222 = or(_T_7218, _T_7221) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7223 = or(_T_7222, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7224 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7225 = and(_T_7223, _T_7224) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7226 = bits(_T_7225, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7227 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7226 : @[Reg.scala 28:19]
|
|
_T_7227 <= _T_7215 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][61] <= _T_7227 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7228 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7229 = eq(_T_7228, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7230 = and(ic_valid_ff, _T_7229) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7231 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7232 = and(_T_7230, _T_7231) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7233 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7234 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7235 = and(_T_7233, _T_7234) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7236 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7237 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7238 = and(_T_7236, _T_7237) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7239 = or(_T_7235, _T_7238) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7240 = or(_T_7239, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7241 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7242 = and(_T_7240, _T_7241) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7243 = bits(_T_7242, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7244 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7243 : @[Reg.scala 28:19]
|
|
_T_7244 <= _T_7232 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][62] <= _T_7244 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7245 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7246 = eq(_T_7245, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7247 = and(ic_valid_ff, _T_7246) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7248 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7249 = and(_T_7247, _T_7248) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7250 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7251 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7252 = and(_T_7250, _T_7251) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7253 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7254 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7255 = and(_T_7253, _T_7254) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7256 = or(_T_7252, _T_7255) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7257 = or(_T_7256, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7258 = bits(tag_valid_clken_1, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7259 = and(_T_7257, _T_7258) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7260 = bits(_T_7259, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7261 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7260 : @[Reg.scala 28:19]
|
|
_T_7261 <= _T_7249 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][63] <= _T_7261 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7262 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7263 = eq(_T_7262, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7264 = and(ic_valid_ff, _T_7263) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7265 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7266 = and(_T_7264, _T_7265) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7267 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7268 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7269 = and(_T_7267, _T_7268) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7270 = eq(perr_ic_index_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7271 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7272 = and(_T_7270, _T_7271) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7273 = or(_T_7269, _T_7272) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7274 = or(_T_7273, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7275 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7276 = and(_T_7274, _T_7275) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7277 = bits(_T_7276, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7278 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7277 : @[Reg.scala 28:19]
|
|
_T_7278 <= _T_7266 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][32] <= _T_7278 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7279 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7280 = eq(_T_7279, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7281 = and(ic_valid_ff, _T_7280) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7282 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7283 = and(_T_7281, _T_7282) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7284 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7285 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7286 = and(_T_7284, _T_7285) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7287 = eq(perr_ic_index_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7288 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7289 = and(_T_7287, _T_7288) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7290 = or(_T_7286, _T_7289) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7291 = or(_T_7290, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7292 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7293 = and(_T_7291, _T_7292) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7294 = bits(_T_7293, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7295 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7294 : @[Reg.scala 28:19]
|
|
_T_7295 <= _T_7283 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][33] <= _T_7295 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7296 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7297 = eq(_T_7296, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7298 = and(ic_valid_ff, _T_7297) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7299 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7300 = and(_T_7298, _T_7299) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7301 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7302 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7303 = and(_T_7301, _T_7302) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7304 = eq(perr_ic_index_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7305 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7306 = and(_T_7304, _T_7305) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7307 = or(_T_7303, _T_7306) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7308 = or(_T_7307, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7309 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7310 = and(_T_7308, _T_7309) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7311 = bits(_T_7310, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7312 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7311 : @[Reg.scala 28:19]
|
|
_T_7312 <= _T_7300 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][34] <= _T_7312 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7313 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7314 = eq(_T_7313, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7315 = and(ic_valid_ff, _T_7314) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7316 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7317 = and(_T_7315, _T_7316) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7318 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7319 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7320 = and(_T_7318, _T_7319) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7321 = eq(perr_ic_index_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7322 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7323 = and(_T_7321, _T_7322) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7324 = or(_T_7320, _T_7323) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7325 = or(_T_7324, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7326 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7327 = and(_T_7325, _T_7326) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7328 = bits(_T_7327, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7329 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7328 : @[Reg.scala 28:19]
|
|
_T_7329 <= _T_7317 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][35] <= _T_7329 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7330 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7331 = eq(_T_7330, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7332 = and(ic_valid_ff, _T_7331) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7333 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7334 = and(_T_7332, _T_7333) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7335 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7336 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7337 = and(_T_7335, _T_7336) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7338 = eq(perr_ic_index_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7339 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7340 = and(_T_7338, _T_7339) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7341 = or(_T_7337, _T_7340) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7342 = or(_T_7341, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7343 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7344 = and(_T_7342, _T_7343) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7345 = bits(_T_7344, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7346 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7345 : @[Reg.scala 28:19]
|
|
_T_7346 <= _T_7334 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][36] <= _T_7346 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7347 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7348 = eq(_T_7347, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7349 = and(ic_valid_ff, _T_7348) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7350 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7351 = and(_T_7349, _T_7350) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7352 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7353 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7354 = and(_T_7352, _T_7353) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7355 = eq(perr_ic_index_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7356 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7357 = and(_T_7355, _T_7356) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7358 = or(_T_7354, _T_7357) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7359 = or(_T_7358, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7360 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7361 = and(_T_7359, _T_7360) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7362 = bits(_T_7361, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7363 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7362 : @[Reg.scala 28:19]
|
|
_T_7363 <= _T_7351 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][37] <= _T_7363 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7364 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7365 = eq(_T_7364, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7366 = and(ic_valid_ff, _T_7365) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7367 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7368 = and(_T_7366, _T_7367) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7369 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7370 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7371 = and(_T_7369, _T_7370) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7372 = eq(perr_ic_index_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7373 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7374 = and(_T_7372, _T_7373) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7375 = or(_T_7371, _T_7374) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7376 = or(_T_7375, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7377 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7378 = and(_T_7376, _T_7377) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7379 = bits(_T_7378, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7380 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7379 : @[Reg.scala 28:19]
|
|
_T_7380 <= _T_7368 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][38] <= _T_7380 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7381 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7382 = eq(_T_7381, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7383 = and(ic_valid_ff, _T_7382) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7384 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7385 = and(_T_7383, _T_7384) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7386 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7387 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7388 = and(_T_7386, _T_7387) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7389 = eq(perr_ic_index_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7390 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7391 = and(_T_7389, _T_7390) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7392 = or(_T_7388, _T_7391) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7393 = or(_T_7392, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7394 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7395 = and(_T_7393, _T_7394) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7396 = bits(_T_7395, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7397 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7396 : @[Reg.scala 28:19]
|
|
_T_7397 <= _T_7385 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][39] <= _T_7397 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7398 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7399 = eq(_T_7398, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7400 = and(ic_valid_ff, _T_7399) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7401 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7402 = and(_T_7400, _T_7401) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7403 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7404 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7405 = and(_T_7403, _T_7404) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7406 = eq(perr_ic_index_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7407 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7408 = and(_T_7406, _T_7407) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7409 = or(_T_7405, _T_7408) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7410 = or(_T_7409, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7411 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7412 = and(_T_7410, _T_7411) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7413 = bits(_T_7412, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7414 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7413 : @[Reg.scala 28:19]
|
|
_T_7414 <= _T_7402 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][40] <= _T_7414 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7415 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7416 = eq(_T_7415, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7417 = and(ic_valid_ff, _T_7416) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7418 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7419 = and(_T_7417, _T_7418) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7420 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7421 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7422 = and(_T_7420, _T_7421) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7423 = eq(perr_ic_index_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7424 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7425 = and(_T_7423, _T_7424) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7426 = or(_T_7422, _T_7425) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7427 = or(_T_7426, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7428 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7429 = and(_T_7427, _T_7428) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7430 = bits(_T_7429, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7431 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7430 : @[Reg.scala 28:19]
|
|
_T_7431 <= _T_7419 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][41] <= _T_7431 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7432 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7433 = eq(_T_7432, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7434 = and(ic_valid_ff, _T_7433) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7435 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7436 = and(_T_7434, _T_7435) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7437 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7438 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7439 = and(_T_7437, _T_7438) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7440 = eq(perr_ic_index_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7441 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7442 = and(_T_7440, _T_7441) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7443 = or(_T_7439, _T_7442) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7444 = or(_T_7443, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7445 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7446 = and(_T_7444, _T_7445) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7447 = bits(_T_7446, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7448 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7447 : @[Reg.scala 28:19]
|
|
_T_7448 <= _T_7436 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][42] <= _T_7448 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7449 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7450 = eq(_T_7449, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7451 = and(ic_valid_ff, _T_7450) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7452 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7453 = and(_T_7451, _T_7452) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7454 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7455 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7456 = and(_T_7454, _T_7455) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7457 = eq(perr_ic_index_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7458 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7459 = and(_T_7457, _T_7458) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7460 = or(_T_7456, _T_7459) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7461 = or(_T_7460, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7462 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7463 = and(_T_7461, _T_7462) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7464 = bits(_T_7463, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7465 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7464 : @[Reg.scala 28:19]
|
|
_T_7465 <= _T_7453 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][43] <= _T_7465 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7466 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7467 = eq(_T_7466, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7468 = and(ic_valid_ff, _T_7467) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7469 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7470 = and(_T_7468, _T_7469) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7471 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7472 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7473 = and(_T_7471, _T_7472) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7474 = eq(perr_ic_index_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7475 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7476 = and(_T_7474, _T_7475) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7477 = or(_T_7473, _T_7476) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7478 = or(_T_7477, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7479 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7480 = and(_T_7478, _T_7479) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7481 = bits(_T_7480, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7482 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7481 : @[Reg.scala 28:19]
|
|
_T_7482 <= _T_7470 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][44] <= _T_7482 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7483 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7484 = eq(_T_7483, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7485 = and(ic_valid_ff, _T_7484) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7486 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7487 = and(_T_7485, _T_7486) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7488 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7489 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7490 = and(_T_7488, _T_7489) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7491 = eq(perr_ic_index_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7492 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7493 = and(_T_7491, _T_7492) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7494 = or(_T_7490, _T_7493) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7495 = or(_T_7494, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7496 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7497 = and(_T_7495, _T_7496) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7498 = bits(_T_7497, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7499 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7498 : @[Reg.scala 28:19]
|
|
_T_7499 <= _T_7487 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][45] <= _T_7499 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7500 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7501 = eq(_T_7500, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7502 = and(ic_valid_ff, _T_7501) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7503 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7504 = and(_T_7502, _T_7503) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7505 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7506 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7507 = and(_T_7505, _T_7506) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7508 = eq(perr_ic_index_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7509 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7510 = and(_T_7508, _T_7509) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7511 = or(_T_7507, _T_7510) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7512 = or(_T_7511, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7513 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7514 = and(_T_7512, _T_7513) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7515 = bits(_T_7514, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7516 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7515 : @[Reg.scala 28:19]
|
|
_T_7516 <= _T_7504 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][46] <= _T_7516 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7517 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7518 = eq(_T_7517, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7519 = and(ic_valid_ff, _T_7518) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7520 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7521 = and(_T_7519, _T_7520) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7522 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7523 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7524 = and(_T_7522, _T_7523) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7525 = eq(perr_ic_index_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7526 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7527 = and(_T_7525, _T_7526) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7528 = or(_T_7524, _T_7527) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7529 = or(_T_7528, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7530 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7531 = and(_T_7529, _T_7530) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7532 = bits(_T_7531, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7533 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7532 : @[Reg.scala 28:19]
|
|
_T_7533 <= _T_7521 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][47] <= _T_7533 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7534 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7535 = eq(_T_7534, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7536 = and(ic_valid_ff, _T_7535) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7537 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7538 = and(_T_7536, _T_7537) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7539 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7540 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7541 = and(_T_7539, _T_7540) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7542 = eq(perr_ic_index_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7543 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7544 = and(_T_7542, _T_7543) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7545 = or(_T_7541, _T_7544) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7546 = or(_T_7545, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7547 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7548 = and(_T_7546, _T_7547) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7549 = bits(_T_7548, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7550 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7549 : @[Reg.scala 28:19]
|
|
_T_7550 <= _T_7538 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][48] <= _T_7550 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7551 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7552 = eq(_T_7551, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7553 = and(ic_valid_ff, _T_7552) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7554 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7555 = and(_T_7553, _T_7554) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7556 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7557 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7558 = and(_T_7556, _T_7557) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7559 = eq(perr_ic_index_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7560 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7561 = and(_T_7559, _T_7560) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7562 = or(_T_7558, _T_7561) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7563 = or(_T_7562, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7564 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7565 = and(_T_7563, _T_7564) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7566 = bits(_T_7565, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7567 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7566 : @[Reg.scala 28:19]
|
|
_T_7567 <= _T_7555 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][49] <= _T_7567 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7568 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7569 = eq(_T_7568, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7570 = and(ic_valid_ff, _T_7569) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7571 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7572 = and(_T_7570, _T_7571) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7573 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7574 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7575 = and(_T_7573, _T_7574) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7576 = eq(perr_ic_index_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7577 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7578 = and(_T_7576, _T_7577) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7579 = or(_T_7575, _T_7578) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7580 = or(_T_7579, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7581 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7582 = and(_T_7580, _T_7581) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7583 = bits(_T_7582, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7584 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7583 : @[Reg.scala 28:19]
|
|
_T_7584 <= _T_7572 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][50] <= _T_7584 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7585 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7586 = eq(_T_7585, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7587 = and(ic_valid_ff, _T_7586) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7588 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7589 = and(_T_7587, _T_7588) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7590 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7591 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7592 = and(_T_7590, _T_7591) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7593 = eq(perr_ic_index_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7594 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7595 = and(_T_7593, _T_7594) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7596 = or(_T_7592, _T_7595) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7597 = or(_T_7596, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7598 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7599 = and(_T_7597, _T_7598) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7600 = bits(_T_7599, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7601 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7600 : @[Reg.scala 28:19]
|
|
_T_7601 <= _T_7589 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][51] <= _T_7601 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7602 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7603 = eq(_T_7602, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7604 = and(ic_valid_ff, _T_7603) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7605 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7606 = and(_T_7604, _T_7605) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7607 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7608 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7609 = and(_T_7607, _T_7608) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7610 = eq(perr_ic_index_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7611 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7612 = and(_T_7610, _T_7611) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7613 = or(_T_7609, _T_7612) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7614 = or(_T_7613, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7615 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7616 = and(_T_7614, _T_7615) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7617 = bits(_T_7616, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7618 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7617 : @[Reg.scala 28:19]
|
|
_T_7618 <= _T_7606 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][52] <= _T_7618 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7619 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7620 = eq(_T_7619, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7621 = and(ic_valid_ff, _T_7620) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7622 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7623 = and(_T_7621, _T_7622) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7624 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7625 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7626 = and(_T_7624, _T_7625) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7627 = eq(perr_ic_index_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7628 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7629 = and(_T_7627, _T_7628) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7630 = or(_T_7626, _T_7629) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7631 = or(_T_7630, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7632 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7633 = and(_T_7631, _T_7632) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7634 = bits(_T_7633, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7635 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7634 : @[Reg.scala 28:19]
|
|
_T_7635 <= _T_7623 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][53] <= _T_7635 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7636 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7637 = eq(_T_7636, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7638 = and(ic_valid_ff, _T_7637) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7639 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7640 = and(_T_7638, _T_7639) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7641 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7642 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7643 = and(_T_7641, _T_7642) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7644 = eq(perr_ic_index_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7645 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7646 = and(_T_7644, _T_7645) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7647 = or(_T_7643, _T_7646) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7648 = or(_T_7647, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7649 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7650 = and(_T_7648, _T_7649) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7651 = bits(_T_7650, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7652 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7651 : @[Reg.scala 28:19]
|
|
_T_7652 <= _T_7640 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][54] <= _T_7652 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7653 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7654 = eq(_T_7653, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7655 = and(ic_valid_ff, _T_7654) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7656 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7657 = and(_T_7655, _T_7656) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7658 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7659 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7660 = and(_T_7658, _T_7659) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7661 = eq(perr_ic_index_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7662 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7663 = and(_T_7661, _T_7662) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7664 = or(_T_7660, _T_7663) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7665 = or(_T_7664, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7666 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7667 = and(_T_7665, _T_7666) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7668 = bits(_T_7667, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7669 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7668 : @[Reg.scala 28:19]
|
|
_T_7669 <= _T_7657 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][55] <= _T_7669 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7670 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7671 = eq(_T_7670, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7672 = and(ic_valid_ff, _T_7671) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7673 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7674 = and(_T_7672, _T_7673) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7675 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7676 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7677 = and(_T_7675, _T_7676) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7678 = eq(perr_ic_index_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7679 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7680 = and(_T_7678, _T_7679) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7681 = or(_T_7677, _T_7680) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7682 = or(_T_7681, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7683 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7684 = and(_T_7682, _T_7683) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7685 = bits(_T_7684, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7686 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7685 : @[Reg.scala 28:19]
|
|
_T_7686 <= _T_7674 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][56] <= _T_7686 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7687 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7688 = eq(_T_7687, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7689 = and(ic_valid_ff, _T_7688) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7690 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7691 = and(_T_7689, _T_7690) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7692 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7693 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7694 = and(_T_7692, _T_7693) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7695 = eq(perr_ic_index_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7696 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7697 = and(_T_7695, _T_7696) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7698 = or(_T_7694, _T_7697) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7699 = or(_T_7698, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7700 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7701 = and(_T_7699, _T_7700) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7702 = bits(_T_7701, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7703 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7702 : @[Reg.scala 28:19]
|
|
_T_7703 <= _T_7691 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][57] <= _T_7703 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7704 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7705 = eq(_T_7704, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7706 = and(ic_valid_ff, _T_7705) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7707 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7708 = and(_T_7706, _T_7707) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7709 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7710 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7711 = and(_T_7709, _T_7710) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7712 = eq(perr_ic_index_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7713 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7714 = and(_T_7712, _T_7713) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7715 = or(_T_7711, _T_7714) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7716 = or(_T_7715, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7717 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7718 = and(_T_7716, _T_7717) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7719 = bits(_T_7718, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7720 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7719 : @[Reg.scala 28:19]
|
|
_T_7720 <= _T_7708 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][58] <= _T_7720 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7721 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7722 = eq(_T_7721, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7723 = and(ic_valid_ff, _T_7722) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7724 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7725 = and(_T_7723, _T_7724) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7726 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7727 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7728 = and(_T_7726, _T_7727) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7729 = eq(perr_ic_index_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7730 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7731 = and(_T_7729, _T_7730) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7732 = or(_T_7728, _T_7731) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7733 = or(_T_7732, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7734 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7735 = and(_T_7733, _T_7734) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7736 = bits(_T_7735, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7737 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7736 : @[Reg.scala 28:19]
|
|
_T_7737 <= _T_7725 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][59] <= _T_7737 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7738 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7739 = eq(_T_7738, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7740 = and(ic_valid_ff, _T_7739) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7741 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7742 = and(_T_7740, _T_7741) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7743 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7744 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7745 = and(_T_7743, _T_7744) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7746 = eq(perr_ic_index_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7747 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7748 = and(_T_7746, _T_7747) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7749 = or(_T_7745, _T_7748) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7750 = or(_T_7749, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7751 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7752 = and(_T_7750, _T_7751) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7753 = bits(_T_7752, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7754 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7753 : @[Reg.scala 28:19]
|
|
_T_7754 <= _T_7742 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][60] <= _T_7754 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7755 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7756 = eq(_T_7755, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7757 = and(ic_valid_ff, _T_7756) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7758 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7759 = and(_T_7757, _T_7758) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7760 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7761 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7762 = and(_T_7760, _T_7761) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7763 = eq(perr_ic_index_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7764 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7765 = and(_T_7763, _T_7764) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7766 = or(_T_7762, _T_7765) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7767 = or(_T_7766, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7768 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7769 = and(_T_7767, _T_7768) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7770 = bits(_T_7769, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7771 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7770 : @[Reg.scala 28:19]
|
|
_T_7771 <= _T_7759 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][61] <= _T_7771 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7772 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7773 = eq(_T_7772, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7774 = and(ic_valid_ff, _T_7773) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7775 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7776 = and(_T_7774, _T_7775) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7777 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7778 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7779 = and(_T_7777, _T_7778) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7780 = eq(perr_ic_index_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7781 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7782 = and(_T_7780, _T_7781) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7783 = or(_T_7779, _T_7782) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7784 = or(_T_7783, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7785 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7786 = and(_T_7784, _T_7785) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7787 = bits(_T_7786, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7788 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7787 : @[Reg.scala 28:19]
|
|
_T_7788 <= _T_7776 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][62] <= _T_7788 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7789 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7790 = eq(_T_7789, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7791 = and(ic_valid_ff, _T_7790) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7792 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7793 = and(_T_7791, _T_7792) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7794 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7795 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7796 = and(_T_7794, _T_7795) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7797 = eq(perr_ic_index_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7798 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7799 = and(_T_7797, _T_7798) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7800 = or(_T_7796, _T_7799) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7801 = or(_T_7800, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7802 = bits(tag_valid_clken_1, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7803 = and(_T_7801, _T_7802) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7804 = bits(_T_7803, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7805 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7804 : @[Reg.scala 28:19]
|
|
_T_7805 <= _T_7793 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][63] <= _T_7805 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7806 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7807 = eq(_T_7806, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7808 = and(ic_valid_ff, _T_7807) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7809 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7810 = and(_T_7808, _T_7809) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7811 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7812 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7813 = and(_T_7811, _T_7812) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7814 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7815 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7816 = and(_T_7814, _T_7815) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7817 = or(_T_7813, _T_7816) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7818 = or(_T_7817, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7819 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7820 = and(_T_7818, _T_7819) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7821 = bits(_T_7820, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7822 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7821 : @[Reg.scala 28:19]
|
|
_T_7822 <= _T_7810 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][64] <= _T_7822 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7823 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7824 = eq(_T_7823, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7825 = and(ic_valid_ff, _T_7824) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7826 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7827 = and(_T_7825, _T_7826) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7828 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7829 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7830 = and(_T_7828, _T_7829) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7831 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7832 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7833 = and(_T_7831, _T_7832) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7834 = or(_T_7830, _T_7833) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7835 = or(_T_7834, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7836 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7837 = and(_T_7835, _T_7836) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7838 = bits(_T_7837, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7839 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7838 : @[Reg.scala 28:19]
|
|
_T_7839 <= _T_7827 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][65] <= _T_7839 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7840 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7841 = eq(_T_7840, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7842 = and(ic_valid_ff, _T_7841) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7843 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7844 = and(_T_7842, _T_7843) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7845 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7846 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7847 = and(_T_7845, _T_7846) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7848 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7849 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7850 = and(_T_7848, _T_7849) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7851 = or(_T_7847, _T_7850) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7852 = or(_T_7851, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7853 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7854 = and(_T_7852, _T_7853) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7855 = bits(_T_7854, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7856 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7855 : @[Reg.scala 28:19]
|
|
_T_7856 <= _T_7844 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][66] <= _T_7856 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7857 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7858 = eq(_T_7857, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7859 = and(ic_valid_ff, _T_7858) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7860 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7861 = and(_T_7859, _T_7860) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7862 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7863 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7864 = and(_T_7862, _T_7863) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7865 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7866 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7867 = and(_T_7865, _T_7866) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7868 = or(_T_7864, _T_7867) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7869 = or(_T_7868, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7870 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7871 = and(_T_7869, _T_7870) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7872 = bits(_T_7871, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7873 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7872 : @[Reg.scala 28:19]
|
|
_T_7873 <= _T_7861 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][67] <= _T_7873 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7874 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7875 = eq(_T_7874, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7876 = and(ic_valid_ff, _T_7875) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7877 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7878 = and(_T_7876, _T_7877) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7879 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7880 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7881 = and(_T_7879, _T_7880) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7882 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7883 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7884 = and(_T_7882, _T_7883) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7885 = or(_T_7881, _T_7884) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7886 = or(_T_7885, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7887 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7888 = and(_T_7886, _T_7887) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7889 = bits(_T_7888, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7890 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7889 : @[Reg.scala 28:19]
|
|
_T_7890 <= _T_7878 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][68] <= _T_7890 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7891 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7892 = eq(_T_7891, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7893 = and(ic_valid_ff, _T_7892) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7894 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7895 = and(_T_7893, _T_7894) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7896 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7897 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7898 = and(_T_7896, _T_7897) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7899 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7900 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7901 = and(_T_7899, _T_7900) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7902 = or(_T_7898, _T_7901) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7903 = or(_T_7902, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7904 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7905 = and(_T_7903, _T_7904) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7906 = bits(_T_7905, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7907 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7906 : @[Reg.scala 28:19]
|
|
_T_7907 <= _T_7895 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][69] <= _T_7907 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7908 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7909 = eq(_T_7908, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7910 = and(ic_valid_ff, _T_7909) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7911 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7912 = and(_T_7910, _T_7911) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7913 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7914 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7915 = and(_T_7913, _T_7914) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7916 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7917 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7918 = and(_T_7916, _T_7917) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7919 = or(_T_7915, _T_7918) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7920 = or(_T_7919, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7921 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7922 = and(_T_7920, _T_7921) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7923 = bits(_T_7922, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7924 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7923 : @[Reg.scala 28:19]
|
|
_T_7924 <= _T_7912 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][70] <= _T_7924 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7925 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7926 = eq(_T_7925, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7927 = and(ic_valid_ff, _T_7926) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7928 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7929 = and(_T_7927, _T_7928) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7930 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7931 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7932 = and(_T_7930, _T_7931) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7933 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7934 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7935 = and(_T_7933, _T_7934) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7936 = or(_T_7932, _T_7935) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7937 = or(_T_7936, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7938 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7939 = and(_T_7937, _T_7938) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7940 = bits(_T_7939, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7941 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7940 : @[Reg.scala 28:19]
|
|
_T_7941 <= _T_7929 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][71] <= _T_7941 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7942 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7943 = eq(_T_7942, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7944 = and(ic_valid_ff, _T_7943) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7945 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7946 = and(_T_7944, _T_7945) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7947 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7948 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7949 = and(_T_7947, _T_7948) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7950 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7951 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7952 = and(_T_7950, _T_7951) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7953 = or(_T_7949, _T_7952) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7954 = or(_T_7953, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7955 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7956 = and(_T_7954, _T_7955) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7957 = bits(_T_7956, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7958 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7957 : @[Reg.scala 28:19]
|
|
_T_7958 <= _T_7946 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][72] <= _T_7958 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7959 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7960 = eq(_T_7959, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7961 = and(ic_valid_ff, _T_7960) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7962 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7963 = and(_T_7961, _T_7962) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7964 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7965 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7966 = and(_T_7964, _T_7965) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7967 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7968 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7969 = and(_T_7967, _T_7968) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7970 = or(_T_7966, _T_7969) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7971 = or(_T_7970, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7972 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7973 = and(_T_7971, _T_7972) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7974 = bits(_T_7973, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7975 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7974 : @[Reg.scala 28:19]
|
|
_T_7975 <= _T_7963 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][73] <= _T_7975 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7976 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7977 = eq(_T_7976, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7978 = and(ic_valid_ff, _T_7977) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7979 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7980 = and(_T_7978, _T_7979) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7981 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7982 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_7983 = and(_T_7981, _T_7982) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_7984 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_7985 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_7986 = and(_T_7984, _T_7985) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_7987 = or(_T_7983, _T_7986) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_7988 = or(_T_7987, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_7989 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_7990 = and(_T_7988, _T_7989) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_7991 = bits(_T_7990, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_7992 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_7991 : @[Reg.scala 28:19]
|
|
_T_7992 <= _T_7980 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][74] <= _T_7992 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_7993 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_7994 = eq(_T_7993, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_7995 = and(ic_valid_ff, _T_7994) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_7996 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_7997 = and(_T_7995, _T_7996) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_7998 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_7999 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8000 = and(_T_7998, _T_7999) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8001 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8002 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8003 = and(_T_8001, _T_8002) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8004 = or(_T_8000, _T_8003) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8005 = or(_T_8004, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8006 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8007 = and(_T_8005, _T_8006) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8008 = bits(_T_8007, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8009 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8008 : @[Reg.scala 28:19]
|
|
_T_8009 <= _T_7997 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][75] <= _T_8009 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8010 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8011 = eq(_T_8010, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8012 = and(ic_valid_ff, _T_8011) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8013 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8014 = and(_T_8012, _T_8013) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8015 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8016 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8017 = and(_T_8015, _T_8016) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8018 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8019 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8020 = and(_T_8018, _T_8019) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8021 = or(_T_8017, _T_8020) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8022 = or(_T_8021, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8023 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8024 = and(_T_8022, _T_8023) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8025 = bits(_T_8024, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8026 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8025 : @[Reg.scala 28:19]
|
|
_T_8026 <= _T_8014 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][76] <= _T_8026 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8027 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8028 = eq(_T_8027, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8029 = and(ic_valid_ff, _T_8028) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8030 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8031 = and(_T_8029, _T_8030) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8032 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8033 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8034 = and(_T_8032, _T_8033) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8035 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8036 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8037 = and(_T_8035, _T_8036) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8038 = or(_T_8034, _T_8037) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8039 = or(_T_8038, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8040 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8041 = and(_T_8039, _T_8040) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8042 = bits(_T_8041, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8043 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8042 : @[Reg.scala 28:19]
|
|
_T_8043 <= _T_8031 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][77] <= _T_8043 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8044 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8045 = eq(_T_8044, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8046 = and(ic_valid_ff, _T_8045) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8047 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8048 = and(_T_8046, _T_8047) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8049 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8050 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8051 = and(_T_8049, _T_8050) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8052 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8053 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8054 = and(_T_8052, _T_8053) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8055 = or(_T_8051, _T_8054) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8056 = or(_T_8055, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8057 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8058 = and(_T_8056, _T_8057) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8059 = bits(_T_8058, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8060 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8059 : @[Reg.scala 28:19]
|
|
_T_8060 <= _T_8048 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][78] <= _T_8060 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8061 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8062 = eq(_T_8061, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8063 = and(ic_valid_ff, _T_8062) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8064 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8065 = and(_T_8063, _T_8064) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8066 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8067 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8068 = and(_T_8066, _T_8067) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8069 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8070 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8071 = and(_T_8069, _T_8070) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8072 = or(_T_8068, _T_8071) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8073 = or(_T_8072, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8074 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8075 = and(_T_8073, _T_8074) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8076 = bits(_T_8075, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8077 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8076 : @[Reg.scala 28:19]
|
|
_T_8077 <= _T_8065 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][79] <= _T_8077 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8078 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8079 = eq(_T_8078, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8080 = and(ic_valid_ff, _T_8079) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8081 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8082 = and(_T_8080, _T_8081) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8083 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8084 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8085 = and(_T_8083, _T_8084) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8086 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8087 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8088 = and(_T_8086, _T_8087) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8089 = or(_T_8085, _T_8088) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8090 = or(_T_8089, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8091 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8092 = and(_T_8090, _T_8091) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8093 = bits(_T_8092, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8094 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8093 : @[Reg.scala 28:19]
|
|
_T_8094 <= _T_8082 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][80] <= _T_8094 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8095 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8096 = eq(_T_8095, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8097 = and(ic_valid_ff, _T_8096) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8098 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8099 = and(_T_8097, _T_8098) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8100 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8101 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8102 = and(_T_8100, _T_8101) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8103 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8104 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8105 = and(_T_8103, _T_8104) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8106 = or(_T_8102, _T_8105) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8107 = or(_T_8106, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8108 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8109 = and(_T_8107, _T_8108) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8110 = bits(_T_8109, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8111 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8110 : @[Reg.scala 28:19]
|
|
_T_8111 <= _T_8099 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][81] <= _T_8111 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8112 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8113 = eq(_T_8112, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8114 = and(ic_valid_ff, _T_8113) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8115 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8116 = and(_T_8114, _T_8115) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8117 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8118 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8119 = and(_T_8117, _T_8118) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8120 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8121 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8122 = and(_T_8120, _T_8121) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8123 = or(_T_8119, _T_8122) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8124 = or(_T_8123, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8125 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8126 = and(_T_8124, _T_8125) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8127 = bits(_T_8126, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8128 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8127 : @[Reg.scala 28:19]
|
|
_T_8128 <= _T_8116 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][82] <= _T_8128 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8129 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8130 = eq(_T_8129, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8131 = and(ic_valid_ff, _T_8130) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8132 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8133 = and(_T_8131, _T_8132) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8134 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8135 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8136 = and(_T_8134, _T_8135) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8137 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8138 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8139 = and(_T_8137, _T_8138) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8140 = or(_T_8136, _T_8139) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8141 = or(_T_8140, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8142 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8143 = and(_T_8141, _T_8142) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8144 = bits(_T_8143, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8145 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8144 : @[Reg.scala 28:19]
|
|
_T_8145 <= _T_8133 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][83] <= _T_8145 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8146 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8147 = eq(_T_8146, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8148 = and(ic_valid_ff, _T_8147) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8149 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8150 = and(_T_8148, _T_8149) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8151 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8152 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8153 = and(_T_8151, _T_8152) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8154 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8155 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8156 = and(_T_8154, _T_8155) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8157 = or(_T_8153, _T_8156) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8158 = or(_T_8157, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8159 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8160 = and(_T_8158, _T_8159) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8161 = bits(_T_8160, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8162 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8161 : @[Reg.scala 28:19]
|
|
_T_8162 <= _T_8150 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][84] <= _T_8162 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8163 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8164 = eq(_T_8163, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8165 = and(ic_valid_ff, _T_8164) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8166 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8167 = and(_T_8165, _T_8166) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8168 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8169 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8170 = and(_T_8168, _T_8169) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8171 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8172 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8173 = and(_T_8171, _T_8172) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8174 = or(_T_8170, _T_8173) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8175 = or(_T_8174, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8176 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8177 = and(_T_8175, _T_8176) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8178 = bits(_T_8177, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8179 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8178 : @[Reg.scala 28:19]
|
|
_T_8179 <= _T_8167 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][85] <= _T_8179 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8180 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8181 = eq(_T_8180, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8182 = and(ic_valid_ff, _T_8181) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8183 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8184 = and(_T_8182, _T_8183) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8185 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8186 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8187 = and(_T_8185, _T_8186) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8188 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8189 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8190 = and(_T_8188, _T_8189) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8191 = or(_T_8187, _T_8190) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8192 = or(_T_8191, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8193 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8194 = and(_T_8192, _T_8193) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8195 = bits(_T_8194, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8196 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8195 : @[Reg.scala 28:19]
|
|
_T_8196 <= _T_8184 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][86] <= _T_8196 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8197 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8198 = eq(_T_8197, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8199 = and(ic_valid_ff, _T_8198) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8200 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8201 = and(_T_8199, _T_8200) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8203 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8204 = and(_T_8202, _T_8203) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8205 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8206 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8207 = and(_T_8205, _T_8206) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8208 = or(_T_8204, _T_8207) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8209 = or(_T_8208, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8210 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8211 = and(_T_8209, _T_8210) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8212 = bits(_T_8211, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8213 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8212 : @[Reg.scala 28:19]
|
|
_T_8213 <= _T_8201 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][87] <= _T_8213 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8214 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8215 = eq(_T_8214, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8216 = and(ic_valid_ff, _T_8215) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8217 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8218 = and(_T_8216, _T_8217) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8219 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8220 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8221 = and(_T_8219, _T_8220) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8222 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8223 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8224 = and(_T_8222, _T_8223) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8225 = or(_T_8221, _T_8224) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8226 = or(_T_8225, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8227 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8228 = and(_T_8226, _T_8227) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8229 = bits(_T_8228, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8230 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8229 : @[Reg.scala 28:19]
|
|
_T_8230 <= _T_8218 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][88] <= _T_8230 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8231 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8232 = eq(_T_8231, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8233 = and(ic_valid_ff, _T_8232) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8234 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8235 = and(_T_8233, _T_8234) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8236 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8237 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8238 = and(_T_8236, _T_8237) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8239 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8240 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8241 = and(_T_8239, _T_8240) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8242 = or(_T_8238, _T_8241) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8243 = or(_T_8242, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8244 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8245 = and(_T_8243, _T_8244) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8246 = bits(_T_8245, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8247 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8246 : @[Reg.scala 28:19]
|
|
_T_8247 <= _T_8235 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][89] <= _T_8247 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8248 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8249 = eq(_T_8248, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8250 = and(ic_valid_ff, _T_8249) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8251 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8252 = and(_T_8250, _T_8251) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8253 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8254 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8255 = and(_T_8253, _T_8254) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8256 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8257 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8258 = and(_T_8256, _T_8257) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8259 = or(_T_8255, _T_8258) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8260 = or(_T_8259, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8261 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8262 = and(_T_8260, _T_8261) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8263 = bits(_T_8262, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8264 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8263 : @[Reg.scala 28:19]
|
|
_T_8264 <= _T_8252 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][90] <= _T_8264 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8265 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8266 = eq(_T_8265, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8267 = and(ic_valid_ff, _T_8266) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8268 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8269 = and(_T_8267, _T_8268) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8270 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8271 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8272 = and(_T_8270, _T_8271) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8273 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8274 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8275 = and(_T_8273, _T_8274) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8276 = or(_T_8272, _T_8275) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8277 = or(_T_8276, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8278 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8279 = and(_T_8277, _T_8278) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8280 = bits(_T_8279, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8281 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8280 : @[Reg.scala 28:19]
|
|
_T_8281 <= _T_8269 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][91] <= _T_8281 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8282 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8283 = eq(_T_8282, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8284 = and(ic_valid_ff, _T_8283) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8285 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8286 = and(_T_8284, _T_8285) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8287 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8288 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8289 = and(_T_8287, _T_8288) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8290 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8291 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8292 = and(_T_8290, _T_8291) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8293 = or(_T_8289, _T_8292) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8294 = or(_T_8293, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8295 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8296 = and(_T_8294, _T_8295) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8297 = bits(_T_8296, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8298 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8297 : @[Reg.scala 28:19]
|
|
_T_8298 <= _T_8286 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][92] <= _T_8298 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8299 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8300 = eq(_T_8299, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8301 = and(ic_valid_ff, _T_8300) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8302 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8303 = and(_T_8301, _T_8302) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8304 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8305 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8306 = and(_T_8304, _T_8305) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8307 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8308 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8309 = and(_T_8307, _T_8308) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8310 = or(_T_8306, _T_8309) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8311 = or(_T_8310, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8312 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8313 = and(_T_8311, _T_8312) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8314 = bits(_T_8313, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8315 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8314 : @[Reg.scala 28:19]
|
|
_T_8315 <= _T_8303 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][93] <= _T_8315 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8316 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8317 = eq(_T_8316, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8318 = and(ic_valid_ff, _T_8317) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8319 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8320 = and(_T_8318, _T_8319) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8321 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8322 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8323 = and(_T_8321, _T_8322) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8324 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8325 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8326 = and(_T_8324, _T_8325) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8327 = or(_T_8323, _T_8326) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8328 = or(_T_8327, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8329 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8330 = and(_T_8328, _T_8329) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8331 = bits(_T_8330, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8332 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8331 : @[Reg.scala 28:19]
|
|
_T_8332 <= _T_8320 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][94] <= _T_8332 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8333 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8334 = eq(_T_8333, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8335 = and(ic_valid_ff, _T_8334) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8336 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8337 = and(_T_8335, _T_8336) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8338 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8339 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8340 = and(_T_8338, _T_8339) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8341 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8342 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8343 = and(_T_8341, _T_8342) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8344 = or(_T_8340, _T_8343) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8345 = or(_T_8344, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8346 = bits(tag_valid_clken_2, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8347 = and(_T_8345, _T_8346) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8348 = bits(_T_8347, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8349 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8348 : @[Reg.scala 28:19]
|
|
_T_8349 <= _T_8337 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][95] <= _T_8349 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8350 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8351 = eq(_T_8350, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8352 = and(ic_valid_ff, _T_8351) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8353 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8354 = and(_T_8352, _T_8353) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8355 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8356 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8357 = and(_T_8355, _T_8356) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8358 = eq(perr_ic_index_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8359 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8360 = and(_T_8358, _T_8359) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8361 = or(_T_8357, _T_8360) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8362 = or(_T_8361, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8363 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8364 = and(_T_8362, _T_8363) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8365 = bits(_T_8364, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8366 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8365 : @[Reg.scala 28:19]
|
|
_T_8366 <= _T_8354 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][64] <= _T_8366 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8367 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8368 = eq(_T_8367, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8369 = and(ic_valid_ff, _T_8368) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8370 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8371 = and(_T_8369, _T_8370) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8372 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8373 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8374 = and(_T_8372, _T_8373) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8375 = eq(perr_ic_index_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8376 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8377 = and(_T_8375, _T_8376) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8378 = or(_T_8374, _T_8377) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8379 = or(_T_8378, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8380 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8381 = and(_T_8379, _T_8380) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8382 = bits(_T_8381, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8383 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8382 : @[Reg.scala 28:19]
|
|
_T_8383 <= _T_8371 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][65] <= _T_8383 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8384 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8385 = eq(_T_8384, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8386 = and(ic_valid_ff, _T_8385) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8387 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8388 = and(_T_8386, _T_8387) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8389 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8390 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8391 = and(_T_8389, _T_8390) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8392 = eq(perr_ic_index_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8393 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8394 = and(_T_8392, _T_8393) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8395 = or(_T_8391, _T_8394) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8396 = or(_T_8395, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8397 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8398 = and(_T_8396, _T_8397) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8399 = bits(_T_8398, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8400 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8399 : @[Reg.scala 28:19]
|
|
_T_8400 <= _T_8388 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][66] <= _T_8400 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8401 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8402 = eq(_T_8401, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8403 = and(ic_valid_ff, _T_8402) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8404 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8405 = and(_T_8403, _T_8404) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8406 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8407 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8408 = and(_T_8406, _T_8407) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8409 = eq(perr_ic_index_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8410 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8411 = and(_T_8409, _T_8410) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8412 = or(_T_8408, _T_8411) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8413 = or(_T_8412, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8414 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8415 = and(_T_8413, _T_8414) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8416 = bits(_T_8415, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8417 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8416 : @[Reg.scala 28:19]
|
|
_T_8417 <= _T_8405 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][67] <= _T_8417 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8418 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8419 = eq(_T_8418, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8420 = and(ic_valid_ff, _T_8419) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8421 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8422 = and(_T_8420, _T_8421) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8423 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8424 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8425 = and(_T_8423, _T_8424) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8426 = eq(perr_ic_index_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8427 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8428 = and(_T_8426, _T_8427) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8429 = or(_T_8425, _T_8428) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8430 = or(_T_8429, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8431 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8432 = and(_T_8430, _T_8431) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8433 = bits(_T_8432, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8434 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8433 : @[Reg.scala 28:19]
|
|
_T_8434 <= _T_8422 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][68] <= _T_8434 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8435 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8436 = eq(_T_8435, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8437 = and(ic_valid_ff, _T_8436) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8438 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8439 = and(_T_8437, _T_8438) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8440 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8441 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8442 = and(_T_8440, _T_8441) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8443 = eq(perr_ic_index_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8444 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8445 = and(_T_8443, _T_8444) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8446 = or(_T_8442, _T_8445) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8447 = or(_T_8446, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8448 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8449 = and(_T_8447, _T_8448) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8450 = bits(_T_8449, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8451 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8450 : @[Reg.scala 28:19]
|
|
_T_8451 <= _T_8439 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][69] <= _T_8451 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8452 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8453 = eq(_T_8452, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8454 = and(ic_valid_ff, _T_8453) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8455 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8456 = and(_T_8454, _T_8455) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8457 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8458 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8459 = and(_T_8457, _T_8458) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8460 = eq(perr_ic_index_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8461 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8462 = and(_T_8460, _T_8461) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8463 = or(_T_8459, _T_8462) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8464 = or(_T_8463, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8465 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8466 = and(_T_8464, _T_8465) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8467 = bits(_T_8466, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8468 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8467 : @[Reg.scala 28:19]
|
|
_T_8468 <= _T_8456 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][70] <= _T_8468 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8469 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8470 = eq(_T_8469, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8471 = and(ic_valid_ff, _T_8470) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8472 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8473 = and(_T_8471, _T_8472) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8474 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8475 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8476 = and(_T_8474, _T_8475) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8477 = eq(perr_ic_index_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8478 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8479 = and(_T_8477, _T_8478) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8480 = or(_T_8476, _T_8479) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8481 = or(_T_8480, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8482 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8483 = and(_T_8481, _T_8482) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8484 = bits(_T_8483, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8485 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8484 : @[Reg.scala 28:19]
|
|
_T_8485 <= _T_8473 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][71] <= _T_8485 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8486 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8487 = eq(_T_8486, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8488 = and(ic_valid_ff, _T_8487) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8489 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8490 = and(_T_8488, _T_8489) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8491 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8492 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8493 = and(_T_8491, _T_8492) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8494 = eq(perr_ic_index_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8495 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8496 = and(_T_8494, _T_8495) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8497 = or(_T_8493, _T_8496) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8498 = or(_T_8497, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8499 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8500 = and(_T_8498, _T_8499) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8501 = bits(_T_8500, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8502 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8501 : @[Reg.scala 28:19]
|
|
_T_8502 <= _T_8490 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][72] <= _T_8502 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8503 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8504 = eq(_T_8503, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8505 = and(ic_valid_ff, _T_8504) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8506 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8507 = and(_T_8505, _T_8506) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8508 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8509 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8510 = and(_T_8508, _T_8509) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8511 = eq(perr_ic_index_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8512 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8513 = and(_T_8511, _T_8512) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8514 = or(_T_8510, _T_8513) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8515 = or(_T_8514, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8516 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8517 = and(_T_8515, _T_8516) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8518 = bits(_T_8517, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8519 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8518 : @[Reg.scala 28:19]
|
|
_T_8519 <= _T_8507 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][73] <= _T_8519 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8520 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8521 = eq(_T_8520, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8522 = and(ic_valid_ff, _T_8521) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8523 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8524 = and(_T_8522, _T_8523) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8526 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8527 = and(_T_8525, _T_8526) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8528 = eq(perr_ic_index_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8529 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8530 = and(_T_8528, _T_8529) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8531 = or(_T_8527, _T_8530) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8532 = or(_T_8531, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8533 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8534 = and(_T_8532, _T_8533) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8535 = bits(_T_8534, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8536 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8535 : @[Reg.scala 28:19]
|
|
_T_8536 <= _T_8524 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][74] <= _T_8536 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8537 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8538 = eq(_T_8537, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8539 = and(ic_valid_ff, _T_8538) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8540 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8541 = and(_T_8539, _T_8540) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8542 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8543 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8544 = and(_T_8542, _T_8543) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8545 = eq(perr_ic_index_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8546 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8547 = and(_T_8545, _T_8546) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8548 = or(_T_8544, _T_8547) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8549 = or(_T_8548, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8550 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8551 = and(_T_8549, _T_8550) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8552 = bits(_T_8551, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8553 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8552 : @[Reg.scala 28:19]
|
|
_T_8553 <= _T_8541 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][75] <= _T_8553 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8554 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8555 = eq(_T_8554, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8556 = and(ic_valid_ff, _T_8555) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8557 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8558 = and(_T_8556, _T_8557) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8559 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8560 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8561 = and(_T_8559, _T_8560) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8562 = eq(perr_ic_index_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8563 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8564 = and(_T_8562, _T_8563) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8565 = or(_T_8561, _T_8564) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8566 = or(_T_8565, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8567 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8568 = and(_T_8566, _T_8567) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8569 = bits(_T_8568, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8570 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8569 : @[Reg.scala 28:19]
|
|
_T_8570 <= _T_8558 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][76] <= _T_8570 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8571 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8572 = eq(_T_8571, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8573 = and(ic_valid_ff, _T_8572) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8574 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8575 = and(_T_8573, _T_8574) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8576 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8577 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8578 = and(_T_8576, _T_8577) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8579 = eq(perr_ic_index_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8580 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8581 = and(_T_8579, _T_8580) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8582 = or(_T_8578, _T_8581) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8583 = or(_T_8582, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8584 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8585 = and(_T_8583, _T_8584) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8586 = bits(_T_8585, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8587 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8586 : @[Reg.scala 28:19]
|
|
_T_8587 <= _T_8575 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][77] <= _T_8587 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8588 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8589 = eq(_T_8588, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8590 = and(ic_valid_ff, _T_8589) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8591 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8592 = and(_T_8590, _T_8591) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8593 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8594 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8595 = and(_T_8593, _T_8594) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8596 = eq(perr_ic_index_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8597 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8598 = and(_T_8596, _T_8597) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8599 = or(_T_8595, _T_8598) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8600 = or(_T_8599, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8601 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8602 = and(_T_8600, _T_8601) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8603 = bits(_T_8602, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8604 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8603 : @[Reg.scala 28:19]
|
|
_T_8604 <= _T_8592 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][78] <= _T_8604 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8605 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8606 = eq(_T_8605, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8607 = and(ic_valid_ff, _T_8606) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8608 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8609 = and(_T_8607, _T_8608) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8610 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8611 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8612 = and(_T_8610, _T_8611) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8613 = eq(perr_ic_index_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8614 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8615 = and(_T_8613, _T_8614) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8616 = or(_T_8612, _T_8615) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8617 = or(_T_8616, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8618 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8619 = and(_T_8617, _T_8618) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8620 = bits(_T_8619, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8621 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8620 : @[Reg.scala 28:19]
|
|
_T_8621 <= _T_8609 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][79] <= _T_8621 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8622 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8623 = eq(_T_8622, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8624 = and(ic_valid_ff, _T_8623) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8625 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8626 = and(_T_8624, _T_8625) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8627 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8628 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8629 = and(_T_8627, _T_8628) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8630 = eq(perr_ic_index_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8631 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8632 = and(_T_8630, _T_8631) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8633 = or(_T_8629, _T_8632) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8634 = or(_T_8633, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8635 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8636 = and(_T_8634, _T_8635) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8637 = bits(_T_8636, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8638 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8637 : @[Reg.scala 28:19]
|
|
_T_8638 <= _T_8626 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][80] <= _T_8638 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8639 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8640 = eq(_T_8639, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8641 = and(ic_valid_ff, _T_8640) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8642 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8643 = and(_T_8641, _T_8642) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8644 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8645 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8646 = and(_T_8644, _T_8645) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8647 = eq(perr_ic_index_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8648 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8649 = and(_T_8647, _T_8648) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8650 = or(_T_8646, _T_8649) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8651 = or(_T_8650, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8652 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8653 = and(_T_8651, _T_8652) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8654 = bits(_T_8653, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8655 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8654 : @[Reg.scala 28:19]
|
|
_T_8655 <= _T_8643 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][81] <= _T_8655 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8656 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8657 = eq(_T_8656, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8658 = and(ic_valid_ff, _T_8657) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8659 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8660 = and(_T_8658, _T_8659) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8661 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8662 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8663 = and(_T_8661, _T_8662) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8664 = eq(perr_ic_index_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8665 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8666 = and(_T_8664, _T_8665) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8667 = or(_T_8663, _T_8666) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8668 = or(_T_8667, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8669 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8670 = and(_T_8668, _T_8669) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8671 = bits(_T_8670, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8672 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8671 : @[Reg.scala 28:19]
|
|
_T_8672 <= _T_8660 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][82] <= _T_8672 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8673 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8674 = eq(_T_8673, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8675 = and(ic_valid_ff, _T_8674) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8676 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8677 = and(_T_8675, _T_8676) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8678 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8679 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8680 = and(_T_8678, _T_8679) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8681 = eq(perr_ic_index_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8682 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8683 = and(_T_8681, _T_8682) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8684 = or(_T_8680, _T_8683) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8685 = or(_T_8684, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8686 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8687 = and(_T_8685, _T_8686) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8688 = bits(_T_8687, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8689 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8688 : @[Reg.scala 28:19]
|
|
_T_8689 <= _T_8677 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][83] <= _T_8689 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8690 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8691 = eq(_T_8690, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8692 = and(ic_valid_ff, _T_8691) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8693 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8694 = and(_T_8692, _T_8693) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8695 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8696 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8697 = and(_T_8695, _T_8696) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8698 = eq(perr_ic_index_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8699 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8700 = and(_T_8698, _T_8699) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8701 = or(_T_8697, _T_8700) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8702 = or(_T_8701, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8703 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8704 = and(_T_8702, _T_8703) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8705 = bits(_T_8704, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8706 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8705 : @[Reg.scala 28:19]
|
|
_T_8706 <= _T_8694 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][84] <= _T_8706 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8707 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8708 = eq(_T_8707, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8709 = and(ic_valid_ff, _T_8708) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8710 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8711 = and(_T_8709, _T_8710) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8712 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8713 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8714 = and(_T_8712, _T_8713) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8715 = eq(perr_ic_index_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8716 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8717 = and(_T_8715, _T_8716) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8718 = or(_T_8714, _T_8717) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8719 = or(_T_8718, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8720 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8721 = and(_T_8719, _T_8720) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8722 = bits(_T_8721, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8723 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8722 : @[Reg.scala 28:19]
|
|
_T_8723 <= _T_8711 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][85] <= _T_8723 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8724 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8725 = eq(_T_8724, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8726 = and(ic_valid_ff, _T_8725) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8727 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8728 = and(_T_8726, _T_8727) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8729 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8730 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8731 = and(_T_8729, _T_8730) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8732 = eq(perr_ic_index_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8733 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8734 = and(_T_8732, _T_8733) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8735 = or(_T_8731, _T_8734) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8736 = or(_T_8735, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8737 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8738 = and(_T_8736, _T_8737) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8739 = bits(_T_8738, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8740 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8739 : @[Reg.scala 28:19]
|
|
_T_8740 <= _T_8728 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][86] <= _T_8740 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8741 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8742 = eq(_T_8741, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8743 = and(ic_valid_ff, _T_8742) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8744 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8745 = and(_T_8743, _T_8744) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8746 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8747 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8748 = and(_T_8746, _T_8747) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8749 = eq(perr_ic_index_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8750 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8751 = and(_T_8749, _T_8750) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8752 = or(_T_8748, _T_8751) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8753 = or(_T_8752, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8754 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8755 = and(_T_8753, _T_8754) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8756 = bits(_T_8755, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8757 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8756 : @[Reg.scala 28:19]
|
|
_T_8757 <= _T_8745 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][87] <= _T_8757 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8758 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8759 = eq(_T_8758, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8760 = and(ic_valid_ff, _T_8759) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8761 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8762 = and(_T_8760, _T_8761) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8763 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8764 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8765 = and(_T_8763, _T_8764) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8766 = eq(perr_ic_index_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8767 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8768 = and(_T_8766, _T_8767) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8769 = or(_T_8765, _T_8768) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8770 = or(_T_8769, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8771 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8772 = and(_T_8770, _T_8771) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8773 = bits(_T_8772, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8774 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8773 : @[Reg.scala 28:19]
|
|
_T_8774 <= _T_8762 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][88] <= _T_8774 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8775 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8776 = eq(_T_8775, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8777 = and(ic_valid_ff, _T_8776) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8778 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8779 = and(_T_8777, _T_8778) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8780 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8781 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8782 = and(_T_8780, _T_8781) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8783 = eq(perr_ic_index_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8784 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8785 = and(_T_8783, _T_8784) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8786 = or(_T_8782, _T_8785) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8787 = or(_T_8786, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8788 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8789 = and(_T_8787, _T_8788) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8790 = bits(_T_8789, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8791 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8790 : @[Reg.scala 28:19]
|
|
_T_8791 <= _T_8779 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][89] <= _T_8791 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8792 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8793 = eq(_T_8792, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8794 = and(ic_valid_ff, _T_8793) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8795 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8796 = and(_T_8794, _T_8795) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8797 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8798 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8799 = and(_T_8797, _T_8798) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8800 = eq(perr_ic_index_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8801 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8802 = and(_T_8800, _T_8801) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8803 = or(_T_8799, _T_8802) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8804 = or(_T_8803, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8805 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8806 = and(_T_8804, _T_8805) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8807 = bits(_T_8806, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8808 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8807 : @[Reg.scala 28:19]
|
|
_T_8808 <= _T_8796 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][90] <= _T_8808 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8809 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8810 = eq(_T_8809, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8811 = and(ic_valid_ff, _T_8810) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8812 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8813 = and(_T_8811, _T_8812) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8814 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8815 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8816 = and(_T_8814, _T_8815) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8817 = eq(perr_ic_index_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8818 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8819 = and(_T_8817, _T_8818) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8820 = or(_T_8816, _T_8819) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8821 = or(_T_8820, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8822 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8823 = and(_T_8821, _T_8822) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8824 = bits(_T_8823, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8825 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8824 : @[Reg.scala 28:19]
|
|
_T_8825 <= _T_8813 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][91] <= _T_8825 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8826 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8827 = eq(_T_8826, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8828 = and(ic_valid_ff, _T_8827) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8829 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8830 = and(_T_8828, _T_8829) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8831 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8832 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8833 = and(_T_8831, _T_8832) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8834 = eq(perr_ic_index_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8835 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8836 = and(_T_8834, _T_8835) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8837 = or(_T_8833, _T_8836) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8838 = or(_T_8837, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8839 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8840 = and(_T_8838, _T_8839) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8841 = bits(_T_8840, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8842 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8841 : @[Reg.scala 28:19]
|
|
_T_8842 <= _T_8830 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][92] <= _T_8842 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8843 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8844 = eq(_T_8843, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8845 = and(ic_valid_ff, _T_8844) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8846 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8847 = and(_T_8845, _T_8846) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8848 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8849 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8850 = and(_T_8848, _T_8849) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8851 = eq(perr_ic_index_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8852 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8853 = and(_T_8851, _T_8852) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8854 = or(_T_8850, _T_8853) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8855 = or(_T_8854, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8856 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8857 = and(_T_8855, _T_8856) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8858 = bits(_T_8857, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8859 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8858 : @[Reg.scala 28:19]
|
|
_T_8859 <= _T_8847 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][93] <= _T_8859 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8860 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8861 = eq(_T_8860, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8862 = and(ic_valid_ff, _T_8861) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8863 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8864 = and(_T_8862, _T_8863) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8865 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8866 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8867 = and(_T_8865, _T_8866) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8868 = eq(perr_ic_index_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8869 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8870 = and(_T_8868, _T_8869) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8871 = or(_T_8867, _T_8870) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8872 = or(_T_8871, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8873 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8874 = and(_T_8872, _T_8873) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8875 = bits(_T_8874, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8876 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8875 : @[Reg.scala 28:19]
|
|
_T_8876 <= _T_8864 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][94] <= _T_8876 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8877 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8878 = eq(_T_8877, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8879 = and(ic_valid_ff, _T_8878) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8880 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8881 = and(_T_8879, _T_8880) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8882 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8883 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8884 = and(_T_8882, _T_8883) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8885 = eq(perr_ic_index_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8886 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8887 = and(_T_8885, _T_8886) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8888 = or(_T_8884, _T_8887) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8889 = or(_T_8888, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8890 = bits(tag_valid_clken_2, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8891 = and(_T_8889, _T_8890) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8892 = bits(_T_8891, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8893 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8892 : @[Reg.scala 28:19]
|
|
_T_8893 <= _T_8881 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][95] <= _T_8893 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8894 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8895 = eq(_T_8894, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8896 = and(ic_valid_ff, _T_8895) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8897 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8898 = and(_T_8896, _T_8897) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8899 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8900 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8901 = and(_T_8899, _T_8900) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8902 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8903 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8904 = and(_T_8902, _T_8903) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8905 = or(_T_8901, _T_8904) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8906 = or(_T_8905, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8907 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8908 = and(_T_8906, _T_8907) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8909 = bits(_T_8908, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8910 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8909 : @[Reg.scala 28:19]
|
|
_T_8910 <= _T_8898 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][96] <= _T_8910 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8911 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8912 = eq(_T_8911, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8913 = and(ic_valid_ff, _T_8912) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8914 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8915 = and(_T_8913, _T_8914) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8916 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8917 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8918 = and(_T_8916, _T_8917) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8919 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8920 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8921 = and(_T_8919, _T_8920) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8922 = or(_T_8918, _T_8921) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8923 = or(_T_8922, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8924 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8925 = and(_T_8923, _T_8924) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8926 = bits(_T_8925, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8927 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8926 : @[Reg.scala 28:19]
|
|
_T_8927 <= _T_8915 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][97] <= _T_8927 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8928 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8929 = eq(_T_8928, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8930 = and(ic_valid_ff, _T_8929) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8931 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8932 = and(_T_8930, _T_8931) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8933 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8934 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8935 = and(_T_8933, _T_8934) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8936 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8937 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8938 = and(_T_8936, _T_8937) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8939 = or(_T_8935, _T_8938) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8940 = or(_T_8939, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8941 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8942 = and(_T_8940, _T_8941) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8943 = bits(_T_8942, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8944 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8943 : @[Reg.scala 28:19]
|
|
_T_8944 <= _T_8932 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][98] <= _T_8944 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8945 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8946 = eq(_T_8945, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8947 = and(ic_valid_ff, _T_8946) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8948 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8949 = and(_T_8947, _T_8948) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8950 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8951 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8952 = and(_T_8950, _T_8951) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8953 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8954 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8955 = and(_T_8953, _T_8954) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8956 = or(_T_8952, _T_8955) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8957 = or(_T_8956, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8958 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8959 = and(_T_8957, _T_8958) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8960 = bits(_T_8959, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8961 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8960 : @[Reg.scala 28:19]
|
|
_T_8961 <= _T_8949 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][99] <= _T_8961 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8962 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8963 = eq(_T_8962, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8964 = and(ic_valid_ff, _T_8963) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8965 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8966 = and(_T_8964, _T_8965) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8967 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8968 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8969 = and(_T_8967, _T_8968) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8970 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8971 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8972 = and(_T_8970, _T_8971) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8973 = or(_T_8969, _T_8972) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8974 = or(_T_8973, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8975 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8976 = and(_T_8974, _T_8975) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8977 = bits(_T_8976, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8978 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8977 : @[Reg.scala 28:19]
|
|
_T_8978 <= _T_8966 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][100] <= _T_8978 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8979 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8980 = eq(_T_8979, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8981 = and(ic_valid_ff, _T_8980) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8982 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_8983 = and(_T_8981, _T_8982) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_8984 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_8985 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_8986 = and(_T_8984, _T_8985) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_8987 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_8988 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_8989 = and(_T_8987, _T_8988) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_8990 = or(_T_8986, _T_8989) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_8991 = or(_T_8990, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_8992 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_8993 = and(_T_8991, _T_8992) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_8994 = bits(_T_8993, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_8995 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_8994 : @[Reg.scala 28:19]
|
|
_T_8995 <= _T_8983 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][101] <= _T_8995 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_8996 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_8997 = eq(_T_8996, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_8998 = and(ic_valid_ff, _T_8997) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_8999 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9000 = and(_T_8998, _T_8999) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9001 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9002 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9003 = and(_T_9001, _T_9002) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9004 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9005 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9006 = and(_T_9004, _T_9005) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9007 = or(_T_9003, _T_9006) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9008 = or(_T_9007, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9009 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9010 = and(_T_9008, _T_9009) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9011 = bits(_T_9010, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9012 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9011 : @[Reg.scala 28:19]
|
|
_T_9012 <= _T_9000 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][102] <= _T_9012 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9013 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9014 = eq(_T_9013, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9015 = and(ic_valid_ff, _T_9014) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9016 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9017 = and(_T_9015, _T_9016) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9018 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9019 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9020 = and(_T_9018, _T_9019) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9021 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9022 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9023 = and(_T_9021, _T_9022) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9024 = or(_T_9020, _T_9023) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9025 = or(_T_9024, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9026 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9027 = and(_T_9025, _T_9026) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9028 = bits(_T_9027, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9029 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9028 : @[Reg.scala 28:19]
|
|
_T_9029 <= _T_9017 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][103] <= _T_9029 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9030 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9031 = eq(_T_9030, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9032 = and(ic_valid_ff, _T_9031) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9033 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9034 = and(_T_9032, _T_9033) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9035 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9036 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9037 = and(_T_9035, _T_9036) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9038 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9039 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9040 = and(_T_9038, _T_9039) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9041 = or(_T_9037, _T_9040) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9042 = or(_T_9041, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9043 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9044 = and(_T_9042, _T_9043) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9045 = bits(_T_9044, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9046 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9045 : @[Reg.scala 28:19]
|
|
_T_9046 <= _T_9034 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][104] <= _T_9046 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9047 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9048 = eq(_T_9047, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9049 = and(ic_valid_ff, _T_9048) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9050 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9051 = and(_T_9049, _T_9050) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9052 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9053 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9054 = and(_T_9052, _T_9053) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9055 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9056 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9057 = and(_T_9055, _T_9056) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9058 = or(_T_9054, _T_9057) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9059 = or(_T_9058, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9060 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9061 = and(_T_9059, _T_9060) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9062 = bits(_T_9061, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9063 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9062 : @[Reg.scala 28:19]
|
|
_T_9063 <= _T_9051 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][105] <= _T_9063 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9064 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9065 = eq(_T_9064, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9066 = and(ic_valid_ff, _T_9065) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9067 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9068 = and(_T_9066, _T_9067) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9069 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9070 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9071 = and(_T_9069, _T_9070) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9072 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9073 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9074 = and(_T_9072, _T_9073) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9075 = or(_T_9071, _T_9074) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9076 = or(_T_9075, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9077 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9078 = and(_T_9076, _T_9077) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9079 = bits(_T_9078, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9080 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9079 : @[Reg.scala 28:19]
|
|
_T_9080 <= _T_9068 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][106] <= _T_9080 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9081 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9082 = eq(_T_9081, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9083 = and(ic_valid_ff, _T_9082) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9084 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9085 = and(_T_9083, _T_9084) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9086 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9087 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9088 = and(_T_9086, _T_9087) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9089 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9090 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9091 = and(_T_9089, _T_9090) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9092 = or(_T_9088, _T_9091) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9093 = or(_T_9092, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9094 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9095 = and(_T_9093, _T_9094) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9096 = bits(_T_9095, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9097 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9096 : @[Reg.scala 28:19]
|
|
_T_9097 <= _T_9085 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][107] <= _T_9097 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9098 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9099 = eq(_T_9098, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9100 = and(ic_valid_ff, _T_9099) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9101 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9102 = and(_T_9100, _T_9101) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9103 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9104 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9105 = and(_T_9103, _T_9104) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9106 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9107 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9108 = and(_T_9106, _T_9107) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9109 = or(_T_9105, _T_9108) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9110 = or(_T_9109, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9111 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9112 = and(_T_9110, _T_9111) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9113 = bits(_T_9112, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9114 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9113 : @[Reg.scala 28:19]
|
|
_T_9114 <= _T_9102 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][108] <= _T_9114 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9115 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9116 = eq(_T_9115, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9117 = and(ic_valid_ff, _T_9116) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9118 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9119 = and(_T_9117, _T_9118) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9121 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9122 = and(_T_9120, _T_9121) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9123 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9124 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9125 = and(_T_9123, _T_9124) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9126 = or(_T_9122, _T_9125) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9127 = or(_T_9126, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9128 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9129 = and(_T_9127, _T_9128) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9130 = bits(_T_9129, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9131 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9130 : @[Reg.scala 28:19]
|
|
_T_9131 <= _T_9119 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][109] <= _T_9131 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9132 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9133 = eq(_T_9132, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9134 = and(ic_valid_ff, _T_9133) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9135 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9136 = and(_T_9134, _T_9135) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9137 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9138 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9139 = and(_T_9137, _T_9138) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9140 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9141 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9142 = and(_T_9140, _T_9141) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9143 = or(_T_9139, _T_9142) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9144 = or(_T_9143, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9145 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9146 = and(_T_9144, _T_9145) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9147 = bits(_T_9146, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9148 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9147 : @[Reg.scala 28:19]
|
|
_T_9148 <= _T_9136 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][110] <= _T_9148 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9149 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9150 = eq(_T_9149, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9151 = and(ic_valid_ff, _T_9150) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9152 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9153 = and(_T_9151, _T_9152) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9154 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9155 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9156 = and(_T_9154, _T_9155) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9157 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9158 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9159 = and(_T_9157, _T_9158) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9160 = or(_T_9156, _T_9159) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9161 = or(_T_9160, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9162 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9163 = and(_T_9161, _T_9162) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9164 = bits(_T_9163, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9165 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9164 : @[Reg.scala 28:19]
|
|
_T_9165 <= _T_9153 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][111] <= _T_9165 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9166 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9167 = eq(_T_9166, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9168 = and(ic_valid_ff, _T_9167) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9169 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9170 = and(_T_9168, _T_9169) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9171 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9172 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9173 = and(_T_9171, _T_9172) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9174 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9175 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9176 = and(_T_9174, _T_9175) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9177 = or(_T_9173, _T_9176) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9178 = or(_T_9177, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9179 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9180 = and(_T_9178, _T_9179) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9181 = bits(_T_9180, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9182 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9181 : @[Reg.scala 28:19]
|
|
_T_9182 <= _T_9170 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][112] <= _T_9182 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9183 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9184 = eq(_T_9183, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9185 = and(ic_valid_ff, _T_9184) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9186 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9187 = and(_T_9185, _T_9186) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9188 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9189 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9190 = and(_T_9188, _T_9189) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9191 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9192 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9193 = and(_T_9191, _T_9192) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9194 = or(_T_9190, _T_9193) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9195 = or(_T_9194, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9196 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9197 = and(_T_9195, _T_9196) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9198 = bits(_T_9197, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9199 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9198 : @[Reg.scala 28:19]
|
|
_T_9199 <= _T_9187 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][113] <= _T_9199 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9200 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9201 = eq(_T_9200, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9202 = and(ic_valid_ff, _T_9201) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9203 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9204 = and(_T_9202, _T_9203) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9205 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9206 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9207 = and(_T_9205, _T_9206) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9208 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9209 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9210 = and(_T_9208, _T_9209) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9211 = or(_T_9207, _T_9210) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9212 = or(_T_9211, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9213 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9214 = and(_T_9212, _T_9213) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9215 = bits(_T_9214, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9216 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9215 : @[Reg.scala 28:19]
|
|
_T_9216 <= _T_9204 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][114] <= _T_9216 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9217 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9218 = eq(_T_9217, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9219 = and(ic_valid_ff, _T_9218) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9220 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9221 = and(_T_9219, _T_9220) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9222 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9223 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9224 = and(_T_9222, _T_9223) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9225 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9226 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9227 = and(_T_9225, _T_9226) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9228 = or(_T_9224, _T_9227) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9229 = or(_T_9228, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9230 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9231 = and(_T_9229, _T_9230) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9232 = bits(_T_9231, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9233 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9232 : @[Reg.scala 28:19]
|
|
_T_9233 <= _T_9221 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][115] <= _T_9233 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9234 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9235 = eq(_T_9234, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9236 = and(ic_valid_ff, _T_9235) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9237 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9238 = and(_T_9236, _T_9237) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9239 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9240 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9241 = and(_T_9239, _T_9240) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9242 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9243 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9244 = and(_T_9242, _T_9243) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9245 = or(_T_9241, _T_9244) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9246 = or(_T_9245, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9247 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9248 = and(_T_9246, _T_9247) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9249 = bits(_T_9248, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9250 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9249 : @[Reg.scala 28:19]
|
|
_T_9250 <= _T_9238 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][116] <= _T_9250 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9251 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9252 = eq(_T_9251, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9253 = and(ic_valid_ff, _T_9252) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9254 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9255 = and(_T_9253, _T_9254) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9256 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9257 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9258 = and(_T_9256, _T_9257) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9259 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9260 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9261 = and(_T_9259, _T_9260) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9262 = or(_T_9258, _T_9261) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9263 = or(_T_9262, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9264 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9265 = and(_T_9263, _T_9264) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9266 = bits(_T_9265, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9267 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9266 : @[Reg.scala 28:19]
|
|
_T_9267 <= _T_9255 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][117] <= _T_9267 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9268 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9269 = eq(_T_9268, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9270 = and(ic_valid_ff, _T_9269) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9271 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9272 = and(_T_9270, _T_9271) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9273 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9274 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9275 = and(_T_9273, _T_9274) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9276 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9277 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9278 = and(_T_9276, _T_9277) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9279 = or(_T_9275, _T_9278) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9280 = or(_T_9279, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9281 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9282 = and(_T_9280, _T_9281) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9283 = bits(_T_9282, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9284 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9283 : @[Reg.scala 28:19]
|
|
_T_9284 <= _T_9272 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][118] <= _T_9284 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9285 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9286 = eq(_T_9285, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9287 = and(ic_valid_ff, _T_9286) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9288 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9289 = and(_T_9287, _T_9288) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9290 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9291 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9292 = and(_T_9290, _T_9291) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9293 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9294 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9295 = and(_T_9293, _T_9294) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9296 = or(_T_9292, _T_9295) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9297 = or(_T_9296, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9298 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9299 = and(_T_9297, _T_9298) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9300 = bits(_T_9299, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9301 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9300 : @[Reg.scala 28:19]
|
|
_T_9301 <= _T_9289 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][119] <= _T_9301 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9302 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9303 = eq(_T_9302, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9304 = and(ic_valid_ff, _T_9303) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9305 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9306 = and(_T_9304, _T_9305) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9307 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9308 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9309 = and(_T_9307, _T_9308) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9310 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9311 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9312 = and(_T_9310, _T_9311) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9313 = or(_T_9309, _T_9312) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9314 = or(_T_9313, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9315 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9316 = and(_T_9314, _T_9315) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9317 = bits(_T_9316, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9318 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9317 : @[Reg.scala 28:19]
|
|
_T_9318 <= _T_9306 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][120] <= _T_9318 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9319 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9320 = eq(_T_9319, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9321 = and(ic_valid_ff, _T_9320) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9322 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9323 = and(_T_9321, _T_9322) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9324 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9325 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9326 = and(_T_9324, _T_9325) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9327 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9328 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9329 = and(_T_9327, _T_9328) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9330 = or(_T_9326, _T_9329) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9331 = or(_T_9330, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9332 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9333 = and(_T_9331, _T_9332) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9334 = bits(_T_9333, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9335 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9334 : @[Reg.scala 28:19]
|
|
_T_9335 <= _T_9323 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][121] <= _T_9335 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9336 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9337 = eq(_T_9336, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9338 = and(ic_valid_ff, _T_9337) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9339 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9340 = and(_T_9338, _T_9339) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9341 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9342 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9343 = and(_T_9341, _T_9342) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9344 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9345 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9346 = and(_T_9344, _T_9345) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9347 = or(_T_9343, _T_9346) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9348 = or(_T_9347, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9349 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9350 = and(_T_9348, _T_9349) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9351 = bits(_T_9350, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9352 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9351 : @[Reg.scala 28:19]
|
|
_T_9352 <= _T_9340 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][122] <= _T_9352 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9353 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9354 = eq(_T_9353, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9355 = and(ic_valid_ff, _T_9354) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9356 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9357 = and(_T_9355, _T_9356) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9358 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9359 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9360 = and(_T_9358, _T_9359) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9361 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9362 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9363 = and(_T_9361, _T_9362) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9364 = or(_T_9360, _T_9363) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9365 = or(_T_9364, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9366 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9367 = and(_T_9365, _T_9366) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9368 = bits(_T_9367, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9369 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9368 : @[Reg.scala 28:19]
|
|
_T_9369 <= _T_9357 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][123] <= _T_9369 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9370 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9371 = eq(_T_9370, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9372 = and(ic_valid_ff, _T_9371) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9373 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9374 = and(_T_9372, _T_9373) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9375 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9376 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9377 = and(_T_9375, _T_9376) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9378 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9379 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9380 = and(_T_9378, _T_9379) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9381 = or(_T_9377, _T_9380) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9382 = or(_T_9381, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9383 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9384 = and(_T_9382, _T_9383) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9385 = bits(_T_9384, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9386 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9385 : @[Reg.scala 28:19]
|
|
_T_9386 <= _T_9374 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][124] <= _T_9386 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9387 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9388 = eq(_T_9387, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9389 = and(ic_valid_ff, _T_9388) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9390 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9391 = and(_T_9389, _T_9390) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9392 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9393 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9394 = and(_T_9392, _T_9393) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9395 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9396 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9397 = and(_T_9395, _T_9396) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9398 = or(_T_9394, _T_9397) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9399 = or(_T_9398, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9400 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9401 = and(_T_9399, _T_9400) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9402 = bits(_T_9401, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9403 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9402 : @[Reg.scala 28:19]
|
|
_T_9403 <= _T_9391 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][125] <= _T_9403 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9404 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9405 = eq(_T_9404, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9406 = and(ic_valid_ff, _T_9405) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9407 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9408 = and(_T_9406, _T_9407) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9409 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9410 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9411 = and(_T_9409, _T_9410) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9412 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9413 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9414 = and(_T_9412, _T_9413) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9415 = or(_T_9411, _T_9414) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9416 = or(_T_9415, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9417 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9418 = and(_T_9416, _T_9417) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9419 = bits(_T_9418, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9420 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9419 : @[Reg.scala 28:19]
|
|
_T_9420 <= _T_9408 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][126] <= _T_9420 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9421 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9422 = eq(_T_9421, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9423 = and(ic_valid_ff, _T_9422) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9424 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9425 = and(_T_9423, _T_9424) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9426 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9427 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9428 = and(_T_9426, _T_9427) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9429 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9430 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9431 = and(_T_9429, _T_9430) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9432 = or(_T_9428, _T_9431) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9433 = or(_T_9432, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9434 = bits(tag_valid_clken_3, 0, 0) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9435 = and(_T_9433, _T_9434) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9436 = bits(_T_9435, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9437 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9436 : @[Reg.scala 28:19]
|
|
_T_9437 <= _T_9425 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[0][127] <= _T_9437 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9438 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9439 = eq(_T_9438, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9440 = and(ic_valid_ff, _T_9439) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9441 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9442 = and(_T_9440, _T_9441) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9443 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9444 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9445 = and(_T_9443, _T_9444) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9446 = eq(perr_ic_index_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9447 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9448 = and(_T_9446, _T_9447) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9449 = or(_T_9445, _T_9448) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9450 = or(_T_9449, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9451 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9452 = and(_T_9450, _T_9451) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9453 = bits(_T_9452, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9454 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9453 : @[Reg.scala 28:19]
|
|
_T_9454 <= _T_9442 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][96] <= _T_9454 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9455 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9456 = eq(_T_9455, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9457 = and(ic_valid_ff, _T_9456) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9458 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9459 = and(_T_9457, _T_9458) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9460 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9461 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9462 = and(_T_9460, _T_9461) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9463 = eq(perr_ic_index_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9464 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9465 = and(_T_9463, _T_9464) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9466 = or(_T_9462, _T_9465) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9467 = or(_T_9466, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9468 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9469 = and(_T_9467, _T_9468) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9470 = bits(_T_9469, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9471 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9470 : @[Reg.scala 28:19]
|
|
_T_9471 <= _T_9459 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][97] <= _T_9471 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9472 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9473 = eq(_T_9472, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9474 = and(ic_valid_ff, _T_9473) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9475 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9476 = and(_T_9474, _T_9475) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9477 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9478 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9479 = and(_T_9477, _T_9478) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9480 = eq(perr_ic_index_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9481 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9482 = and(_T_9480, _T_9481) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9483 = or(_T_9479, _T_9482) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9484 = or(_T_9483, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9485 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9486 = and(_T_9484, _T_9485) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9487 = bits(_T_9486, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9488 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9487 : @[Reg.scala 28:19]
|
|
_T_9488 <= _T_9476 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][98] <= _T_9488 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9489 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9490 = eq(_T_9489, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9491 = and(ic_valid_ff, _T_9490) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9492 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9493 = and(_T_9491, _T_9492) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9494 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9495 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9496 = and(_T_9494, _T_9495) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9497 = eq(perr_ic_index_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9498 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9499 = and(_T_9497, _T_9498) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9500 = or(_T_9496, _T_9499) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9501 = or(_T_9500, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9502 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9503 = and(_T_9501, _T_9502) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9504 = bits(_T_9503, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9505 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9504 : @[Reg.scala 28:19]
|
|
_T_9505 <= _T_9493 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][99] <= _T_9505 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9506 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9507 = eq(_T_9506, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9508 = and(ic_valid_ff, _T_9507) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9509 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9510 = and(_T_9508, _T_9509) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9512 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9513 = and(_T_9511, _T_9512) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9514 = eq(perr_ic_index_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9515 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9516 = and(_T_9514, _T_9515) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9517 = or(_T_9513, _T_9516) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9518 = or(_T_9517, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9519 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9520 = and(_T_9518, _T_9519) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9521 = bits(_T_9520, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9522 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9521 : @[Reg.scala 28:19]
|
|
_T_9522 <= _T_9510 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][100] <= _T_9522 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9523 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9524 = eq(_T_9523, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9525 = and(ic_valid_ff, _T_9524) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9526 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9527 = and(_T_9525, _T_9526) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9528 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9529 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9530 = and(_T_9528, _T_9529) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9531 = eq(perr_ic_index_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9532 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9533 = and(_T_9531, _T_9532) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9534 = or(_T_9530, _T_9533) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9535 = or(_T_9534, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9536 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9537 = and(_T_9535, _T_9536) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9538 = bits(_T_9537, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9539 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9538 : @[Reg.scala 28:19]
|
|
_T_9539 <= _T_9527 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][101] <= _T_9539 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9540 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9541 = eq(_T_9540, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9542 = and(ic_valid_ff, _T_9541) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9543 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9544 = and(_T_9542, _T_9543) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9546 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9547 = and(_T_9545, _T_9546) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9548 = eq(perr_ic_index_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9549 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9550 = and(_T_9548, _T_9549) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9551 = or(_T_9547, _T_9550) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9552 = or(_T_9551, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9553 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9554 = and(_T_9552, _T_9553) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9555 = bits(_T_9554, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9556 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9555 : @[Reg.scala 28:19]
|
|
_T_9556 <= _T_9544 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][102] <= _T_9556 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9557 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9558 = eq(_T_9557, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9559 = and(ic_valid_ff, _T_9558) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9560 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9561 = and(_T_9559, _T_9560) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9562 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9563 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9564 = and(_T_9562, _T_9563) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9565 = eq(perr_ic_index_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9566 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9567 = and(_T_9565, _T_9566) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9568 = or(_T_9564, _T_9567) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9569 = or(_T_9568, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9570 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9571 = and(_T_9569, _T_9570) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9572 = bits(_T_9571, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9573 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9572 : @[Reg.scala 28:19]
|
|
_T_9573 <= _T_9561 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][103] <= _T_9573 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9574 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9575 = eq(_T_9574, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9576 = and(ic_valid_ff, _T_9575) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9577 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9578 = and(_T_9576, _T_9577) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9579 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9580 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9581 = and(_T_9579, _T_9580) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9582 = eq(perr_ic_index_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9583 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9584 = and(_T_9582, _T_9583) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9585 = or(_T_9581, _T_9584) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9586 = or(_T_9585, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9587 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9588 = and(_T_9586, _T_9587) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9589 = bits(_T_9588, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9590 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9589 : @[Reg.scala 28:19]
|
|
_T_9590 <= _T_9578 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][104] <= _T_9590 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9591 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9592 = eq(_T_9591, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9593 = and(ic_valid_ff, _T_9592) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9594 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9595 = and(_T_9593, _T_9594) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9596 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9597 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9598 = and(_T_9596, _T_9597) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9599 = eq(perr_ic_index_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9600 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9601 = and(_T_9599, _T_9600) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9602 = or(_T_9598, _T_9601) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9603 = or(_T_9602, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9604 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9605 = and(_T_9603, _T_9604) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9606 = bits(_T_9605, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9607 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9606 : @[Reg.scala 28:19]
|
|
_T_9607 <= _T_9595 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][105] <= _T_9607 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9608 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9609 = eq(_T_9608, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9610 = and(ic_valid_ff, _T_9609) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9611 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9612 = and(_T_9610, _T_9611) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9613 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9614 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9615 = and(_T_9613, _T_9614) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9616 = eq(perr_ic_index_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9617 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9618 = and(_T_9616, _T_9617) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9619 = or(_T_9615, _T_9618) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9620 = or(_T_9619, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9621 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9622 = and(_T_9620, _T_9621) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9623 = bits(_T_9622, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9624 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9623 : @[Reg.scala 28:19]
|
|
_T_9624 <= _T_9612 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][106] <= _T_9624 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9625 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9626 = eq(_T_9625, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9627 = and(ic_valid_ff, _T_9626) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9628 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9629 = and(_T_9627, _T_9628) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9630 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9631 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9632 = and(_T_9630, _T_9631) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9633 = eq(perr_ic_index_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9634 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9635 = and(_T_9633, _T_9634) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9636 = or(_T_9632, _T_9635) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9637 = or(_T_9636, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9638 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9639 = and(_T_9637, _T_9638) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9640 = bits(_T_9639, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9641 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9640 : @[Reg.scala 28:19]
|
|
_T_9641 <= _T_9629 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][107] <= _T_9641 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9642 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9643 = eq(_T_9642, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9644 = and(ic_valid_ff, _T_9643) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9645 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9646 = and(_T_9644, _T_9645) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9647 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9648 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9649 = and(_T_9647, _T_9648) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9650 = eq(perr_ic_index_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9651 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9652 = and(_T_9650, _T_9651) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9653 = or(_T_9649, _T_9652) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9654 = or(_T_9653, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9655 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9656 = and(_T_9654, _T_9655) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9657 = bits(_T_9656, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9658 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9657 : @[Reg.scala 28:19]
|
|
_T_9658 <= _T_9646 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][108] <= _T_9658 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9659 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9660 = eq(_T_9659, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9661 = and(ic_valid_ff, _T_9660) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9662 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9663 = and(_T_9661, _T_9662) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9664 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9665 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9666 = and(_T_9664, _T_9665) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9667 = eq(perr_ic_index_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9668 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9669 = and(_T_9667, _T_9668) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9670 = or(_T_9666, _T_9669) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9671 = or(_T_9670, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9672 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9673 = and(_T_9671, _T_9672) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9674 = bits(_T_9673, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9675 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9674 : @[Reg.scala 28:19]
|
|
_T_9675 <= _T_9663 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][109] <= _T_9675 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9676 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9677 = eq(_T_9676, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9678 = and(ic_valid_ff, _T_9677) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9679 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9680 = and(_T_9678, _T_9679) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9681 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9682 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9683 = and(_T_9681, _T_9682) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9684 = eq(perr_ic_index_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9685 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9686 = and(_T_9684, _T_9685) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9687 = or(_T_9683, _T_9686) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9688 = or(_T_9687, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9689 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9690 = and(_T_9688, _T_9689) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9691 = bits(_T_9690, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9692 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9691 : @[Reg.scala 28:19]
|
|
_T_9692 <= _T_9680 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][110] <= _T_9692 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9693 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9694 = eq(_T_9693, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9695 = and(ic_valid_ff, _T_9694) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9696 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9697 = and(_T_9695, _T_9696) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9698 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9699 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9700 = and(_T_9698, _T_9699) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9701 = eq(perr_ic_index_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9702 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9703 = and(_T_9701, _T_9702) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9704 = or(_T_9700, _T_9703) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9705 = or(_T_9704, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9706 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9707 = and(_T_9705, _T_9706) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9708 = bits(_T_9707, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9709 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9708 : @[Reg.scala 28:19]
|
|
_T_9709 <= _T_9697 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][111] <= _T_9709 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9710 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9711 = eq(_T_9710, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9712 = and(ic_valid_ff, _T_9711) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9713 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9714 = and(_T_9712, _T_9713) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9715 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9716 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9717 = and(_T_9715, _T_9716) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9718 = eq(perr_ic_index_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9719 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9720 = and(_T_9718, _T_9719) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9721 = or(_T_9717, _T_9720) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9722 = or(_T_9721, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9723 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9724 = and(_T_9722, _T_9723) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9725 = bits(_T_9724, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9726 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9725 : @[Reg.scala 28:19]
|
|
_T_9726 <= _T_9714 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][112] <= _T_9726 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9727 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9728 = eq(_T_9727, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9729 = and(ic_valid_ff, _T_9728) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9730 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9731 = and(_T_9729, _T_9730) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9732 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9733 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9734 = and(_T_9732, _T_9733) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9735 = eq(perr_ic_index_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9736 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9737 = and(_T_9735, _T_9736) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9738 = or(_T_9734, _T_9737) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9739 = or(_T_9738, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9740 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9741 = and(_T_9739, _T_9740) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9742 = bits(_T_9741, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9743 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9742 : @[Reg.scala 28:19]
|
|
_T_9743 <= _T_9731 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][113] <= _T_9743 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9744 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9745 = eq(_T_9744, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9746 = and(ic_valid_ff, _T_9745) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9747 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9748 = and(_T_9746, _T_9747) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9749 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9750 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9751 = and(_T_9749, _T_9750) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9752 = eq(perr_ic_index_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9753 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9754 = and(_T_9752, _T_9753) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9755 = or(_T_9751, _T_9754) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9756 = or(_T_9755, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9757 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9758 = and(_T_9756, _T_9757) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9759 = bits(_T_9758, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9760 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9759 : @[Reg.scala 28:19]
|
|
_T_9760 <= _T_9748 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][114] <= _T_9760 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9761 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9762 = eq(_T_9761, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9763 = and(ic_valid_ff, _T_9762) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9764 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9765 = and(_T_9763, _T_9764) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9766 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9767 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9768 = and(_T_9766, _T_9767) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9769 = eq(perr_ic_index_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9770 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9771 = and(_T_9769, _T_9770) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9772 = or(_T_9768, _T_9771) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9773 = or(_T_9772, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9774 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9775 = and(_T_9773, _T_9774) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9776 = bits(_T_9775, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9777 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9776 : @[Reg.scala 28:19]
|
|
_T_9777 <= _T_9765 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][115] <= _T_9777 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9778 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9779 = eq(_T_9778, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9780 = and(ic_valid_ff, _T_9779) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9781 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9782 = and(_T_9780, _T_9781) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9783 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9784 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9785 = and(_T_9783, _T_9784) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9786 = eq(perr_ic_index_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9787 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9788 = and(_T_9786, _T_9787) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9789 = or(_T_9785, _T_9788) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9790 = or(_T_9789, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9791 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9792 = and(_T_9790, _T_9791) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9793 = bits(_T_9792, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9794 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9793 : @[Reg.scala 28:19]
|
|
_T_9794 <= _T_9782 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][116] <= _T_9794 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9795 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9796 = eq(_T_9795, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9797 = and(ic_valid_ff, _T_9796) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9798 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9799 = and(_T_9797, _T_9798) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9800 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9801 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9802 = and(_T_9800, _T_9801) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9803 = eq(perr_ic_index_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9804 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9805 = and(_T_9803, _T_9804) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9806 = or(_T_9802, _T_9805) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9807 = or(_T_9806, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9808 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9809 = and(_T_9807, _T_9808) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9810 = bits(_T_9809, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9811 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9810 : @[Reg.scala 28:19]
|
|
_T_9811 <= _T_9799 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][117] <= _T_9811 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9812 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9813 = eq(_T_9812, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9814 = and(ic_valid_ff, _T_9813) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9815 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9816 = and(_T_9814, _T_9815) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9817 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9818 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9819 = and(_T_9817, _T_9818) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9820 = eq(perr_ic_index_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9821 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9822 = and(_T_9820, _T_9821) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9823 = or(_T_9819, _T_9822) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9824 = or(_T_9823, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9825 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9826 = and(_T_9824, _T_9825) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9827 = bits(_T_9826, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9828 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9827 : @[Reg.scala 28:19]
|
|
_T_9828 <= _T_9816 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][118] <= _T_9828 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9829 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9830 = eq(_T_9829, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9831 = and(ic_valid_ff, _T_9830) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9832 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9833 = and(_T_9831, _T_9832) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9834 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9835 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9836 = and(_T_9834, _T_9835) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9837 = eq(perr_ic_index_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9838 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9839 = and(_T_9837, _T_9838) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9840 = or(_T_9836, _T_9839) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9841 = or(_T_9840, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9842 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9843 = and(_T_9841, _T_9842) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9844 = bits(_T_9843, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9845 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9844 : @[Reg.scala 28:19]
|
|
_T_9845 <= _T_9833 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][119] <= _T_9845 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9846 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9847 = eq(_T_9846, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9848 = and(ic_valid_ff, _T_9847) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9849 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9850 = and(_T_9848, _T_9849) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9851 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9852 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9853 = and(_T_9851, _T_9852) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9854 = eq(perr_ic_index_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9855 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9856 = and(_T_9854, _T_9855) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9857 = or(_T_9853, _T_9856) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9858 = or(_T_9857, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9859 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9860 = and(_T_9858, _T_9859) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9861 = bits(_T_9860, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9862 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9861 : @[Reg.scala 28:19]
|
|
_T_9862 <= _T_9850 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][120] <= _T_9862 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9863 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9864 = eq(_T_9863, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9865 = and(ic_valid_ff, _T_9864) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9866 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9867 = and(_T_9865, _T_9866) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9868 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9869 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9870 = and(_T_9868, _T_9869) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9871 = eq(perr_ic_index_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9872 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9873 = and(_T_9871, _T_9872) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9874 = or(_T_9870, _T_9873) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9875 = or(_T_9874, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9876 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9877 = and(_T_9875, _T_9876) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9878 = bits(_T_9877, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9879 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9878 : @[Reg.scala 28:19]
|
|
_T_9879 <= _T_9867 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][121] <= _T_9879 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9880 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9881 = eq(_T_9880, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9882 = and(ic_valid_ff, _T_9881) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9883 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9884 = and(_T_9882, _T_9883) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9885 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9886 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9887 = and(_T_9885, _T_9886) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9888 = eq(perr_ic_index_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9889 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9890 = and(_T_9888, _T_9889) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9891 = or(_T_9887, _T_9890) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9892 = or(_T_9891, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9893 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9894 = and(_T_9892, _T_9893) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9895 = bits(_T_9894, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9896 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9895 : @[Reg.scala 28:19]
|
|
_T_9896 <= _T_9884 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][122] <= _T_9896 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9897 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9898 = eq(_T_9897, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9899 = and(ic_valid_ff, _T_9898) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9900 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9901 = and(_T_9899, _T_9900) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9902 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9903 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9904 = and(_T_9902, _T_9903) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9905 = eq(perr_ic_index_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9906 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9907 = and(_T_9905, _T_9906) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9908 = or(_T_9904, _T_9907) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9909 = or(_T_9908, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9910 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9911 = and(_T_9909, _T_9910) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9912 = bits(_T_9911, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9913 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9912 : @[Reg.scala 28:19]
|
|
_T_9913 <= _T_9901 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][123] <= _T_9913 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9914 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9915 = eq(_T_9914, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9916 = and(ic_valid_ff, _T_9915) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9917 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9918 = and(_T_9916, _T_9917) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9919 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9920 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9921 = and(_T_9919, _T_9920) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9922 = eq(perr_ic_index_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9923 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9924 = and(_T_9922, _T_9923) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9925 = or(_T_9921, _T_9924) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9926 = or(_T_9925, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9927 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9928 = and(_T_9926, _T_9927) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9929 = bits(_T_9928, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9930 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9929 : @[Reg.scala 28:19]
|
|
_T_9930 <= _T_9918 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][124] <= _T_9930 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9931 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9932 = eq(_T_9931, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9933 = and(ic_valid_ff, _T_9932) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9934 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9935 = and(_T_9933, _T_9934) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9936 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9937 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9938 = and(_T_9936, _T_9937) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9939 = eq(perr_ic_index_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9940 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9941 = and(_T_9939, _T_9940) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9942 = or(_T_9938, _T_9941) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9943 = or(_T_9942, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9944 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9945 = and(_T_9943, _T_9944) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9946 = bits(_T_9945, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9947 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9946 : @[Reg.scala 28:19]
|
|
_T_9947 <= _T_9935 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][125] <= _T_9947 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9948 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9949 = eq(_T_9948, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9950 = and(ic_valid_ff, _T_9949) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9951 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9952 = and(_T_9950, _T_9951) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9953 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9954 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9955 = and(_T_9953, _T_9954) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9956 = eq(perr_ic_index_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9957 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9958 = and(_T_9956, _T_9957) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9959 = or(_T_9955, _T_9958) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9960 = or(_T_9959, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9961 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9962 = and(_T_9960, _T_9961) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9963 = bits(_T_9962, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9964 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9963 : @[Reg.scala 28:19]
|
|
_T_9964 <= _T_9952 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][126] <= _T_9964 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9965 = bits(reset_all_tags, 0, 0) @[el2_ifu_mem_ctl.scala 754:84]
|
|
node _T_9966 = eq(_T_9965, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:68]
|
|
node _T_9967 = and(ic_valid_ff, _T_9966) @[el2_ifu_mem_ctl.scala 754:66]
|
|
node _T_9968 = eq(perr_sel_invalidate, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 754:93]
|
|
node _T_9969 = and(_T_9967, _T_9968) @[el2_ifu_mem_ctl.scala 754:91]
|
|
node _T_9970 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 755:37]
|
|
node _T_9971 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 755:76]
|
|
node _T_9972 = and(_T_9970, _T_9971) @[el2_ifu_mem_ctl.scala 755:59]
|
|
node _T_9973 = eq(perr_ic_index_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 755:102]
|
|
node _T_9974 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 755:142]
|
|
node _T_9975 = and(_T_9973, _T_9974) @[el2_ifu_mem_ctl.scala 755:124]
|
|
node _T_9976 = or(_T_9972, _T_9975) @[el2_ifu_mem_ctl.scala 755:81]
|
|
node _T_9977 = or(_T_9976, reset_all_tags) @[el2_ifu_mem_ctl.scala 755:147]
|
|
node _T_9978 = bits(tag_valid_clken_3, 1, 1) @[el2_ifu_mem_ctl.scala 755:185]
|
|
node _T_9979 = and(_T_9977, _T_9978) @[el2_ifu_mem_ctl.scala 755:165]
|
|
node _T_9980 = bits(_T_9979, 0, 0) @[el2_ifu_mem_ctl.scala 755:190]
|
|
reg _T_9981 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_9980 : @[Reg.scala 28:19]
|
|
_T_9981 <= _T_9969 @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_tag_valid_out[1][127] <= _T_9981 @[el2_ifu_mem_ctl.scala 754:41]
|
|
node _T_9982 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9983 = mux(_T_9982, ic_tag_valid_out[0][0], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_9984 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9985 = mux(_T_9984, ic_tag_valid_out[0][1], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_9986 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9987 = mux(_T_9986, ic_tag_valid_out[0][2], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_9988 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9989 = mux(_T_9988, ic_tag_valid_out[0][3], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_9990 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9991 = mux(_T_9990, ic_tag_valid_out[0][4], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_9992 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9993 = mux(_T_9992, ic_tag_valid_out[0][5], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_9994 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9995 = mux(_T_9994, ic_tag_valid_out[0][6], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_9996 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9997 = mux(_T_9996, ic_tag_valid_out[0][7], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_9998 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_9999 = mux(_T_9998, ic_tag_valid_out[0][8], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10000 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10001 = mux(_T_10000, ic_tag_valid_out[0][9], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10002 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10003 = mux(_T_10002, ic_tag_valid_out[0][10], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10004 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10005 = mux(_T_10004, ic_tag_valid_out[0][11], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10006 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10007 = mux(_T_10006, ic_tag_valid_out[0][12], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10008 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10009 = mux(_T_10008, ic_tag_valid_out[0][13], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10010 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10011 = mux(_T_10010, ic_tag_valid_out[0][14], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10012 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10013 = mux(_T_10012, ic_tag_valid_out[0][15], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10014 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10015 = mux(_T_10014, ic_tag_valid_out[0][16], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10016 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10017 = mux(_T_10016, ic_tag_valid_out[0][17], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10018 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10019 = mux(_T_10018, ic_tag_valid_out[0][18], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10020 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10021 = mux(_T_10020, ic_tag_valid_out[0][19], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10022 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10023 = mux(_T_10022, ic_tag_valid_out[0][20], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10024 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10025 = mux(_T_10024, ic_tag_valid_out[0][21], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10026 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10027 = mux(_T_10026, ic_tag_valid_out[0][22], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10028 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10029 = mux(_T_10028, ic_tag_valid_out[0][23], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10030 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10031 = mux(_T_10030, ic_tag_valid_out[0][24], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10032 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10033 = mux(_T_10032, ic_tag_valid_out[0][25], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10034 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10035 = mux(_T_10034, ic_tag_valid_out[0][26], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10036 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10037 = mux(_T_10036, ic_tag_valid_out[0][27], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10038 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10039 = mux(_T_10038, ic_tag_valid_out[0][28], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10040 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10041 = mux(_T_10040, ic_tag_valid_out[0][29], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10042 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10043 = mux(_T_10042, ic_tag_valid_out[0][30], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10044 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10045 = mux(_T_10044, ic_tag_valid_out[0][31], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10046 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10047 = mux(_T_10046, ic_tag_valid_out[0][32], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10048 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10049 = mux(_T_10048, ic_tag_valid_out[0][33], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10050 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10051 = mux(_T_10050, ic_tag_valid_out[0][34], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10052 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10053 = mux(_T_10052, ic_tag_valid_out[0][35], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10054 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10055 = mux(_T_10054, ic_tag_valid_out[0][36], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10056 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10057 = mux(_T_10056, ic_tag_valid_out[0][37], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10058 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10059 = mux(_T_10058, ic_tag_valid_out[0][38], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10060 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10061 = mux(_T_10060, ic_tag_valid_out[0][39], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10062 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10063 = mux(_T_10062, ic_tag_valid_out[0][40], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10064 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10065 = mux(_T_10064, ic_tag_valid_out[0][41], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10066 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10067 = mux(_T_10066, ic_tag_valid_out[0][42], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10068 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10069 = mux(_T_10068, ic_tag_valid_out[0][43], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10070 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10071 = mux(_T_10070, ic_tag_valid_out[0][44], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10072 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10073 = mux(_T_10072, ic_tag_valid_out[0][45], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10074 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10075 = mux(_T_10074, ic_tag_valid_out[0][46], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10076 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10077 = mux(_T_10076, ic_tag_valid_out[0][47], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10078 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10079 = mux(_T_10078, ic_tag_valid_out[0][48], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10080 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10081 = mux(_T_10080, ic_tag_valid_out[0][49], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10082 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10083 = mux(_T_10082, ic_tag_valid_out[0][50], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10084 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10085 = mux(_T_10084, ic_tag_valid_out[0][51], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10086 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10087 = mux(_T_10086, ic_tag_valid_out[0][52], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10088 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10089 = mux(_T_10088, ic_tag_valid_out[0][53], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10090 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10091 = mux(_T_10090, ic_tag_valid_out[0][54], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10092 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10093 = mux(_T_10092, ic_tag_valid_out[0][55], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10094 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10095 = mux(_T_10094, ic_tag_valid_out[0][56], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10096 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10097 = mux(_T_10096, ic_tag_valid_out[0][57], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10098 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10099 = mux(_T_10098, ic_tag_valid_out[0][58], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10100 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10101 = mux(_T_10100, ic_tag_valid_out[0][59], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10102 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10103 = mux(_T_10102, ic_tag_valid_out[0][60], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10104 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10105 = mux(_T_10104, ic_tag_valid_out[0][61], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10106 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10107 = mux(_T_10106, ic_tag_valid_out[0][62], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10108 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10109 = mux(_T_10108, ic_tag_valid_out[0][63], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10110 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10111 = mux(_T_10110, ic_tag_valid_out[0][64], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10112 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10113 = mux(_T_10112, ic_tag_valid_out[0][65], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10114 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10115 = mux(_T_10114, ic_tag_valid_out[0][66], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10116 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10117 = mux(_T_10116, ic_tag_valid_out[0][67], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10118 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10119 = mux(_T_10118, ic_tag_valid_out[0][68], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10120 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10121 = mux(_T_10120, ic_tag_valid_out[0][69], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10122 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10123 = mux(_T_10122, ic_tag_valid_out[0][70], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10124 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10125 = mux(_T_10124, ic_tag_valid_out[0][71], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10126 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10127 = mux(_T_10126, ic_tag_valid_out[0][72], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10128 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 758:33]
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|
node _T_10129 = mux(_T_10128, ic_tag_valid_out[0][73], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
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|
node _T_10130 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10131 = mux(_T_10130, ic_tag_valid_out[0][74], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10132 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10133 = mux(_T_10132, ic_tag_valid_out[0][75], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10134 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10135 = mux(_T_10134, ic_tag_valid_out[0][76], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10136 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10137 = mux(_T_10136, ic_tag_valid_out[0][77], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10138 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10139 = mux(_T_10138, ic_tag_valid_out[0][78], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10140 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10141 = mux(_T_10140, ic_tag_valid_out[0][79], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10142 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10143 = mux(_T_10142, ic_tag_valid_out[0][80], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10144 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10145 = mux(_T_10144, ic_tag_valid_out[0][81], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10146 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10147 = mux(_T_10146, ic_tag_valid_out[0][82], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10148 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10149 = mux(_T_10148, ic_tag_valid_out[0][83], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10150 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10151 = mux(_T_10150, ic_tag_valid_out[0][84], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10152 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10153 = mux(_T_10152, ic_tag_valid_out[0][85], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10154 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10155 = mux(_T_10154, ic_tag_valid_out[0][86], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10156 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10157 = mux(_T_10156, ic_tag_valid_out[0][87], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10158 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10159 = mux(_T_10158, ic_tag_valid_out[0][88], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10160 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10161 = mux(_T_10160, ic_tag_valid_out[0][89], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10162 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10163 = mux(_T_10162, ic_tag_valid_out[0][90], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10164 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10165 = mux(_T_10164, ic_tag_valid_out[0][91], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10166 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10167 = mux(_T_10166, ic_tag_valid_out[0][92], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10168 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10169 = mux(_T_10168, ic_tag_valid_out[0][93], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10170 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10171 = mux(_T_10170, ic_tag_valid_out[0][94], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10172 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10173 = mux(_T_10172, ic_tag_valid_out[0][95], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10174 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10175 = mux(_T_10174, ic_tag_valid_out[0][96], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10176 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10177 = mux(_T_10176, ic_tag_valid_out[0][97], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10178 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10179 = mux(_T_10178, ic_tag_valid_out[0][98], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10180 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10181 = mux(_T_10180, ic_tag_valid_out[0][99], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10182 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10183 = mux(_T_10182, ic_tag_valid_out[0][100], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10184 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10185 = mux(_T_10184, ic_tag_valid_out[0][101], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10186 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10187 = mux(_T_10186, ic_tag_valid_out[0][102], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10188 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10189 = mux(_T_10188, ic_tag_valid_out[0][103], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10190 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10191 = mux(_T_10190, ic_tag_valid_out[0][104], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10192 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10193 = mux(_T_10192, ic_tag_valid_out[0][105], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10194 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10195 = mux(_T_10194, ic_tag_valid_out[0][106], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10196 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10197 = mux(_T_10196, ic_tag_valid_out[0][107], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10198 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10199 = mux(_T_10198, ic_tag_valid_out[0][108], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10200 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10201 = mux(_T_10200, ic_tag_valid_out[0][109], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10202 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10203 = mux(_T_10202, ic_tag_valid_out[0][110], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10204 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10205 = mux(_T_10204, ic_tag_valid_out[0][111], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10206 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10207 = mux(_T_10206, ic_tag_valid_out[0][112], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10208 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10209 = mux(_T_10208, ic_tag_valid_out[0][113], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10210 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10211 = mux(_T_10210, ic_tag_valid_out[0][114], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10212 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10213 = mux(_T_10212, ic_tag_valid_out[0][115], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10214 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10215 = mux(_T_10214, ic_tag_valid_out[0][116], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10216 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10217 = mux(_T_10216, ic_tag_valid_out[0][117], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10218 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10219 = mux(_T_10218, ic_tag_valid_out[0][118], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10220 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10221 = mux(_T_10220, ic_tag_valid_out[0][119], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10222 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10223 = mux(_T_10222, ic_tag_valid_out[0][120], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10224 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10225 = mux(_T_10224, ic_tag_valid_out[0][121], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10226 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10227 = mux(_T_10226, ic_tag_valid_out[0][122], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10228 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10229 = mux(_T_10228, ic_tag_valid_out[0][123], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10230 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10231 = mux(_T_10230, ic_tag_valid_out[0][124], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10232 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10233 = mux(_T_10232, ic_tag_valid_out[0][125], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10234 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10235 = mux(_T_10234, ic_tag_valid_out[0][126], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10236 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10237 = mux(_T_10236, ic_tag_valid_out[0][127], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10238 = or(_T_9983, _T_9985) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10239 = or(_T_10238, _T_9987) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10240 = or(_T_10239, _T_9989) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10241 = or(_T_10240, _T_9991) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10242 = or(_T_10241, _T_9993) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10243 = or(_T_10242, _T_9995) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10244 = or(_T_10243, _T_9997) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10245 = or(_T_10244, _T_9999) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10246 = or(_T_10245, _T_10001) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10247 = or(_T_10246, _T_10003) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10248 = or(_T_10247, _T_10005) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10249 = or(_T_10248, _T_10007) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10250 = or(_T_10249, _T_10009) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10251 = or(_T_10250, _T_10011) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10252 = or(_T_10251, _T_10013) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10253 = or(_T_10252, _T_10015) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10254 = or(_T_10253, _T_10017) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10255 = or(_T_10254, _T_10019) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10256 = or(_T_10255, _T_10021) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10257 = or(_T_10256, _T_10023) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10258 = or(_T_10257, _T_10025) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10259 = or(_T_10258, _T_10027) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10260 = or(_T_10259, _T_10029) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10261 = or(_T_10260, _T_10031) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10262 = or(_T_10261, _T_10033) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10263 = or(_T_10262, _T_10035) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10264 = or(_T_10263, _T_10037) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10265 = or(_T_10264, _T_10039) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10266 = or(_T_10265, _T_10041) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10267 = or(_T_10266, _T_10043) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10268 = or(_T_10267, _T_10045) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10269 = or(_T_10268, _T_10047) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10270 = or(_T_10269, _T_10049) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10271 = or(_T_10270, _T_10051) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10272 = or(_T_10271, _T_10053) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10273 = or(_T_10272, _T_10055) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10274 = or(_T_10273, _T_10057) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10275 = or(_T_10274, _T_10059) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10276 = or(_T_10275, _T_10061) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10277 = or(_T_10276, _T_10063) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10278 = or(_T_10277, _T_10065) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10279 = or(_T_10278, _T_10067) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10280 = or(_T_10279, _T_10069) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10281 = or(_T_10280, _T_10071) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10282 = or(_T_10281, _T_10073) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10283 = or(_T_10282, _T_10075) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10284 = or(_T_10283, _T_10077) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10285 = or(_T_10284, _T_10079) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10286 = or(_T_10285, _T_10081) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10287 = or(_T_10286, _T_10083) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10288 = or(_T_10287, _T_10085) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10289 = or(_T_10288, _T_10087) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10290 = or(_T_10289, _T_10089) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10291 = or(_T_10290, _T_10091) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10292 = or(_T_10291, _T_10093) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10293 = or(_T_10292, _T_10095) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10294 = or(_T_10293, _T_10097) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10295 = or(_T_10294, _T_10099) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10296 = or(_T_10295, _T_10101) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10297 = or(_T_10296, _T_10103) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10298 = or(_T_10297, _T_10105) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10299 = or(_T_10298, _T_10107) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10300 = or(_T_10299, _T_10109) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10301 = or(_T_10300, _T_10111) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10302 = or(_T_10301, _T_10113) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10303 = or(_T_10302, _T_10115) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10304 = or(_T_10303, _T_10117) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10305 = or(_T_10304, _T_10119) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10306 = or(_T_10305, _T_10121) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10307 = or(_T_10306, _T_10123) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10308 = or(_T_10307, _T_10125) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10309 = or(_T_10308, _T_10127) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10310 = or(_T_10309, _T_10129) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10311 = or(_T_10310, _T_10131) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10312 = or(_T_10311, _T_10133) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10313 = or(_T_10312, _T_10135) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10314 = or(_T_10313, _T_10137) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10315 = or(_T_10314, _T_10139) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10316 = or(_T_10315, _T_10141) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10317 = or(_T_10316, _T_10143) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10318 = or(_T_10317, _T_10145) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10319 = or(_T_10318, _T_10147) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10320 = or(_T_10319, _T_10149) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10321 = or(_T_10320, _T_10151) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10322 = or(_T_10321, _T_10153) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10323 = or(_T_10322, _T_10155) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10324 = or(_T_10323, _T_10157) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10325 = or(_T_10324, _T_10159) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10326 = or(_T_10325, _T_10161) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10327 = or(_T_10326, _T_10163) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10328 = or(_T_10327, _T_10165) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10329 = or(_T_10328, _T_10167) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10330 = or(_T_10329, _T_10169) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10331 = or(_T_10330, _T_10171) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10332 = or(_T_10331, _T_10173) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10333 = or(_T_10332, _T_10175) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10334 = or(_T_10333, _T_10177) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10335 = or(_T_10334, _T_10179) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10336 = or(_T_10335, _T_10181) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10337 = or(_T_10336, _T_10183) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10338 = or(_T_10337, _T_10185) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10339 = or(_T_10338, _T_10187) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10340 = or(_T_10339, _T_10189) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10341 = or(_T_10340, _T_10191) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10342 = or(_T_10341, _T_10193) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10343 = or(_T_10342, _T_10195) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10344 = or(_T_10343, _T_10197) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10345 = or(_T_10344, _T_10199) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10346 = or(_T_10345, _T_10201) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10347 = or(_T_10346, _T_10203) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10348 = or(_T_10347, _T_10205) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10349 = or(_T_10348, _T_10207) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10350 = or(_T_10349, _T_10209) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10351 = or(_T_10350, _T_10211) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10352 = or(_T_10351, _T_10213) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10353 = or(_T_10352, _T_10215) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10354 = or(_T_10353, _T_10217) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10355 = or(_T_10354, _T_10219) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10356 = or(_T_10355, _T_10221) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10357 = or(_T_10356, _T_10223) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10358 = or(_T_10357, _T_10225) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10359 = or(_T_10358, _T_10227) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10360 = or(_T_10359, _T_10229) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10361 = or(_T_10360, _T_10231) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10362 = or(_T_10361, _T_10233) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10363 = or(_T_10362, _T_10235) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10364 = or(_T_10363, _T_10237) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10365 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10366 = mux(_T_10365, ic_tag_valid_out[1][0], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10367 = eq(ifu_ic_rw_int_addr_ff, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10368 = mux(_T_10367, ic_tag_valid_out[1][1], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10369 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10370 = mux(_T_10369, ic_tag_valid_out[1][2], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10371 = eq(ifu_ic_rw_int_addr_ff, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10372 = mux(_T_10371, ic_tag_valid_out[1][3], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10373 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h04")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10374 = mux(_T_10373, ic_tag_valid_out[1][4], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10375 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h05")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10376 = mux(_T_10375, ic_tag_valid_out[1][5], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10377 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h06")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10378 = mux(_T_10377, ic_tag_valid_out[1][6], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10379 = eq(ifu_ic_rw_int_addr_ff, UInt<3>("h07")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10380 = mux(_T_10379, ic_tag_valid_out[1][7], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10381 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h08")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10382 = mux(_T_10381, ic_tag_valid_out[1][8], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10383 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h09")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10384 = mux(_T_10383, ic_tag_valid_out[1][9], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10385 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10386 = mux(_T_10385, ic_tag_valid_out[1][10], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10387 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10388 = mux(_T_10387, ic_tag_valid_out[1][11], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10389 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10390 = mux(_T_10389, ic_tag_valid_out[1][12], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10391 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10392 = mux(_T_10391, ic_tag_valid_out[1][13], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10393 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10394 = mux(_T_10393, ic_tag_valid_out[1][14], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10395 = eq(ifu_ic_rw_int_addr_ff, UInt<4>("h0f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10396 = mux(_T_10395, ic_tag_valid_out[1][15], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10397 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h010")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10398 = mux(_T_10397, ic_tag_valid_out[1][16], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10399 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h011")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10400 = mux(_T_10399, ic_tag_valid_out[1][17], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10401 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h012")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10402 = mux(_T_10401, ic_tag_valid_out[1][18], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10403 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h013")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10404 = mux(_T_10403, ic_tag_valid_out[1][19], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10405 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h014")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10406 = mux(_T_10405, ic_tag_valid_out[1][20], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10407 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h015")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10408 = mux(_T_10407, ic_tag_valid_out[1][21], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10409 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h016")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10410 = mux(_T_10409, ic_tag_valid_out[1][22], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10411 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h017")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10412 = mux(_T_10411, ic_tag_valid_out[1][23], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10413 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h018")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10414 = mux(_T_10413, ic_tag_valid_out[1][24], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10415 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h019")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10416 = mux(_T_10415, ic_tag_valid_out[1][25], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10417 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10418 = mux(_T_10417, ic_tag_valid_out[1][26], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10419 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10420 = mux(_T_10419, ic_tag_valid_out[1][27], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10421 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10422 = mux(_T_10421, ic_tag_valid_out[1][28], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10423 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10424 = mux(_T_10423, ic_tag_valid_out[1][29], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10425 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10426 = mux(_T_10425, ic_tag_valid_out[1][30], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10427 = eq(ifu_ic_rw_int_addr_ff, UInt<5>("h01f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10428 = mux(_T_10427, ic_tag_valid_out[1][31], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10429 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h020")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10430 = mux(_T_10429, ic_tag_valid_out[1][32], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10431 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h021")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10432 = mux(_T_10431, ic_tag_valid_out[1][33], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10433 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h022")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10434 = mux(_T_10433, ic_tag_valid_out[1][34], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10435 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h023")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10436 = mux(_T_10435, ic_tag_valid_out[1][35], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10437 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h024")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10438 = mux(_T_10437, ic_tag_valid_out[1][36], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10439 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h025")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10440 = mux(_T_10439, ic_tag_valid_out[1][37], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10441 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h026")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10442 = mux(_T_10441, ic_tag_valid_out[1][38], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10443 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h027")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10444 = mux(_T_10443, ic_tag_valid_out[1][39], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10445 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h028")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10446 = mux(_T_10445, ic_tag_valid_out[1][40], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10447 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h029")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10448 = mux(_T_10447, ic_tag_valid_out[1][41], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10449 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10450 = mux(_T_10449, ic_tag_valid_out[1][42], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10451 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10452 = mux(_T_10451, ic_tag_valid_out[1][43], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10453 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10454 = mux(_T_10453, ic_tag_valid_out[1][44], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10455 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10456 = mux(_T_10455, ic_tag_valid_out[1][45], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10457 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10458 = mux(_T_10457, ic_tag_valid_out[1][46], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10459 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h02f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10460 = mux(_T_10459, ic_tag_valid_out[1][47], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10461 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h030")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10462 = mux(_T_10461, ic_tag_valid_out[1][48], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10463 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h031")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10464 = mux(_T_10463, ic_tag_valid_out[1][49], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10465 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h032")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10466 = mux(_T_10465, ic_tag_valid_out[1][50], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10467 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h033")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10468 = mux(_T_10467, ic_tag_valid_out[1][51], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10469 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h034")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10470 = mux(_T_10469, ic_tag_valid_out[1][52], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10471 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h035")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10472 = mux(_T_10471, ic_tag_valid_out[1][53], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10473 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h036")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10474 = mux(_T_10473, ic_tag_valid_out[1][54], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10475 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h037")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10476 = mux(_T_10475, ic_tag_valid_out[1][55], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10477 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h038")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10478 = mux(_T_10477, ic_tag_valid_out[1][56], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10479 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h039")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10480 = mux(_T_10479, ic_tag_valid_out[1][57], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10481 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10482 = mux(_T_10481, ic_tag_valid_out[1][58], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10483 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10484 = mux(_T_10483, ic_tag_valid_out[1][59], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10485 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10486 = mux(_T_10485, ic_tag_valid_out[1][60], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10487 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10488 = mux(_T_10487, ic_tag_valid_out[1][61], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10489 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10490 = mux(_T_10489, ic_tag_valid_out[1][62], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10491 = eq(ifu_ic_rw_int_addr_ff, UInt<6>("h03f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10492 = mux(_T_10491, ic_tag_valid_out[1][63], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10493 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h040")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10494 = mux(_T_10493, ic_tag_valid_out[1][64], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10495 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h041")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10496 = mux(_T_10495, ic_tag_valid_out[1][65], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10497 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h042")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10498 = mux(_T_10497, ic_tag_valid_out[1][66], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10499 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h043")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10500 = mux(_T_10499, ic_tag_valid_out[1][67], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10501 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h044")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10502 = mux(_T_10501, ic_tag_valid_out[1][68], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10503 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h045")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10504 = mux(_T_10503, ic_tag_valid_out[1][69], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10505 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h046")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10506 = mux(_T_10505, ic_tag_valid_out[1][70], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10507 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h047")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10508 = mux(_T_10507, ic_tag_valid_out[1][71], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10509 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h048")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10510 = mux(_T_10509, ic_tag_valid_out[1][72], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10511 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h049")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10512 = mux(_T_10511, ic_tag_valid_out[1][73], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10513 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10514 = mux(_T_10513, ic_tag_valid_out[1][74], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10515 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10516 = mux(_T_10515, ic_tag_valid_out[1][75], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10517 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10518 = mux(_T_10517, ic_tag_valid_out[1][76], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10519 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10520 = mux(_T_10519, ic_tag_valid_out[1][77], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10521 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10522 = mux(_T_10521, ic_tag_valid_out[1][78], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10523 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h04f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10524 = mux(_T_10523, ic_tag_valid_out[1][79], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10525 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h050")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10526 = mux(_T_10525, ic_tag_valid_out[1][80], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10527 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h051")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10528 = mux(_T_10527, ic_tag_valid_out[1][81], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10529 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h052")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10530 = mux(_T_10529, ic_tag_valid_out[1][82], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10531 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h053")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10532 = mux(_T_10531, ic_tag_valid_out[1][83], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10533 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h054")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10534 = mux(_T_10533, ic_tag_valid_out[1][84], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10535 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h055")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10536 = mux(_T_10535, ic_tag_valid_out[1][85], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10537 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h056")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10538 = mux(_T_10537, ic_tag_valid_out[1][86], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10539 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h057")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10540 = mux(_T_10539, ic_tag_valid_out[1][87], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10541 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h058")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10542 = mux(_T_10541, ic_tag_valid_out[1][88], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10543 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h059")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10544 = mux(_T_10543, ic_tag_valid_out[1][89], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10545 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10546 = mux(_T_10545, ic_tag_valid_out[1][90], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10547 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10548 = mux(_T_10547, ic_tag_valid_out[1][91], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10549 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10550 = mux(_T_10549, ic_tag_valid_out[1][92], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10551 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10552 = mux(_T_10551, ic_tag_valid_out[1][93], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10553 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10554 = mux(_T_10553, ic_tag_valid_out[1][94], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10555 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h05f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10556 = mux(_T_10555, ic_tag_valid_out[1][95], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10557 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h060")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10558 = mux(_T_10557, ic_tag_valid_out[1][96], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10559 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h061")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10560 = mux(_T_10559, ic_tag_valid_out[1][97], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10561 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h062")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10562 = mux(_T_10561, ic_tag_valid_out[1][98], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10563 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h063")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10564 = mux(_T_10563, ic_tag_valid_out[1][99], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10565 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h064")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10566 = mux(_T_10565, ic_tag_valid_out[1][100], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10567 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h065")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10568 = mux(_T_10567, ic_tag_valid_out[1][101], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10569 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h066")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10570 = mux(_T_10569, ic_tag_valid_out[1][102], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10571 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h067")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10572 = mux(_T_10571, ic_tag_valid_out[1][103], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10573 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h068")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10574 = mux(_T_10573, ic_tag_valid_out[1][104], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10575 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h069")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10576 = mux(_T_10575, ic_tag_valid_out[1][105], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10577 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10578 = mux(_T_10577, ic_tag_valid_out[1][106], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10579 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10580 = mux(_T_10579, ic_tag_valid_out[1][107], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10581 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10582 = mux(_T_10581, ic_tag_valid_out[1][108], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10583 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10584 = mux(_T_10583, ic_tag_valid_out[1][109], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10585 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10586 = mux(_T_10585, ic_tag_valid_out[1][110], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10587 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h06f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10588 = mux(_T_10587, ic_tag_valid_out[1][111], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10589 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h070")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10590 = mux(_T_10589, ic_tag_valid_out[1][112], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10591 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h071")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10592 = mux(_T_10591, ic_tag_valid_out[1][113], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10593 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h072")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10594 = mux(_T_10593, ic_tag_valid_out[1][114], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10595 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h073")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10596 = mux(_T_10595, ic_tag_valid_out[1][115], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10597 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h074")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10598 = mux(_T_10597, ic_tag_valid_out[1][116], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10599 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h075")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10600 = mux(_T_10599, ic_tag_valid_out[1][117], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10601 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h076")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10602 = mux(_T_10601, ic_tag_valid_out[1][118], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10603 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h077")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10604 = mux(_T_10603, ic_tag_valid_out[1][119], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10605 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h078")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10606 = mux(_T_10605, ic_tag_valid_out[1][120], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10607 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h079")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10608 = mux(_T_10607, ic_tag_valid_out[1][121], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10609 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07a")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10610 = mux(_T_10609, ic_tag_valid_out[1][122], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10611 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07b")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10612 = mux(_T_10611, ic_tag_valid_out[1][123], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10613 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07c")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10614 = mux(_T_10613, ic_tag_valid_out[1][124], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10615 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07d")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10616 = mux(_T_10615, ic_tag_valid_out[1][125], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10617 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07e")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10618 = mux(_T_10617, ic_tag_valid_out[1][126], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10619 = eq(ifu_ic_rw_int_addr_ff, UInt<7>("h07f")) @[el2_ifu_mem_ctl.scala 758:33]
|
|
node _T_10620 = mux(_T_10619, ic_tag_valid_out[1][127], UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 758:10]
|
|
node _T_10621 = or(_T_10366, _T_10368) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10622 = or(_T_10621, _T_10370) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10623 = or(_T_10622, _T_10372) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10624 = or(_T_10623, _T_10374) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10625 = or(_T_10624, _T_10376) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10626 = or(_T_10625, _T_10378) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10627 = or(_T_10626, _T_10380) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10628 = or(_T_10627, _T_10382) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10629 = or(_T_10628, _T_10384) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10630 = or(_T_10629, _T_10386) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10631 = or(_T_10630, _T_10388) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10632 = or(_T_10631, _T_10390) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10633 = or(_T_10632, _T_10392) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10634 = or(_T_10633, _T_10394) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10635 = or(_T_10634, _T_10396) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10636 = or(_T_10635, _T_10398) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10637 = or(_T_10636, _T_10400) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10638 = or(_T_10637, _T_10402) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10639 = or(_T_10638, _T_10404) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10640 = or(_T_10639, _T_10406) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10641 = or(_T_10640, _T_10408) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10642 = or(_T_10641, _T_10410) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10643 = or(_T_10642, _T_10412) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10644 = or(_T_10643, _T_10414) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10645 = or(_T_10644, _T_10416) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10646 = or(_T_10645, _T_10418) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10647 = or(_T_10646, _T_10420) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10648 = or(_T_10647, _T_10422) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10649 = or(_T_10648, _T_10424) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10650 = or(_T_10649, _T_10426) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10651 = or(_T_10650, _T_10428) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10652 = or(_T_10651, _T_10430) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10653 = or(_T_10652, _T_10432) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10654 = or(_T_10653, _T_10434) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10655 = or(_T_10654, _T_10436) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10656 = or(_T_10655, _T_10438) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10657 = or(_T_10656, _T_10440) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10658 = or(_T_10657, _T_10442) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10659 = or(_T_10658, _T_10444) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10660 = or(_T_10659, _T_10446) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10661 = or(_T_10660, _T_10448) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10662 = or(_T_10661, _T_10450) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10663 = or(_T_10662, _T_10452) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10664 = or(_T_10663, _T_10454) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10665 = or(_T_10664, _T_10456) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10666 = or(_T_10665, _T_10458) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10667 = or(_T_10666, _T_10460) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10668 = or(_T_10667, _T_10462) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10669 = or(_T_10668, _T_10464) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10670 = or(_T_10669, _T_10466) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10671 = or(_T_10670, _T_10468) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10672 = or(_T_10671, _T_10470) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10673 = or(_T_10672, _T_10472) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10674 = or(_T_10673, _T_10474) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10675 = or(_T_10674, _T_10476) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10676 = or(_T_10675, _T_10478) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10677 = or(_T_10676, _T_10480) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10678 = or(_T_10677, _T_10482) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10679 = or(_T_10678, _T_10484) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10680 = or(_T_10679, _T_10486) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10681 = or(_T_10680, _T_10488) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10682 = or(_T_10681, _T_10490) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10683 = or(_T_10682, _T_10492) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10684 = or(_T_10683, _T_10494) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10685 = or(_T_10684, _T_10496) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10686 = or(_T_10685, _T_10498) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10687 = or(_T_10686, _T_10500) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10688 = or(_T_10687, _T_10502) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10689 = or(_T_10688, _T_10504) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10690 = or(_T_10689, _T_10506) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10691 = or(_T_10690, _T_10508) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10692 = or(_T_10691, _T_10510) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10693 = or(_T_10692, _T_10512) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10694 = or(_T_10693, _T_10514) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10695 = or(_T_10694, _T_10516) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10696 = or(_T_10695, _T_10518) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10697 = or(_T_10696, _T_10520) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10698 = or(_T_10697, _T_10522) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10699 = or(_T_10698, _T_10524) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10700 = or(_T_10699, _T_10526) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10701 = or(_T_10700, _T_10528) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10702 = or(_T_10701, _T_10530) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10703 = or(_T_10702, _T_10532) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10704 = or(_T_10703, _T_10534) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10705 = or(_T_10704, _T_10536) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10706 = or(_T_10705, _T_10538) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10707 = or(_T_10706, _T_10540) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10708 = or(_T_10707, _T_10542) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10709 = or(_T_10708, _T_10544) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10710 = or(_T_10709, _T_10546) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10711 = or(_T_10710, _T_10548) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10712 = or(_T_10711, _T_10550) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10713 = or(_T_10712, _T_10552) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10714 = or(_T_10713, _T_10554) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10715 = or(_T_10714, _T_10556) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10716 = or(_T_10715, _T_10558) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10717 = or(_T_10716, _T_10560) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10718 = or(_T_10717, _T_10562) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10719 = or(_T_10718, _T_10564) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10720 = or(_T_10719, _T_10566) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10721 = or(_T_10720, _T_10568) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10722 = or(_T_10721, _T_10570) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10723 = or(_T_10722, _T_10572) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10724 = or(_T_10723, _T_10574) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10725 = or(_T_10724, _T_10576) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10726 = or(_T_10725, _T_10578) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10727 = or(_T_10726, _T_10580) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10728 = or(_T_10727, _T_10582) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10729 = or(_T_10728, _T_10584) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10730 = or(_T_10729, _T_10586) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10731 = or(_T_10730, _T_10588) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10732 = or(_T_10731, _T_10590) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10733 = or(_T_10732, _T_10592) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10734 = or(_T_10733, _T_10594) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10735 = or(_T_10734, _T_10596) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10736 = or(_T_10735, _T_10598) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10737 = or(_T_10736, _T_10600) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10738 = or(_T_10737, _T_10602) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10739 = or(_T_10738, _T_10604) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10740 = or(_T_10739, _T_10606) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10741 = or(_T_10740, _T_10608) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10742 = or(_T_10741, _T_10610) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10743 = or(_T_10742, _T_10612) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10744 = or(_T_10743, _T_10614) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10745 = or(_T_10744, _T_10616) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10746 = or(_T_10745, _T_10618) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node _T_10747 = or(_T_10746, _T_10620) @[el2_ifu_mem_ctl.scala 758:91]
|
|
node ic_tag_valid_unq = cat(_T_10747, _T_10364) @[Cat.scala 29:58]
|
|
wire way_status_hit_new : UInt<1>
|
|
way_status_hit_new <= UInt<1>("h00")
|
|
node _T_10748 = eq(way_status_mb_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 783:33]
|
|
node _T_10749 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 783:63]
|
|
node _T_10750 = and(_T_10748, _T_10749) @[el2_ifu_mem_ctl.scala 783:51]
|
|
node _T_10751 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 783:79]
|
|
node _T_10752 = and(_T_10750, _T_10751) @[el2_ifu_mem_ctl.scala 783:67]
|
|
node _T_10753 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 783:97]
|
|
node _T_10754 = eq(_T_10753, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 783:86]
|
|
node _T_10755 = or(_T_10752, _T_10754) @[el2_ifu_mem_ctl.scala 783:84]
|
|
replace_way_mb_any[0] <= _T_10755 @[el2_ifu_mem_ctl.scala 783:29]
|
|
node _T_10756 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 784:62]
|
|
node _T_10757 = and(way_status_mb_ff, _T_10756) @[el2_ifu_mem_ctl.scala 784:50]
|
|
node _T_10758 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 784:78]
|
|
node _T_10759 = and(_T_10757, _T_10758) @[el2_ifu_mem_ctl.scala 784:66]
|
|
node _T_10760 = bits(tagv_mb_ff, 1, 1) @[el2_ifu_mem_ctl.scala 784:96]
|
|
node _T_10761 = eq(_T_10760, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 784:85]
|
|
node _T_10762 = bits(tagv_mb_ff, 0, 0) @[el2_ifu_mem_ctl.scala 784:112]
|
|
node _T_10763 = and(_T_10761, _T_10762) @[el2_ifu_mem_ctl.scala 784:100]
|
|
node _T_10764 = or(_T_10759, _T_10763) @[el2_ifu_mem_ctl.scala 784:83]
|
|
replace_way_mb_any[1] <= _T_10764 @[el2_ifu_mem_ctl.scala 784:29]
|
|
node _T_10765 = bits(io.ic_rd_hit, 0, 0) @[el2_ifu_mem_ctl.scala 785:41]
|
|
way_status_hit_new <= _T_10765 @[el2_ifu_mem_ctl.scala 785:26]
|
|
way_status_rep_new <= replace_way_mb_any[0] @[el2_ifu_mem_ctl.scala 786:26]
|
|
node _T_10766 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 788:47]
|
|
node _T_10767 = bits(_T_10766, 0, 0) @[el2_ifu_mem_ctl.scala 788:60]
|
|
node _T_10768 = mux(_T_10767, way_status_rep_new, way_status_hit_new) @[el2_ifu_mem_ctl.scala 788:26]
|
|
way_status_new <= _T_10768 @[el2_ifu_mem_ctl.scala 788:20]
|
|
node _T_10769 = and(bus_ifu_wr_en_ff_q, last_beat) @[el2_ifu_mem_ctl.scala 789:45]
|
|
node _T_10770 = or(_T_10769, ic_act_hit_f) @[el2_ifu_mem_ctl.scala 789:58]
|
|
way_status_wr_en <= _T_10770 @[el2_ifu_mem_ctl.scala 789:22]
|
|
node _T_10771 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 790:74]
|
|
node bus_wren_0 = and(_T_10771, miss_pending) @[el2_ifu_mem_ctl.scala 790:98]
|
|
node _T_10772 = and(bus_ifu_wr_en_ff_q, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 790:74]
|
|
node bus_wren_1 = and(_T_10772, miss_pending) @[el2_ifu_mem_ctl.scala 790:98]
|
|
node _T_10773 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[0]) @[el2_ifu_mem_ctl.scala 792:84]
|
|
node _T_10774 = and(_T_10773, miss_pending) @[el2_ifu_mem_ctl.scala 792:108]
|
|
node bus_wren_last_0 = and(_T_10774, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node _T_10775 = and(bus_ifu_wr_en_ff_wo_err, replace_way_mb_any[1]) @[el2_ifu_mem_ctl.scala 792:84]
|
|
node _T_10776 = and(_T_10775, miss_pending) @[el2_ifu_mem_ctl.scala 792:108]
|
|
node bus_wren_last_1 = and(_T_10776, bus_last_data_beat) @[el2_ifu_mem_ctl.scala 792:123]
|
|
node wren_reset_miss_0 = and(replace_way_mb_any[0], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 793:84]
|
|
node wren_reset_miss_1 = and(replace_way_mb_any[1], reset_tag_valid_for_miss) @[el2_ifu_mem_ctl.scala 793:84]
|
|
node _T_10777 = or(bus_wren_last_0, wren_reset_miss_0) @[el2_ifu_mem_ctl.scala 794:73]
|
|
node _T_10778 = or(bus_wren_last_1, wren_reset_miss_1) @[el2_ifu_mem_ctl.scala 794:73]
|
|
node _T_10779 = cat(_T_10778, _T_10777) @[Cat.scala 29:58]
|
|
ifu_tag_wren <= _T_10779 @[el2_ifu_mem_ctl.scala 794:18]
|
|
node _T_10780 = cat(bus_wren_1, bus_wren_0) @[Cat.scala 29:58]
|
|
bus_ic_wr_en <= _T_10780 @[el2_ifu_mem_ctl.scala 796:16]
|
|
node _T_10781 = eq(fetch_uncacheable_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 810:63]
|
|
node _T_10782 = and(_T_10781, ifc_fetch_req_f) @[el2_ifu_mem_ctl.scala 810:85]
|
|
node _T_10783 = bits(_T_10782, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10784 = mux(_T_10783, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10785 = and(ic_tag_valid_unq, _T_10784) @[el2_ifu_mem_ctl.scala 810:39]
|
|
io.ic_tag_valid <= _T_10785 @[el2_ifu_mem_ctl.scala 810:19]
|
|
wire ic_debug_way_ff : UInt<2>
|
|
ic_debug_way_ff <= UInt<1>("h00")
|
|
node _T_10786 = bits(ic_debug_rd_en_ff, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10787 = mux(_T_10786, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10788 = and(ic_debug_way_ff, _T_10787) @[el2_ifu_mem_ctl.scala 813:67]
|
|
node _T_10789 = and(ic_tag_valid_unq, _T_10788) @[el2_ifu_mem_ctl.scala 813:48]
|
|
node _T_10790 = orr(_T_10789) @[el2_ifu_mem_ctl.scala 813:115]
|
|
ic_debug_tag_val_rd_out <= _T_10790 @[el2_ifu_mem_ctl.scala 813:27]
|
|
reg _T_10791 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 815:57]
|
|
_T_10791 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 815:57]
|
|
io.ifu_pmu_ic_miss <= _T_10791 @[el2_ifu_mem_ctl.scala 815:22]
|
|
reg _T_10792 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 816:56]
|
|
_T_10792 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 816:56]
|
|
io.ifu_pmu_ic_hit <= _T_10792 @[el2_ifu_mem_ctl.scala 816:21]
|
|
reg _T_10793 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 817:59]
|
|
_T_10793 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 817:59]
|
|
io.ifu_pmu_bus_error <= _T_10793 @[el2_ifu_mem_ctl.scala 817:24]
|
|
node _T_10794 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 818:80]
|
|
node _T_10795 = and(ifu_bus_arvalid_ff, _T_10794) @[el2_ifu_mem_ctl.scala 818:78]
|
|
node _T_10796 = and(_T_10795, miss_pending) @[el2_ifu_mem_ctl.scala 818:100]
|
|
reg _T_10797 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 818:58]
|
|
_T_10797 <= _T_10796 @[el2_ifu_mem_ctl.scala 818:58]
|
|
io.ifu_pmu_bus_busy <= _T_10797 @[el2_ifu_mem_ctl.scala 818:23]
|
|
reg _T_10798 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 819:58]
|
|
_T_10798 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 819:58]
|
|
io.ifu_pmu_bus_trxn <= _T_10798 @[el2_ifu_mem_ctl.scala 819:23]
|
|
io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 822:20]
|
|
node _T_10799 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 823:66]
|
|
io.ic_debug_tag_array <= _T_10799 @[el2_ifu_mem_ctl.scala 823:25]
|
|
io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 824:21]
|
|
io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 825:21]
|
|
node _T_10800 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 826:64]
|
|
node _T_10801 = eq(_T_10800, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 826:71]
|
|
node _T_10802 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 826:117]
|
|
node _T_10803 = eq(_T_10802, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 826:124]
|
|
node _T_10804 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 827:43]
|
|
node _T_10805 = eq(_T_10804, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 827:50]
|
|
node _T_10806 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 827:96]
|
|
node _T_10807 = eq(_T_10806, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 827:103]
|
|
node _T_10808 = cat(_T_10805, _T_10807) @[Cat.scala 29:58]
|
|
node _T_10809 = cat(_T_10801, _T_10803) @[Cat.scala 29:58]
|
|
node _T_10810 = cat(_T_10809, _T_10808) @[Cat.scala 29:58]
|
|
io.ic_debug_way <= _T_10810 @[el2_ifu_mem_ctl.scala 826:19]
|
|
node _T_10811 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 828:65]
|
|
node _T_10812 = bits(_T_10811, 0, 0) @[Bitwise.scala 72:15]
|
|
node _T_10813 = mux(_T_10812, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
|
node _T_10814 = and(_T_10813, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 828:90]
|
|
ic_debug_tag_wr_en <= _T_10814 @[el2_ifu_mem_ctl.scala 828:22]
|
|
node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 829:53]
|
|
node _T_10815 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 830:72]
|
|
reg _T_10816 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_10815 : @[Reg.scala 28:19]
|
|
_T_10816 <= io.ic_debug_way @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_debug_way_ff <= _T_10816 @[el2_ifu_mem_ctl.scala 830:19]
|
|
node _T_10817 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 831:92]
|
|
reg _T_10818 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_10817 : @[Reg.scala 28:19]
|
|
_T_10818 <= ic_debug_ict_array_sel_in @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
ic_debug_ict_array_sel_ff <= _T_10818 @[el2_ifu_mem_ctl.scala 831:29]
|
|
reg _T_10819 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 832:54]
|
|
_T_10819 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 832:54]
|
|
ic_debug_rd_en_ff <= _T_10819 @[el2_ifu_mem_ctl.scala 832:21]
|
|
node _T_10820 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 833:111]
|
|
reg _T_10821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
when _T_10820 : @[Reg.scala 28:19]
|
|
_T_10821 <= ic_debug_rd_en_ff @[Reg.scala 28:23]
|
|
skip @[Reg.scala 28:19]
|
|
io.ifu_ic_debug_rd_data_valid <= _T_10821 @[el2_ifu_mem_ctl.scala 833:33]
|
|
node _T_10822 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10823 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10824 = cat(_T_10823, _T_10822) @[Cat.scala 29:58]
|
|
node _T_10825 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_10826 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
|
node _T_10827 = cat(_T_10826, _T_10825) @[Cat.scala 29:58]
|
|
node _T_10828 = cat(_T_10827, _T_10824) @[Cat.scala 29:58]
|
|
node _T_10829 = orr(_T_10828) @[el2_ifu_mem_ctl.scala 834:213]
|
|
node _T_10830 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10831 = or(_T_10830, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 835:62]
|
|
node _T_10832 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 835:110]
|
|
node _T_10833 = eq(_T_10831, _T_10832) @[el2_ifu_mem_ctl.scala 835:85]
|
|
node _T_10834 = and(UInt<1>("h01"), _T_10833) @[el2_ifu_mem_ctl.scala 835:27]
|
|
node _T_10835 = or(_T_10829, _T_10834) @[el2_ifu_mem_ctl.scala 834:216]
|
|
node _T_10836 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10837 = or(_T_10836, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 836:62]
|
|
node _T_10838 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 836:110]
|
|
node _T_10839 = eq(_T_10837, _T_10838) @[el2_ifu_mem_ctl.scala 836:85]
|
|
node _T_10840 = and(UInt<1>("h01"), _T_10839) @[el2_ifu_mem_ctl.scala 836:27]
|
|
node _T_10841 = or(_T_10835, _T_10840) @[el2_ifu_mem_ctl.scala 835:134]
|
|
node _T_10842 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10843 = or(_T_10842, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 837:62]
|
|
node _T_10844 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 837:110]
|
|
node _T_10845 = eq(_T_10843, _T_10844) @[el2_ifu_mem_ctl.scala 837:85]
|
|
node _T_10846 = and(UInt<1>("h01"), _T_10845) @[el2_ifu_mem_ctl.scala 837:27]
|
|
node _T_10847 = or(_T_10841, _T_10846) @[el2_ifu_mem_ctl.scala 836:134]
|
|
node _T_10848 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10849 = or(_T_10848, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 838:62]
|
|
node _T_10850 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 838:110]
|
|
node _T_10851 = eq(_T_10849, _T_10850) @[el2_ifu_mem_ctl.scala 838:85]
|
|
node _T_10852 = and(UInt<1>("h01"), _T_10851) @[el2_ifu_mem_ctl.scala 838:27]
|
|
node _T_10853 = or(_T_10847, _T_10852) @[el2_ifu_mem_ctl.scala 837:134]
|
|
node _T_10854 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10855 = or(_T_10854, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 839:62]
|
|
node _T_10856 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 839:110]
|
|
node _T_10857 = eq(_T_10855, _T_10856) @[el2_ifu_mem_ctl.scala 839:85]
|
|
node _T_10858 = and(UInt<1>("h00"), _T_10857) @[el2_ifu_mem_ctl.scala 839:27]
|
|
node _T_10859 = or(_T_10853, _T_10858) @[el2_ifu_mem_ctl.scala 838:134]
|
|
node _T_10860 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10861 = or(_T_10860, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 840:62]
|
|
node _T_10862 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 840:110]
|
|
node _T_10863 = eq(_T_10861, _T_10862) @[el2_ifu_mem_ctl.scala 840:85]
|
|
node _T_10864 = and(UInt<1>("h00"), _T_10863) @[el2_ifu_mem_ctl.scala 840:27]
|
|
node _T_10865 = or(_T_10859, _T_10864) @[el2_ifu_mem_ctl.scala 839:134]
|
|
node _T_10866 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10867 = or(_T_10866, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 841:62]
|
|
node _T_10868 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 841:110]
|
|
node _T_10869 = eq(_T_10867, _T_10868) @[el2_ifu_mem_ctl.scala 841:85]
|
|
node _T_10870 = and(UInt<1>("h00"), _T_10869) @[el2_ifu_mem_ctl.scala 841:27]
|
|
node _T_10871 = or(_T_10865, _T_10870) @[el2_ifu_mem_ctl.scala 840:134]
|
|
node _T_10872 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
node _T_10873 = or(_T_10872, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 842:62]
|
|
node _T_10874 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 842:110]
|
|
node _T_10875 = eq(_T_10873, _T_10874) @[el2_ifu_mem_ctl.scala 842:85]
|
|
node _T_10876 = and(UInt<1>("h00"), _T_10875) @[el2_ifu_mem_ctl.scala 842:27]
|
|
node ifc_region_acc_okay = or(_T_10871, _T_10876) @[el2_ifu_mem_ctl.scala 841:134]
|
|
node _T_10877 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 843:40]
|
|
node _T_10878 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 843:65]
|
|
node _T_10879 = and(_T_10877, _T_10878) @[el2_ifu_mem_ctl.scala 843:63]
|
|
node ifc_region_acc_fault_memory_bf = and(_T_10879, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 843:86]
|
|
node _T_10880 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 844:63]
|
|
ifc_region_acc_fault_final_bf <= _T_10880 @[el2_ifu_mem_ctl.scala 844:33]
|
|
reg _T_10881 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 845:66]
|
|
_T_10881 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 845:66]
|
|
ifc_region_acc_fault_memory_f <= _T_10881 @[el2_ifu_mem_ctl.scala 845:33]
|
|
io.tagv_mb_in <= tagv_mb_in @[el2_ifu_mem_ctl.scala 848:17]
|
|
|