199 lines
6.6 KiB
Verilog
199 lines
6.6 KiB
Verilog
module rvclkhdr(
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output io_l1clk,
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input io_clk,
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input io_en
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);
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wire clkhdr_Q; // @[lib.scala 334:26]
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wire clkhdr_CK; // @[lib.scala 334:26]
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wire clkhdr_EN; // @[lib.scala 334:26]
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wire clkhdr_SE; // @[lib.scala 334:26]
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gated_latch clkhdr ( // @[lib.scala 334:26]
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.Q(clkhdr_Q),
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.CK(clkhdr_CK),
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.EN(clkhdr_EN),
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.SE(clkhdr_SE)
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);
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assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14]
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assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
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assign clkhdr_EN = io_en; // @[lib.scala 337:18]
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assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
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endmodule
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module exu_mul_ctl(
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input clock,
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input reset,
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input io_scan_mode,
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input io_mul_p_valid,
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input io_mul_p_bits_rs1_sign,
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input io_mul_p_bits_rs2_sign,
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input io_mul_p_bits_low,
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input io_mul_p_bits_bext,
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input io_mul_p_bits_bdep,
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input io_mul_p_bits_clmul,
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input io_mul_p_bits_clmulh,
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input io_mul_p_bits_clmulr,
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input io_mul_p_bits_grev,
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input io_mul_p_bits_gorc,
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input io_mul_p_bits_shfl,
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input io_mul_p_bits_unshfl,
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input io_mul_p_bits_crc32_b,
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input io_mul_p_bits_crc32_h,
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input io_mul_p_bits_crc32_w,
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input io_mul_p_bits_crc32c_b,
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input io_mul_p_bits_crc32c_h,
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input io_mul_p_bits_crc32c_w,
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input io_mul_p_bits_bfp,
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input [31:0] io_rs1_in,
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input [31:0] io_rs2_in,
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output [31:0] io_result_x
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);
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_0;
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reg [63:0] _RAND_1;
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reg [63:0] _RAND_2;
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`endif // RANDOMIZE_REG_INIT
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wire rvclkhdr_io_l1clk; // @[lib.scala 399:23]
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wire rvclkhdr_io_clk; // @[lib.scala 399:23]
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wire rvclkhdr_io_en; // @[lib.scala 399:23]
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wire rvclkhdr_1_io_l1clk; // @[lib.scala 422:23]
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wire rvclkhdr_1_io_clk; // @[lib.scala 422:23]
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wire rvclkhdr_1_io_en; // @[lib.scala 422:23]
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wire rvclkhdr_2_io_l1clk; // @[lib.scala 422:23]
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wire rvclkhdr_2_io_clk; // @[lib.scala 422:23]
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wire rvclkhdr_2_io_en; // @[lib.scala 422:23]
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wire rvclkhdr_3_io_l1clk; // @[lib.scala 399:23]
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wire rvclkhdr_3_io_clk; // @[lib.scala 399:23]
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wire rvclkhdr_3_io_en; // @[lib.scala 399:23]
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wire rvclkhdr_4_io_l1clk; // @[lib.scala 399:23]
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wire rvclkhdr_4_io_clk; // @[lib.scala 399:23]
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wire rvclkhdr_4_io_en; // @[lib.scala 399:23]
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wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[exu_mul_ctl.scala 123:44]
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wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[exu_mul_ctl.scala 124:44]
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reg low_x; // @[Reg.scala 27:20]
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reg [32:0] rs1_x; // @[lib.scala 428:16]
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reg [32:0] rs2_x; // @[lib.scala 428:16]
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wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[exu_mul_ctl.scala 130:20]
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wire _T_39758 = ~low_x; // @[exu_mul_ctl.scala 388:46]
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wire [7:0] _T_39762 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758}; // @[Cat.scala 29:58]
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wire [15:0] _T_39763 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39762}; // @[Cat.scala 29:58]
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wire [31:0] _T_39764 = {_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39758,_T_39762,_T_39763}; // @[Cat.scala 29:58]
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wire [31:0] _T_39766 = _T_39764 & prod_x[63:32]; // @[exu_mul_ctl.scala 388:54]
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wire [7:0] _T_39771 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x}; // @[Cat.scala 29:58]
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wire [15:0] _T_39772 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771}; // @[Cat.scala 29:58]
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wire [31:0] _T_39773 = {low_x,low_x,low_x,low_x,low_x,low_x,low_x,low_x,_T_39771,_T_39772}; // @[Cat.scala 29:58]
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wire [31:0] _T_39775 = _T_39773 & prod_x[31:0]; // @[exu_mul_ctl.scala 389:40]
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rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
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.io_l1clk(rvclkhdr_io_l1clk),
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.io_clk(rvclkhdr_io_clk),
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.io_en(rvclkhdr_io_en)
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);
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rvclkhdr rvclkhdr_1 ( // @[lib.scala 422:23]
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.io_l1clk(rvclkhdr_1_io_l1clk),
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.io_clk(rvclkhdr_1_io_clk),
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.io_en(rvclkhdr_1_io_en)
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);
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rvclkhdr rvclkhdr_2 ( // @[lib.scala 422:23]
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.io_l1clk(rvclkhdr_2_io_l1clk),
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.io_clk(rvclkhdr_2_io_clk),
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.io_en(rvclkhdr_2_io_en)
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);
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rvclkhdr rvclkhdr_3 ( // @[lib.scala 399:23]
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.io_l1clk(rvclkhdr_3_io_l1clk),
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.io_clk(rvclkhdr_3_io_clk),
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.io_en(rvclkhdr_3_io_en)
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);
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rvclkhdr rvclkhdr_4 ( // @[lib.scala 399:23]
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.io_l1clk(rvclkhdr_4_io_l1clk),
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.io_clk(rvclkhdr_4_io_clk),
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.io_en(rvclkhdr_4_io_en)
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);
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assign io_result_x = _T_39766 | _T_39775; // @[exu_mul_ctl.scala 388:15]
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assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
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assign rvclkhdr_io_en = io_mul_p_valid; // @[lib.scala 402:17]
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assign rvclkhdr_1_io_clk = clock; // @[lib.scala 424:18]
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assign rvclkhdr_1_io_en = io_mul_p_valid; // @[lib.scala 425:17]
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assign rvclkhdr_2_io_clk = clock; // @[lib.scala 424:18]
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assign rvclkhdr_2_io_en = io_mul_p_valid; // @[lib.scala 425:17]
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assign rvclkhdr_3_io_clk = clock; // @[lib.scala 401:18]
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assign rvclkhdr_3_io_en = io_mul_p_valid; // @[lib.scala 402:17]
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assign rvclkhdr_4_io_clk = clock; // @[lib.scala 401:18]
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assign rvclkhdr_4_io_en = io_mul_p_valid; // @[lib.scala 402:17]
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_INVALID_ASSIGN
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif
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`ifndef RANDOM
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`define RANDOM $random
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`endif
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`ifdef RANDOMIZE_MEM_INIT
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integer initvar;
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`endif
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`ifndef SYNTHESIS
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif
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initial begin
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`ifdef RANDOMIZE
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`ifdef INIT_RANDOM
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`INIT_RANDOM
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`endif
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`ifndef VERILATOR
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`ifdef RANDOMIZE_DELAY
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#`RANDOMIZE_DELAY begin end
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`else
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#0.002 begin end
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`endif
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`endif
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`ifdef RANDOMIZE_REG_INIT
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_RAND_0 = {1{`RANDOM}};
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low_x = _RAND_0[0:0];
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_RAND_1 = {2{`RANDOM}};
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rs1_x = _RAND_1[32:0];
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_RAND_2 = {2{`RANDOM}};
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rs2_x = _RAND_2[32:0];
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`endif // RANDOMIZE_REG_INIT
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if (reset) begin
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low_x = 1'h0;
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end
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if (reset) begin
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rs1_x = 33'sh0;
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end
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if (reset) begin
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rs2_x = 33'sh0;
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end
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`endif // RANDOMIZE
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif
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`endif // SYNTHESIS
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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low_x <= 1'h0;
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end else if (io_mul_p_valid) begin
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low_x <= io_mul_p_bits_low;
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end
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end
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always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
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if (reset) begin
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rs1_x <= 33'sh0;
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end else begin
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rs1_x <= {_T_1,io_rs1_in};
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end
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end
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always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin
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if (reset) begin
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rs2_x <= 33'sh0;
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end else begin
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rs2_x <= {_T_5,io_rs2_in};
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end
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end
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endmodule
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