302 lines
18 KiB
Scala
302 lines
18 KiB
Scala
//package dec
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//import chisel3._
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//import chisel3.util._
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//import include._
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//import lib._
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//import lsu._
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//
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//class dec_IO extends Bundle with lib {
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// val free_clk = Input(Clock())
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// val active_clk = Input(Clock())
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// val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
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// val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
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// val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins
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//
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// val nmi_int = Input(Bool()) // NMI pin
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// val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins
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//
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// val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
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// val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
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//
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// val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
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// val o_cpu_halt_ack = Output(Bool()) // Halt request ack
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// val o_cpu_run_ack = Output(Bool()) // Run request ack
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// val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
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//
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// val core_id = Input(UInt(28.W)) // [31:4] CORE ID
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//
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// val mpc_debug_halt_req = Input(Bool()) // Async halt request
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// val mpc_debug_run_req = Input(Bool()) // Async run request
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// val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
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// val mpc_debug_halt_ack = Output(Bool()) // Halt ack
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// val mpc_debug_run_ack = Output(Bool()) // Run ack
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// val debug_brkpt_status = Output(Bool()) // debug breakpoint
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// val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
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//
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//
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// val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address
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// val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
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//
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// val lsu_trigger_match_m = Input(UInt(4.W))
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// val lsu_idle_any = Input(Bool()) // lsu idle for halting
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// val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet
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// val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
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// val exu_div_result = Input(UInt(32.W)) // final div result
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// val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
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// val lsu_result_m = Input(UInt(32.W)) // load result
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// val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
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//
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// val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
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// val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
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//
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//
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// val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
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//
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// val exu_flush_final = Input(Bool()) // slot0 flush
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// val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
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// val soft_int = Input(Bool()) // Software interrupt pending (from pin)
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//
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//
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//
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// // Debug start
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// val dbg_halt_req = Input(Bool()) // DM requests a halt
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// val dbg_resume_req = Input(Bool()) // DM requests a resume
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// val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
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// val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
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// val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
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// val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
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// val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
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//
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// val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
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// val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
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//
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// val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks
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// val exu_i0_br_way_r = Input(Bool()) // way hit or repl
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// val lsu_p = Valid(new lsu_pkt_t) // lsu packet
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// val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
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// val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
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// val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
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// val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
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// val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
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// val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
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// val dec_lsu_valid_raw_d = Output(Bool())
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// val rv_trace_pkt = (new trace_pkt_t) // trace packet
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//
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// // clock gating overrides from mcgc
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// val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
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// val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
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// val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
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// val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
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// val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
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// val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
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// val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
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//
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// val scan_mode = Input(Bool())
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// val ifu_dec = Flipped(new ifu_dec)
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// val dec_exu = Flipped(new dec_exu)
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// val lsu_dec = Flipped (new lsu_dec)
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// val lsu_tlu = Flipped (new lsu_tlu)
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// val dec_dbg = new dec_dbg
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// val dec_dma = new dec_dma
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// val dec_pic = new dec_pic
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//}
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//class dec extends Module with param with RequireAsyncReset{
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// val io = IO(new dec_IO)
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//
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// val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
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// val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
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// val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
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// val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
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//
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// val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
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// val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
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// val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
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//
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//
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// //--------------------------------------------------------------------------//
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// val instbuff = Module(new dec_ib_ctl)
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// val decode = Module(new dec_decode_ctl)
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// val gpr = Module(new dec_gpr_ctl)
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// val tlu = Module(new dec_tlu_ctl)
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// val dec_trigger = Module(new dec_trigger)
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//
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// //connections for dec_Ib
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// //inputs
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// instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib
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// instbuff.io.ib_exu <> io.dec_exu.ib_exu
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// instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib
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// dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
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// dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
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//
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// val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
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// dontTouch(dec_i0_trigger_match_d)
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// decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
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//
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// decode.io.decode_exu<> io.dec_exu.decode_exu
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// decode.io.dec_alu<> io.dec_exu.dec_alu
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// decode.io.dec_div<> io.dec_exu.dec_div
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// decode.io.dctl_dma <> io.dec_dma.dctl_dma
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// decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
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// decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt
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// decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff
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// decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
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// decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
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// decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
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// decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
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// decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m
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// decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
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// decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb
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// decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
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// decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl
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// decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
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// decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d
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// decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
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// decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
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// decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
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// decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
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// decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
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// decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
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// decode.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
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// decode.io.lsu_idle_any := io.lsu_idle_any
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// decode.io.lsu_load_stall_any := io.lsu_load_stall_any
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// decode.io.lsu_store_stall_any := io.lsu_store_stall_any
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// decode.io.exu_div_wren := io.exu_div_wren
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// decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
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// decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
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// decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
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// decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r
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// decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
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// decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
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// decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
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// decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d
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// decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
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// decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
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// decode.io.lsu_result_m := io.lsu_result_m
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// decode.io.lsu_result_corr_r := io.lsu_result_corr_r
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// decode.io.exu_flush_final := io.exu_flush_final
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// decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
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// decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
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// decode.io.free_clk := io.free_clk
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// decode.io.active_clk := io.active_clk
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// decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
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// decode.io.scan_mode := io.scan_mode
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// dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer
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// dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer
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// io.lsu_p := decode.io.lsu_p
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// io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
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// io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
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// io.dec_pause_state_cg := decode.io.dec_pause_state_cg
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// gpr.io.raddr0 := decode.io.dec_i0_rs1_d
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// gpr.io.raddr1 := decode.io.dec_i0_rs2_d
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// gpr.io.wen0 := decode.io.dec_i0_wen_r
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// gpr.io.waddr0 := decode.io.dec_i0_waddr_r
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// gpr.io.wd0 := decode.io.dec_i0_wdata_r
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// gpr.io.wen1 := decode.io.dec_nonblock_load_wen
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// gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
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// gpr.io.wd1 := io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data
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// gpr.io.wen2 := io.exu_div_wren
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// gpr.io.waddr2 := decode.io.div_waddr_wb
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// gpr.io.wd2 := io.exu_div_result
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// gpr.io.scan_mode := io.scan_mode
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// io.dec_exu.gpr_exu <> gpr.io.gpr_exu
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// tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl
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// tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc
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// tlu.io.tlu_bp <> io.ifu_dec.dec_bp
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// tlu.io.tlu_exu <> io.dec_exu.tlu_exu
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// tlu.io.tlu_dma <> io.dec_dma.tlu_dma
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// tlu.io.active_clk := io.active_clk
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// tlu.io.free_clk := io.free_clk
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// tlu.io.scan_mode := io.scan_mode
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// tlu.io.rst_vec := io.rst_vec
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// tlu.io.nmi_int := io.nmi_int
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// tlu.io.nmi_vec := io.nmi_vec
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// tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
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// tlu.io.i_cpu_run_req := io.i_cpu_run_req
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// tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
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// tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned
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// tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
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// tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
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// tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
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// tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
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// tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
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// io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff
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// io.lsu_tlu <> tlu.io.lsu_tlu
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// io.dec_pic <> tlu.io.dec_pic
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// tlu.io.lsu_fir_addr := io.lsu_fir_addr
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// tlu.io.lsu_fir_error := io.lsu_fir_error
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// tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
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// tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
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// tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
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// tlu.io.dec_pause_state := decode.io.dec_pause_state
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// tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
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// tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
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// tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
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// tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
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// tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
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// tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
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// tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
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// tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
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// tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
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// tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
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// tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
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// tlu.io.dec_i0_decode_d := decode.io.dec_aln.dec_i0_decode_d
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// tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
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// tlu.io.dbg_halt_req := io.dbg_halt_req
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// tlu.io.dbg_resume_req := io.dbg_resume_req
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// tlu.io.lsu_idle_any := io.lsu_idle_any
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// tlu.io.dec_div_active := decode.io.dec_div_active
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// tlu.io.timer_int := io.timer_int
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// tlu.io.soft_int := io.soft_int
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// tlu.io.core_id := io.core_id
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// tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
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// tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
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// tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
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// io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
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// io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
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// io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
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// io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
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// io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
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// io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
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// io.trigger_pkt_any := tlu.io.trigger_pkt_any
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// io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
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// io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
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// io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
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// io.o_debug_mode_status := tlu.io.o_debug_mode_status
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// io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
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// io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
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// io.debug_brkpt_status := tlu.io.debug_brkpt_status
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// io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
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// io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
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// io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
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// io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
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// io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
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// dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
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// dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
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// dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
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// dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
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// dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
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// io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
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// io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
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// io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
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// io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
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// io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
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// io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
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// io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
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//
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// //--------------------------------------------------------------------------//
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//
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// io.rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb1
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// io.rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb1, 0.U)
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// io.rv_trace_pkt.rv_i_valid_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1)
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// io.rv_trace_pkt.rv_i_exception_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1)
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// io.rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0)
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// io.rv_trace_pkt.rv_i_interrupt_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, 0.U)
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// io.rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1
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//
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//
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// // debug command read data
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// io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
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//}
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//
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//
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