risc-v-tlm/.gitignore

# Prerequisites
*.d

# Compiled Object files
*.slo
*.lo
*.o
*.obj

# Precompiled Headers
*.gch
*.pch

# Compiled Dynamic libraries
*.so
*.dylib
*.dll

# Fortran module files
*.mod
*.smod

# Compiled Static libraries
*.lai
*.la
*.a
*.lib

# Executables
*.exe
*.out
*.app
*.elf
*.hex

Log.txt
helper.ods
*.swp
RISCV_TLM
Initial commit 2018-09-11 00:41:14 +08:00			`# Prerequisites`
			`*.d`

			`# Compiled Object files`
			`*.slo`
			`*.lo`
			`*.o`
			`*.obj`

			`# Precompiled Headers`
			`*.gch`
			`*.pch`

			`# Compiled Dynamic libraries`
			`*.so`
			`*.dylib`
			`*.dll`

			`# Fortran module files`
			`*.mod`
			`*.smod`

			`# Compiled Static libraries`
			`*.lai`
			`*.la`
			`*.a`
			`*.lib`

			`# Executables`
			`*.exe`
			`*.out`
			`*.app`
Lot of changes: * memory module parses 03 field and sets Program Counter (PC) to right value * almost all RV32I instructions implemented * added Trace module to mimic ARM ITM module * added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals * lot of minor changes 2018-09-20 05:44:38 +08:00			`*.elf`
			`*.hex`
initial import 2018-09-11 00:44:54 +08:00
			`Log.txt`
			`helper.ods`
minor changes 2018-09-12 19:08:48 +08:00			`*.swp`
			`RISCV_TLM`