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risc-v-tlm/asm/Memoryaccess.asm

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Added Data Memory bus. Implemented LW & SW instructions.
2018-09-17 18:21:26 +08:00
li t1, 150
li t2, 300
li t3, -250
sw t1, -4(t2)
li t1, 500
ASM examples updated
2018-09-20 05:52:48 +08:00
#lw t1, -4(t2)