350 lines
14 KiB
C
350 lines
14 KiB
C
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#ifndef _COMPLIANCE_MODEL_H
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#define _COMPLIANCE_MODEL_H
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#define TESTNUM gp
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#if XLEN == 64
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#define ALIGNMENT 3
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#else
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#define ALIGNMENT 2
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#endif
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//RV_COMPLIANCE_HALT
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#define RVMODEL_HALT \
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la t0, begin_signature; \
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la t1, end_signature; \
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fence; \
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ecall
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#define RVMODEL_BOOT \
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.align 6; \
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.weak stvec_handler; \
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.weak mtvec_handler; \
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/* reset vector */ \
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j reset_vector; \
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.align 2; \
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trap_vector: \
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/* test whether the test came from pass/fail */ \
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csrr t5, mcause; \
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li t6, CAUSE_USER_ECALL; \
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beq t5, t6, write_tohost; \
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li t6, CAUSE_SUPERVISOR_ECALL; \
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beq t5, t6, write_tohost; \
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li t6, CAUSE_MACHINE_ECALL; \
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beq t5, t6, write_tohost; \
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/* if an mtvec_handler is defined, jump to it */ \
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la t5, mtvec_handler; \
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beqz t5, 1f; \
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jr t5; \
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/* was it an interrupt or an exception? */ \
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1: csrr t5, mcause; \
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bgez t5, handle_exception; \
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handle_exception: \
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/* we don't know how to handle whatever the exception was */ \
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other_exception: \
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/* some unhandlable exception occurred */ \
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1: ori gp, gp, 1337; \
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write_tohost: \
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sw gp, tohost, t5; \
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j write_tohost; \
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reset_vector: \
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li a0, MSTATUS_MPP; \
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csrs mstatus, a0; \
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la t0, trap_vector; \
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csrw mtvec, t0; \
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la t0, rvtest_init; \
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csrw mepc, t0; \
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csrr a0, mhartid; \
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mret; \
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1: \
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//RV_COMPLIANCE_DATA_BEGIN
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#define RVMODEL_DATA_BEGIN \
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.align 4; .global begin_signature; begin_signature:
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//RV_COMPLIANCE_DATA_END
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#define RVMODEL_DATA_END \
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.align 4; .global end_signature; end_signature: \
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.pushsection .tohost,"aw",@progbits; \
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.align 8; .global tohost; tohost: .dword 0; \
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.align 8; .global fromhost; fromhost: .dword 0; \
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.popsection; \
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.align 8; .global begin_regstate; begin_regstate: \
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.word 128; \
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.align 8; .global end_regstate; end_regstate: \
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.word 4; \
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.align ALIGNMENT;\
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#define RVMODEL_IO_INIT
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#define RVMODEL_SET_MSW_INT
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#define RVMODEL_CLEAR_MSW_INT
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#define RVMODEL_CLEAR_MTIMER_INT
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#define RVMODEL_CLEAR_MEXT_INT
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#endif // _COMPLIANCE_MODEL_H
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// RISC-V Compliance IO Test Header File
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/*
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* Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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//
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// In general the following registers are reserved
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// ra, a0, t0, t1
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// x1, x10 x5, x6
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// new reserve x31
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//
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#ifndef _COMPLIANCE_IO_H
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#define _COMPLIANCE_IO_H
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#ifndef RVMODEL_ASSERT
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# define RVMODEL_IO_QUIET
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#endif
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//-----------------------------------------------------------------------
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// RV IO Macros (Character transfer by custom instruction)
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//-----------------------------------------------------------------------
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#define STRINGIFY(x) #x
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#define TOSTRING(x) STRINGIFY(x)
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#define RVTEST_CUSTOM1 0x40000000
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#ifdef RVMODEL_IO_QUIET
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#define RVMODEL_IO_INIT
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#define RVMODEL_IO_WRITE_STR(_SP, _STR)
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#define RVMODEL_IO_CHECK()
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#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
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#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
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#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
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#else
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#define RVMODEL_IO_INIT
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#if (__riscv_xlen==32)
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# define RSIZE 4
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# define SX sw
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# define LX lw
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#endif
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#if (__riscv_xlen==64)
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# define RSIZE 8
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# define SX sd
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# define LX ld
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#endif
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// _SP = (volatile register)
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#define LOCAL_IO_PUSH(_SP) \
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la _SP, begin_regstate; \
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SX x1, (1*RSIZE)(_SP); \
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SX x5, (5*RSIZE)(_SP); \
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SX x6, (6*RSIZE)(_SP); \
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SX x8, (8*RSIZE)(_SP); \
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SX x10, (10*RSIZE)(_SP);
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// _SP = (volatile register)
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#define LOCAL_IO_POP(_SP) \
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la _SP, begin_regstate; \
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LX x1, (1*RSIZE)(_SP); \
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LX x5, (5*RSIZE)(_SP); \
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LX x6, (6*RSIZE)(_SP); \
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LX x8, (8*RSIZE)(_SP); \
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LX x10, (10*RSIZE)(_SP);
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#define LOCAL_IO_WRITE_GPR(_R) \
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mv a0, _R; \
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la t0, FN_WriteA0; \
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jalr t0;
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#define LOCAL_IO_WRITE_FPR(_F) \
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fmv.x.s a0, _F; \
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jal FN_WriteA0;
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#define LOCAL_IO_WRITE_DFPR(_V1, _V2) \
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mv a0, _V1; \
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jal FN_WriteA0; \
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mv a0, _V2; \
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jal FN_WriteA0; \
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#define LOCAL_IO_PUTC(_R) \
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la t3, RVTEST_CUSTOM1; \
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sw _R, (0)(t3);
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// Assertion violation: file file.c, line 1234: (expr)
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// _SP = (volatile register)
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// _R = GPR
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// _I = Immediate
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#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I) \
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LOCAL_IO_PUSH(_SP) \
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mv s0, _R; \
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li t0, _I; \
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beq s0, t0, 20002f; \
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LOCAL_IO_WRITE_STR("Assertion violation: file "); \
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LOCAL_IO_WRITE_STR(__FILE__); \
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LOCAL_IO_WRITE_STR(", line "); \
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LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \
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LOCAL_IO_WRITE_STR(": "); \
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LOCAL_IO_WRITE_STR(# _R); \
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LOCAL_IO_WRITE_STR("("); \
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LOCAL_IO_WRITE_GPR(s0); \
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LOCAL_IO_WRITE_STR(") != "); \
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LOCAL_IO_WRITE_STR(# _I); \
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LOCAL_IO_WRITE_STR("\n"); \
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li TESTNUM, 100; \
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j rvtest_code_end; \
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20002: \
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LOCAL_IO_POP(_SP)
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// _F = FPR
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// _C = GPR
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// _I = Immediate
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#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _C, _I) \
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fmv.x.s t0, _F; \
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beq _C, t0, 20003f; \
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LOCAL_IO_WRITE_STR("Assertion violation: file "); \
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LOCAL_IO_WRITE_STR(__FILE__); \
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LOCAL_IO_WRITE_STR(", line "); \
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LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \
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LOCAL_IO_WRITE_STR(": "); \
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LOCAL_IO_WRITE_STR(# _F); \
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LOCAL_IO_WRITE_STR("("); \
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LOCAL_IO_WRITE_FPR(_F); \
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LOCAL_IO_WRITE_STR(") != "); \
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LOCAL_IO_WRITE_STR(# _I); \
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LOCAL_IO_WRITE_STR("\n"); \
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li TESTNUM, 100; \
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j rvtest_code_end; \
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20003:
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// _D = DFPR
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// _R = GPR
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// _I = Immediate
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#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) \
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fmv.x.d t0, _D; \
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beq _R, t0, 20005f; \
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LOCAL_IO_WRITE_STR("Assertion violation: file "); \
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LOCAL_IO_WRITE_STR(__FILE__); \
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LOCAL_IO_WRITE_STR(", line "); \
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LOCAL_IO_WRITE_STR(TOSTRING(__LINE__)); \
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LOCAL_IO_WRITE_STR(": "); \
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LOCAL_IO_WRITE_STR(# _D); \
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LOCAL_IO_WRITE_STR("("); \
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LOCAL_IO_WRITE_DFPR(_D); \
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LOCAL_IO_WRITE_STR(") != "); \
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LOCAL_IO_WRITE_STR(# _I); \
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LOCAL_IO_WRITE_STR("\n"); \
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li TESTNUM, 100; \
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j rvtest_code_end; \
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20005:
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// _SP = (volatile register)
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#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
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#define RVMODEL_IO_WRITE_STR(_SP, _STR) \
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LOCAL_IO_PUSH(_SP) \
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.section .data.string; \
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20001: \
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.string _STR; \
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.section .text.init; \
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la a0, 20001b; \
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la t0, FN_WriteStr; \
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jalr t0; \
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LOCAL_IO_POP(_SP)
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// generate assertion listing
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#define LOCAL_CHECK() RVMODEL_IO_CHECK()
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#define RVMODEL_IO_CHECK() \
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li zero, -1; \
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//
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// FN_WriteStr: Uses a0, t0
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//
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FN_WriteStr:
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mv t0, a0;
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10000:
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lbu a0, (t0);
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addi t0, t0, 1;
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beq a0, zero, 10000f;
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LOCAL_IO_PUTC(a0);
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j 10000b;
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10000:
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ret;
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//
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// FN_WriteA0: write register a0(x10) (destroys a0(x10), t0-t2(x5-x7))
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//
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FN_WriteA0:
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mv t0, a0
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// determine architectural register width
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li a0, -1
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srli a0, a0, 31
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srli a0, a0, 1
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bnez a0, FN_WriteA0_64
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FN_WriteA0_32:
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// reverse register when xlen is 32
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li t1, 8
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10000: slli t2, t2, 4
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andi a0, t0, 0xf
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srli t0, t0, 4
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or t2, t2, a0
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addi t1, t1, -1
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bnez t1, 10000b
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li t1, 8
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j FN_WriteA0_common
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FN_WriteA0_64:
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// reverse register when xlen is 64
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li t1, 16
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10000: slli t2, t2, 4
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andi a0, t0, 0xf
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srli t0, t0, 4
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or t2, t2, a0
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addi t1, t1, -1
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bnez t1, 10000b
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li t1, 16
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FN_WriteA0_common:
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// write reversed characters
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li t0, 10
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10000: andi a0, t2, 0xf
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blt a0, t0, 10001f
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addi a0, a0, 'a'-10
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j 10002f
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10001: addi a0, a0, '0'
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10002: LOCAL_IO_PUTC(a0)
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srli t2, t2, 4
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addi t1, t1, -1
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bnez t1, 10000b
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ret
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#endif // RVMODEL_IO_QUIET
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#endif // _COMPLIANCE_IO_H
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