risc-v-tlm/src/Simulator.cpp

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/*!
\file Simulator.cpp
\brief Top level simulation entity
\author Màrius Montón
\date September 2018
*/
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#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "systemc"
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include <signal.h>
#include "CPU.h"
#include "Memory.h"
#include "BusCtrl.h"
#include "Trace.h"
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using namespace sc_core;
using namespace sc_dt;
using namespace std;
string filename;
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/**
* @class Simulator
* This class instiates all necessary modules, connects its ports and starts
* the simulation.
*
* @brief Top simulation entity
*/
SC_MODULE(Simulator)
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{
CPU *cpu;
Memory *MainMemory;
BusCtrl* Bus;
Trace *trace;
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uint32_t start_PC;
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sc_signal<bool> IRQ;
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SC_CTOR(Simulator)
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{
MainMemory = new Memory("Main_Memory", filename);
start_PC = MainMemory->getPCfromHEX();
cpu = new CPU("cpu", start_PC);
Bus = new BusCtrl("BusCtrl");
trace = new Trace("Trace");
cpu->instr_bus.bind(Bus->cpu_instr_socket);
cpu->exec->data_bus.bind(Bus->cpu_data_socket);
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Bus->memory_socket.bind(MainMemory->socket);
Bus->trace_socket.bind(trace->socket);
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//cpu->interrupt.bind(IRQ);
}
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~Simulator() {
cout << "Simulator destructor" << endl;
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delete cpu;
delete MainMemory;
delete Bus;
delete trace;
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}
};
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Simulator *top;
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void intHandler(int dummy) {
delete top;
//sc_stop();
exit(-1);
}
int sc_main(int argc, char* argv[])
{
signal(SIGINT, intHandler);
if (argv[1] == nullptr) {
cerr << "Filename needed for hex memory" << endl;
return -1;
}
filename = argv[1];
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top = new Simulator("top");
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sc_start();
return 0;
}