colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

* Instruction: changed name to accessors 

* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
This commit is contained in:
mariusmonton 2018-10-10 12:08:53 +02:00
parent 557e3c1ba4
commit 08044ac626
5 changed files with 374 additions and 348 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
inc/CPU.h
View File

@ -47,6 +47,15 @@ private:
Performance *perf; Performance *perf;
Log *log; Log *log;
/**
* @brief Executes default ISA instruction
* @param inst instruction to execute
* @return true if PC is affected by instruction
*/
bool process_default_instruction(Instruction &inst);
void CPU_thread(void); void CPU_thread(void);
}; };

28
inc/Instruction.h
View File

@ -128,7 +128,7 @@ public:
* @brief Constructor * @brief Constructor
* @param instr Instruction to decode * @param instr Instruction to decode
*/ */
Instruction(sc_int<32> instr); Instruction(sc_uint<32> instr);
/** /**
* @brief Access to opcode field * @brief Access to opcode field
@ -143,7 +143,7 @@ public:
* @brief Access to rd field * @brief Access to rd field
* @return rd field * @return rd field
*/ */
inline int32_t rd() { inline int32_t get_rd() {
return m_instr.range(11, 7); return m_instr.range(11, 7);
} }
@ -151,7 +151,7 @@ public:
* @brief Access to funct3 field * @brief Access to funct3 field
* @return funct3 field * @return funct3 field
*/ */
inline int32_t funct3() { inline int32_t get_funct3() {
return m_instr.range(14, 12); return m_instr.range(14, 12);
} }
@ -159,7 +159,7 @@ public:
* @brief Access to rs1 field * @brief Access to rs1 field
* @return rs1 field * @return rs1 field
*/ */
inline int32_t rs1() { inline int32_t get_rs1() {
return m_instr.range(19, 15); return m_instr.range(19, 15);
} }
@ -167,7 +167,7 @@ public:
* @brief Access to rs2 field * @brief Access to rs2 field
* @return rs2 field * @return rs2 field
*/ */
inline int32_t rs2() { inline int32_t get_rs2() {
return m_instr.range(24, 20); return m_instr.range(24, 20);
} }
@ -175,7 +175,7 @@ public:
* @brief Access to funct7 field * @brief Access to funct7 field
* @return funct7 field * @return funct7 field
*/ */
inline int32_t funct7() { inline int32_t get_funct7() {
return m_instr.range(31, 25); return m_instr.range(31, 25);
} }
@ -183,7 +183,7 @@ public:
* @brief Access to immediate field for I-type * @brief Access to immediate field for I-type
* @return immediate_I field * @return immediate_I field
*/ */
inline int32_t imm_I() { inline int32_t get_imm_I() {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(31, 20); aux = m_instr.range(31, 20);
@ -200,7 +200,7 @@ public:
* @brief Access to immediate field for S-type * @brief Access to immediate field for S-type
* @return immediate_S field * @return immediate_S field
*/ */
inline int32_t imm_S() { inline int32_t get_imm_S() {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(31, 25) << 5; aux = m_instr.range(31, 25) << 5;
@ -217,7 +217,7 @@ public:
* @brief Access to immediate field for U-type * @brief Access to immediate field for U-type
* @return immediate_U field * @return immediate_U field
*/ */
inline int32_t imm_U() { inline int32_t get_imm_U() {
return m_instr.range(31, 12); return m_instr.range(31, 12);
} }
@ -225,7 +225,7 @@ public:
* @brief Access to immediate field for B-type * @brief Access to immediate field for B-type
* @return immediate_B field * @return immediate_B field
*/ */
inline int32_t imm_B() { inline int32_t get_imm_B() {
int32_t aux = 0; int32_t aux = 0;
aux |= m_instr[7] << 11; aux |= m_instr[7] << 11;
@ -244,7 +244,7 @@ public:
* @brief Access to immediate field for J-type * @brief Access to immediate field for J-type
* @return immediate_J field * @return immediate_J field
*/ */
inline int32_t imm_J() { inline int32_t get_imm_J() {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr[31] << 20; aux = m_instr[31] << 20;
@ -259,8 +259,8 @@ public:
return aux; return aux;
} }
inline int32_t csr() { inline int32_t get_csr() {
return imm_I(); return get_imm_I();
} }
/** /**
@ -273,7 +273,7 @@ public:
cout << hex << "0x" << m_instr << dec << endl; cout << hex << "0x" << m_instr << dec << endl;
} }
private: private:
sc_int<32> m_instr; sc_uint<32> m_instr;
}; };
#endif #endif

295
src/CPU.cpp
View File

@ -22,6 +22,147 @@ CPU::~CPU() {
cout << "*********************************************" << endl; cout << "*********************************************" << endl;
} }
bool CPU::process_default_instruction(Instruction &inst) {
bool PC_not_affected = true;
switch(inst.decode()) {
case OP_LUI:
exec->LUI(inst);
break;
case OP_AUIPC:
exec->AUIPC(inst);
break;
case OP_JAL:
exec->JAL(inst);
PC_not_affected = false;
break;
case OP_JALR:
exec->JALR(inst);
PC_not_affected = false;
break;
case OP_BEQ:
exec->BEQ(inst);
PC_not_affected = false;
break;
case OP_BNE:
exec->BNE(inst);
PC_not_affected = false;
break;
case OP_BLT:
exec->BLT(inst);
PC_not_affected = false;
break;
case OP_BGE:
exec->BGE(inst);
PC_not_affected = false;
break;
case OP_BLTU:
exec->BLTU(inst);
PC_not_affected = false;
break;
case OP_BGEU:
exec->BGEU(inst);
PC_not_affected = false;
break;
case OP_LB:
exec->LB(inst);
break;
case OP_LH:
exec->LB(inst);
break;
case OP_LW:
exec->LW(inst);
break;
case OP_LBU:
exec->LBU(inst);
break;
case OP_LHU:
exec->LHU(inst);
break;
case OP_SB:
exec->SB(inst);
break;
case OP_SH:
exec->SH(inst);
break;
case OP_SW:
exec->SW(inst);
break;
case OP_ADDI:
exec->ADDI(inst);
break;
case OP_SLTI:
exec->SLTI(inst);
break;
case OP_SLTIU:
exec->SLTIU(inst);
break;
case OP_XORI:
exec->XORI(inst);
break;
case OP_ORI:
exec->ORI(inst);
break;
case OP_ANDI:
exec->ANDI(inst);
break;
case OP_SLLI:
exec->SLLI(inst);
break;
case OP_SRLI:
exec->SRLI(inst);
break;
case OP_SRAI:
exec->SRAI(inst);
break;
case OP_ADD:
exec->ADD(inst);
break;
case OP_SUB:
exec->SUB(inst);
break;
case OP_SLL:
exec->SLL(inst);
break;
case OP_SLT:
exec->SLT(inst);
break;
case OP_SLTU:
exec->SLTU(inst);
break;
case OP_XOR:
exec->XOR(inst);
break;
case OP_SRL:
exec->SRL(inst);
break;
case OP_SRA:
exec->SRA(inst);
break;
case OP_OR:
exec->OR(inst);
break;
case OP_AND:
exec->AND(inst);
break;
#if 0
case OP_CSRRW:
exec->CSRRW(inst);
break;
case OP_CSRRS:
exec->CSRRS(inst);
break;
case OP_CSRRC:
exec->CSRRC(inst);
break;
#endif
default:
break;
}
return PC_not_affected;
}
/** /**
* main thread for CPU simulation * main thread for CPU simulation
* @brief CPU mai thread * @brief CPU mai thread
@ -29,9 +170,9 @@ CPU::~CPU() {
void CPU::CPU_thread(void) { void CPU::CPU_thread(void) {
tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
int32_t INSTR; uint32_t INSTR;
sc_time delay = SC_ZERO_TIME; sc_time delay = SC_ZERO_TIME;
bool PC_not_affected = true; bool PC_not_affected;
trans->set_command( tlm::TLM_READ_COMMAND ); trans->set_command( tlm::TLM_READ_COMMAND );
trans->set_data_ptr( reinterpret_cast<unsigned char*>(&INSTR) ); trans->set_data_ptr( reinterpret_cast<unsigned char*>(&INSTR) );
@ -55,150 +196,26 @@ void CPU::CPU_thread(void) {
} else { } else {
log->SC_log(Log::INFO) << "PC: " << hex << register_bank->getPC() log->SC_log(Log::INFO) << "PC: " << hex << register_bank->getPC()
<< dec << endl; << dec << endl;
Instruction inst(INSTR); Instruction inst(INSTR);
PC_not_affected = true; /* check what type of instruction is and execute it */
switch(inst.decode()) {
case OP_LUI:
exec->LUI(inst);
break; PC_not_affected = process_default_instruction(inst);
case OP_AUIPC:
exec->AUIPC(inst);
break; // default:
case OP_JAL: // cout << endl << "Instruction not implemented: ";
exec->JAL(inst); // inst.dump();
PC_not_affected = false; // exec->NOP(inst);
break;
case OP_JALR:
exec->JALR(inst);
PC_not_affected = false;
break;
case OP_BEQ:
exec->BEQ(inst);
PC_not_affected = false;
break;
case OP_BNE:
exec->BNE(inst);
PC_not_affected = false;
break;
case OP_BLT:
exec->BLT(inst);
PC_not_affected = false;
break;
case OP_BGE:
exec->BGE(inst);
PC_not_affected = false;
break;
case OP_BLTU:
exec->BLTU(inst);
PC_not_affected = false;
break;
case OP_BGEU:
exec->BGEU(inst);
PC_not_affected = false;
break;
case OP_LB:
exec->LB(inst);
break;
case OP_LH:
exec->LB(inst);
break;
case OP_LW:
exec->LW(inst);
break;
case OP_LBU:
exec->LBU(inst);
break;
case OP_LHU:
exec->LHU(inst);
break;
case OP_SB:
exec->SB(inst);
break;
case OP_SH:
exec->SH(inst);
break;
case OP_SW:
exec->SW(inst);
break;
case OP_ADDI:
exec->ADDI(inst);
break;
case OP_SLTI:
exec->SLTI(inst);
break;
case OP_SLTIU:
exec->SLTIU(inst);
break;
case OP_XORI:
exec->XORI(inst);
break;
case OP_ORI:
exec->ORI(inst);
break;
case OP_ANDI:
exec->ANDI(inst);
break;
case OP_SLLI:
exec->SLLI(inst);
break;
case OP_SRLI:
exec->SRLI(inst);
break;
case OP_SRAI:
exec->SRAI(inst);
break;
case OP_ADD:
exec->ADD(inst);
break;
case OP_SUB:
exec->SUB(inst);
break;
case OP_SLL:
exec->SLL(inst);
break;
case OP_SLT:
exec->SLT(inst);
break;
case OP_SLTU:
exec->SLTU(inst);
break;
case OP_XOR:
exec->XOR(inst);
break;
case OP_SRL:
exec->SRL(inst);
break;
case OP_SRA:
exec->SRA(inst);
break;
case OP_OR:
exec->OR(inst);
break;
case OP_AND:
exec->AND(inst);
break;
#if 0
case OP_CSRRW:
exec->CSRRW(inst);
break;
case OP_CSRRS:
exec->CSRRS(inst);
break;
case OP_CSRRC:
exec->CSRRC(inst);
break;
#endif
default:
cout << endl << "Instruction not implemented: ";
inst.dump();
exec->NOP(inst);
} }
perf->instructionsInc(); perf->instructionsInc();
if (PC_not_affected == true) { if (PC_not_affected == true) {
register_bank->incPC(); register_bank->incPC();
} }
}
} // while(1) } // while(1)
} // CPU_thread } // CPU_thread

372
src/Execute.cpp
View File

@ -14,10 +14,10 @@ void Execute::LUI(Instruction &inst) {
int rd; int rd;
uint32_t imm = 0; uint32_t imm = 0;
rd = inst.rd(); rd = inst.get_rd();
imm = inst.imm_U() << 12; imm = inst.get_imm_U() << 12;
regs->setValue(rd, imm); regs->setValue(rd, imm);
log->SC_log(Log::INFO) << "LUI R" << rd << " <- 0x" << hex << imm << endl; log->SC_log(Log::INFO) << "LUI x" << rd << " <- 0x" << hex << imm << endl;
} }
@ -26,14 +26,14 @@ void Execute::AUIPC(Instruction &inst) {
uint32_t imm = 0; uint32_t imm = 0;
int new_pc; int new_pc;
rd = inst.rd(); rd = inst.get_rd();
imm = inst.imm_U() << 12; imm = inst.get_imm_U() << 12;
new_pc = regs->getPC() + imm; new_pc = regs->getPC() + imm;
regs->setPC(new_pc); regs->setPC(new_pc);
regs->setValue(rd, new_pc); regs->setValue(rd, new_pc);
log->SC_log(Log::INFO) << "AUIPC R" << rd << " + PC -> PC (" << new_pc << ")" << endl; log->SC_log(Log::INFO) << "AUIPC x" << rd << " + PC -> PC (" << new_pc << ")" << endl;
} }
void Execute::JAL(Instruction &inst) { void Execute::JAL(Instruction &inst) {
@ -41,8 +41,8 @@ void Execute::JAL(Instruction &inst) {
int rd; int rd;
int new_pc, old_pc; int new_pc, old_pc;
rd = inst.rd(); rd = inst.get_rd();
mem_addr = inst.imm_J(); mem_addr = inst.get_imm_J();
old_pc = regs->getPC(); old_pc = regs->getPC();
@ -53,7 +53,7 @@ void Execute::JAL(Instruction &inst) {
old_pc = old_pc + 4; old_pc = old_pc + 4;
regs->setValue(rd, old_pc); regs->setValue(rd, old_pc);
log->SC_log(Log::INFO) << dec << "JAL: R" << rd << " <- 0x" << hex << old_pc log->SC_log(Log::INFO) << dec << "JAL: x" << rd << " <- 0x" << hex << old_pc
<< dec << " PC + " << mem_addr << " -> PC (0x" << dec << " PC + " << mem_addr << " -> PC (0x"
<< hex << new_pc << ")" << endl; << hex << new_pc << ")" << endl;
} }
@ -63,9 +63,9 @@ void Execute::JALR(Instruction &inst) {
int rd, rs1; int rd, rs1;
int new_pc, old_pc; int new_pc, old_pc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
mem_addr = inst.imm_I(); mem_addr = inst.get_imm_I();
old_pc = regs->getPC(); old_pc = regs->getPC();
regs->setValue(rd, old_pc + 4); regs->setValue(rd, old_pc + 4);
@ -74,7 +74,7 @@ void Execute::JALR(Instruction &inst) {
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE; new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
regs->setPC(new_pc); regs->setPC(new_pc);
log->SC_log(Log::INFO) << "JALR: R" << dec << rd << " <- 0x" << hex << old_pc + 4 log->SC_log(Log::INFO) << "JALR: x" << dec << rd << " <- 0x" << hex << old_pc + 4
<< " PC <- 0x" << hex << new_pc << endl; << " PC <- 0x" << hex << new_pc << endl;
} }
@ -82,17 +82,17 @@ void Execute::BEQ(Instruction &inst) {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
if (regs->getValue(rs1) == regs->getValue(rs2)) { if (regs->getValue(rs1) == regs->getValue(rs2)) {
new_pc = regs->getPC() + inst.imm_B(); new_pc = regs->getPC() + inst.get_imm_B();
regs->setPC(new_pc); regs->setPC(new_pc);
} else { } else {
regs->incPC(); regs->incPC();
} }
log->SC_log(Log::INFO) << "BEQ R" << rs1 << " == R" << rs2 << "? -> PC (" << new_pc << ")" << endl; log->SC_log(Log::INFO) << "BEQ x" << rs1 << " == x" << rs2 << "? -> PC (" << new_pc << ")" << endl;
} }
@ -101,21 +101,21 @@ void Execute::BNE(Instruction &inst) {
int new_pc = 0; int new_pc = 0;
uint32_t val1, val2; uint32_t val1, val2;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
val1 = regs->getValue(rs1); val1 = regs->getValue(rs1);
val2 = regs->getValue(rs2); val2 = regs->getValue(rs2);
if (val1 != val2) { if (val1 != val2) {
new_pc = regs->getPC() + inst.imm_B(); new_pc = regs->getPC() + inst.get_imm_B();
regs->setPC(new_pc); regs->setPC(new_pc);
} else { } else {
regs->incPC(); regs->incPC();
} }
log->SC_log(Log::INFO) << "BNE: R" << rs1 << "(" << val1 log->SC_log(Log::INFO) << "BNE: x" << rs1 << "(" << val1
<< ") == R" << rs2 << "(" << val2 << ")? -> PC (" << ") == x" << rs2 << "(" << val2 << ")? -> PC ("
<< new_pc << ")" << endl; << new_pc << ")" << endl;
} }
@ -123,35 +123,35 @@ void Execute::BLT(Instruction &inst) {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
if ((int32_t)regs->getValue(rs1) < (int32_t)regs->getValue(rs2)) { if ((int32_t)regs->getValue(rs1) < (int32_t)regs->getValue(rs2)) {
new_pc = regs->getPC() + inst.imm_B(); new_pc = regs->getPC() + inst.get_imm_B();
regs->setPC(new_pc); regs->setPC(new_pc);
} else { } else {
regs->incPC(); regs->incPC();
} }
log->SC_log(Log::INFO) << "BLT R" << rs1 << " < R" << rs2 << "? -> PC (" << new_pc << ")" << endl; log->SC_log(Log::INFO) << "BLT x" << rs1 << " < x" << rs2 << "? -> PC (" << new_pc << ")" << endl;
} }
void Execute::BGE(Instruction &inst) { void Execute::BGE(Instruction &inst) {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
if ((int32_t)regs->getValue(rs1) >= (int32_t)regs->getValue(rs2)) { if ((int32_t)regs->getValue(rs1) >= (int32_t)regs->getValue(rs2)) {
new_pc = regs->getPC() + inst.imm_B(); new_pc = regs->getPC() + inst.get_imm_B();
regs->setPC(new_pc); regs->setPC(new_pc);
} else { } else {
regs->incPC(); regs->incPC();
} }
log->SC_log(Log::INFO) << "BGE R" << rs1 << "(" << log->SC_log(Log::INFO) << "BGE x" << rs1 << "(" <<
(int32_t)regs->getValue(rs1) << ") > R" << (int32_t)regs->getValue(rs1) << ") > x" <<
rs2 << "(" << (int32_t)regs->getValue(rs2) rs2 << "(" << (int32_t)regs->getValue(rs2)
<< ")? -> PC (" << new_pc << ")" << endl; << ")? -> PC (" << new_pc << ")" << endl;
} }
@ -160,34 +160,34 @@ void Execute::BLTU(Instruction &inst) {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
if (regs->getValue(rs1) < regs->getValue(rs2)) { if (regs->getValue(rs1) < regs->getValue(rs2)) {
new_pc = regs->getPC() + inst.imm_B(); new_pc = regs->getPC() + inst.get_imm_B();
regs->setPC(new_pc); regs->setPC(new_pc);
} else { } else {
regs->incPC(); regs->incPC();
} }
log->SC_log(Log::INFO) << "BLTU R" << rs1 << " < R" << rs2 << "? -> PC (" << new_pc << ")" << endl; log->SC_log(Log::INFO) << "BLTU x" << rs1 << " < x" << rs2 << "? -> PC (" << new_pc << ")" << endl;
} }
void Execute::BGEU(Instruction &inst) { void Execute::BGEU(Instruction &inst) {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
if (regs->getValue(rs1) >= regs->getValue(rs2)) { if (regs->getValue(rs1) >= regs->getValue(rs2)) {
new_pc = regs->getPC() + inst.imm_B(); new_pc = regs->getPC() + inst.get_imm_B();
regs->setPC(new_pc); regs->setPC(new_pc);
} else { } else {
regs->incPC(); regs->incPC();
} }
log->SC_log(Log::INFO) << "BGEU R" << rs1 << " > R" << rs2 << "? -> PC (" << new_pc << ")" << endl; log->SC_log(Log::INFO) << "BGEU x" << rs1 << " > x" << rs2 << "? -> PC (" << new_pc << ")" << endl;
} }
void Execute::LB(Instruction &inst) { void Execute::LB(Instruction &inst) {
@ -196,16 +196,16 @@ void Execute::LB(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
int8_t data; int8_t data;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
mem_addr = imm + regs->getValue(rs1); mem_addr = imm + regs->getValue(rs1);
data = readDataMem(mem_addr, 1); data = readDataMem(mem_addr, 1);
regs->setValue(rd, data); regs->setValue(rd, data);
log->SC_log(Log::INFO) << "LB: R" << rs1 << " + " << imm << " (@0x" log->SC_log(Log::INFO) << "LB: x" << rs1 << " + " << imm << " (@0x"
<< hex <<mem_addr << dec << ") -> R" << rd << endl; << hex <<mem_addr << dec << ") -> x" << rd << endl;
} }
void Execute::LH(Instruction &inst) { void Execute::LH(Instruction &inst) {
@ -214,16 +214,16 @@ void Execute::LH(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
int16_t data; int16_t data;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
mem_addr = imm + regs->getValue(rs1); mem_addr = imm + regs->getValue(rs1);
data = readDataMem(mem_addr, 2); data = readDataMem(mem_addr, 2);
regs->setValue(rd, data); regs->setValue(rd, data);
log->SC_log(Log::INFO) << "LH: R" << rs1 << " + " << imm << " (@0x" log->SC_log(Log::INFO) << "LH: x" << rs1 << " + " << imm << " (@0x"
<< hex <<mem_addr << dec << ") -> R" << rd << endl; << hex <<mem_addr << dec << ") -> x" << rd << endl;
} }
void Execute::LW(Instruction &inst) { void Execute::LW(Instruction &inst) {
@ -232,16 +232,16 @@ void Execute::LW(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
uint32_t data; uint32_t data;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
mem_addr = imm + regs->getValue(rs1); mem_addr = imm + regs->getValue(rs1);
data = readDataMem(mem_addr, 4); data = readDataMem(mem_addr, 4);
regs->setValue(rd, data); regs->setValue(rd, data);
log->SC_log(Log::INFO) << "LW: R" << rs1 << " + " << imm << " (@0x" log->SC_log(Log::INFO) << "LW: x" << rs1 << " + " << imm << " (@0x"
<< hex <<mem_addr << dec << ") -> R" << rd << endl; << hex <<mem_addr << dec << ") -> x" << rd << endl;
} }
void Execute::LBU(Instruction &inst) { void Execute::LBU(Instruction &inst) {
@ -250,16 +250,16 @@ void Execute::LBU(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
uint8_t data; uint8_t data;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
mem_addr = imm + regs->getValue(rs1); mem_addr = imm + regs->getValue(rs1);
data = readDataMem(mem_addr, 1); data = readDataMem(mem_addr, 1);
regs->setValue(rd, data); regs->setValue(rd, data);
log->SC_log(Log::INFO) << "LBU: R" << rs1 << " + " << imm << " (@0x" log->SC_log(Log::INFO) << "LBU: x" << rs1 << " + " << imm << " (@0x"
<< hex <<mem_addr << dec << ") -> R" << rd << endl; << hex <<mem_addr << dec << ") -> x" << rd << endl;
} }
void Execute::LHU(Instruction &inst) { void Execute::LHU(Instruction &inst) {
@ -268,16 +268,16 @@ void Execute::LHU(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
uint16_t data; uint16_t data;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
mem_addr = imm + regs->getValue(rs1); mem_addr = imm + regs->getValue(rs1);
data = readDataMem(mem_addr, 2); data = readDataMem(mem_addr, 2);
regs->setValue(rd, data); regs->setValue(rd, data);
log->SC_log(Log::INFO) << "LHU: R" << rs1 << " + " << imm << " (@0x" log->SC_log(Log::INFO) << "LHU: x" << rs1 << " + " << imm << " (@0x"
<< hex <<mem_addr << dec << ") -> R" << rd << endl; << hex <<mem_addr << dec << ") -> x" << rd << endl;
} }
void Execute::SB(Instruction &inst) { void Execute::SB(Instruction &inst) {
@ -286,16 +286,16 @@ void Execute::SB(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
uint32_t data; uint32_t data;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
imm = inst.imm_S(); imm = inst.get_imm_S();
mem_addr = imm + regs->getValue(rs1); mem_addr = imm + regs->getValue(rs1);
data = regs->getValue(rs2); data = regs->getValue(rs2);
writeDataMem(mem_addr, data, 1); writeDataMem(mem_addr, data, 1);
log->SC_log(Log::INFO) << "SB: R" << rs2 << " -> R" << rs1 << " + " log->SC_log(Log::INFO) << "SB: x" << rs2 << " -> x" << rs1 << " + "
<< imm << " (@0x" << hex <<mem_addr << dec << ")" << endl; << imm << " (@0x" << hex <<mem_addr << dec << ")" << endl;
} }
@ -305,16 +305,16 @@ void Execute::SH(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
uint32_t data; uint32_t data;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
imm = inst.imm_S(); imm = inst.get_imm_S();
mem_addr = imm + regs->getValue(rs1); mem_addr = imm + regs->getValue(rs1);
data = regs->getValue(rs2); data = regs->getValue(rs2);
writeDataMem(mem_addr, data, 2); writeDataMem(mem_addr, data, 2);
log->SC_log(Log::INFO) << "SH: R" << rs2 << " -> R" << rs1 << " + " log->SC_log(Log::INFO) << "SH: x" << rs2 << " -> x" << rs1 << " + "
<< imm << " (@0x" << hex <<mem_addr << dec << ")" << endl; << imm << " (@0x" << hex <<mem_addr << dec << ")" << endl;
} }
@ -324,17 +324,17 @@ void Execute::SW(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
uint32_t data; uint32_t data;
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
imm = inst.imm_S(); imm = inst.get_imm_S();
mem_addr = imm + regs->getValue(rs1); mem_addr = imm + regs->getValue(rs1);
data = regs->getValue(rs2); data = regs->getValue(rs2);
writeDataMem(mem_addr, data, 4); writeDataMem(mem_addr, data, 4);
log->SC_log(Log::INFO) << "SW: R" << dec << rs2 << "(0x" << hex << data log->SC_log(Log::INFO) << "SW: x" << dec << rs2 << "(0x" << hex << data
<< ") -> R" << dec << rs1 << " + " << imm << ") -> x" << dec << rs1 << " + " << imm
<< " (@0x" << hex << mem_addr << dec << ")" << endl; << " (@0x" << hex << mem_addr << dec << ")" << endl;
} }
@ -343,32 +343,32 @@ void Execute::ADDI(Instruction &inst) {
int32_t imm = 0; int32_t imm = 0;
int32_t calc; int32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
calc = regs->getValue(rs1) + imm; calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << dec << "ADDI: R" << rs1 << " + " << imm << " -> R" << rd << endl; log->SC_log(Log::INFO) << dec << "ADDI: x" << rs1 << " + " << imm << " -> x" << rd << endl;
} }
void Execute::SLTI(Instruction &inst) { void Execute::SLTI(Instruction &inst) {
int rd, rs1; int rd, rs1;
int32_t imm; int32_t imm;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
if (regs->getValue(rs1) < imm) { if (regs->getValue(rs1) < imm) {
regs->setValue(rd, 1); regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTI: R" << rs1 << " < " << imm log->SC_log(Log::INFO) << "SLTI: x" << rs1 << " < " << imm
<< " => " << "1 -> R" << rd << endl; << " => " << "1 -> x" << rd << endl;
} else { } else {
regs->setValue(rd, 0); regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTI: R" << rs1 << " < " << imm log->SC_log(Log::INFO) << "SLTI: x" << rs1 << " < " << imm
<< " => " << "0 -> R" << rd << endl; << " => " << "0 -> x" << rd << endl;
} }
} }
@ -376,18 +376,18 @@ void Execute::SLTIU(Instruction &inst) {
int rd, rs1; int rd, rs1;
int32_t imm; int32_t imm;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
if ((uint32_t) regs->getValue(rs1) < (uint32_t)imm) { if ((uint32_t) regs->getValue(rs1) < (uint32_t)imm) {
regs->setValue(rd, 1); regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTIU: R" << rs1 << " < " << imm log->SC_log(Log::INFO) << "SLTIU: x" << rs1 << " < " << imm
<< " => " << "1 -> R" << rd << endl; << " => " << "1 -> x" << rd << endl;
} else { } else {
regs->setValue(rd, 0); regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTIU: R" << rs1 << " < " << imm log->SC_log(Log::INFO) << "SLTIU: x" << rs1 << " < " << imm
<< " => " << "0 -> R" << rd << endl; << " => " << "0 -> x" << rd << endl;
} }
} }
@ -396,15 +396,15 @@ void Execute::XORI(Instruction &inst) {
int32_t imm; int32_t imm;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
calc = regs->getValue(rs1) ^ imm; calc = regs->getValue(rs1) ^ imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "XORI: R" << rs1 << " XOR " << imm log->SC_log(Log::INFO) << "XORI: x" << rs1 << " XOR " << imm
<< "-> R" << rd << endl; << "-> x" << rd << endl;
} }
void Execute::ORI(Instruction &inst) { void Execute::ORI(Instruction &inst) {
@ -412,15 +412,15 @@ void Execute::ORI(Instruction &inst) {
int32_t imm; int32_t imm;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
calc = regs->getValue(rs1) | imm; calc = regs->getValue(rs1) | imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "ORI: R" << rs1 << " OR " << imm log->SC_log(Log::INFO) << "ORI: x" << rs1 << " OR " << imm
<< "-> R" << rd << endl; << "-> x" << rd << endl;
} }
void Execute::ANDI(Instruction &inst) { void Execute::ANDI(Instruction &inst) {
@ -428,15 +428,15 @@ void Execute::ANDI(Instruction &inst) {
int32_t imm; int32_t imm;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
imm = inst.imm_I(); imm = inst.get_imm_I();
calc = regs->getValue(rs1) & imm; calc = regs->getValue(rs1) & imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "ANDI: R" << rs1 << " AND " << imm log->SC_log(Log::INFO) << "ANDI: x" << rs1 << " AND " << imm
<< " -> R" << rd << endl; << " -> x" << rd << endl;
} }
void Execute::SLLI(Instruction &inst) { void Execute::SLLI(Instruction &inst) {
@ -444,16 +444,16 @@ void Execute::SLLI(Instruction &inst) {
uint32_t shift; uint32_t shift;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
shift = rs2 & 0x1F; shift = rs2 & 0x1F;
calc = ((uint32_t)regs->getValue(rs1)) << shift; calc = ((uint32_t)regs->getValue(rs1)) << shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "SLLI: R" << rs1 << " << " << shift << " -> R" << rd << endl; log->SC_log(Log::INFO) << "SLLI: x" << rs1 << " << " << shift << " -> x" << rd << endl;
} }
void Execute::SRLI(Instruction &inst) { void Execute::SRLI(Instruction &inst) {
@ -461,16 +461,16 @@ void Execute::SRLI(Instruction &inst) {
uint32_t shift; uint32_t shift;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
shift = rs2 & 0x1F; shift = rs2 & 0x1F;
calc = ((uint32_t)regs->getValue(rs1)) >> shift; calc = ((uint32_t)regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "SRLI: R" << rs1 << " >> " << shift << " -> R" << rd << endl; log->SC_log(Log::INFO) << "SRLI: x" << rs1 << " >> " << shift << " -> x" << rd << endl;
} }
void Execute::SRAI(Instruction &inst) { void Execute::SRAI(Instruction &inst) {
@ -478,44 +478,44 @@ void Execute::SRAI(Instruction &inst) {
uint32_t shift; uint32_t shift;
int32_t calc; int32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
shift = rs2 & 0x1F; shift = rs2 & 0x1F;
calc = regs->getValue(rs1) >> shift; calc = regs->getValue(rs1) >> shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "SRAI: R" << rs1 << " >> " << shift << " -> R" << rd << endl; log->SC_log(Log::INFO) << "SRAI: x" << rs1 << " >> " << shift << " -> x" << rd << endl;
} }
void Execute::ADD(Instruction &inst) { void Execute::ADD(Instruction &inst) {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
calc = regs->getValue(rs1) + regs->getValue(rs2); calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "ADD: R" << rs1 << " + R" << rs2 << " -> R" << rd << endl; log->SC_log(Log::INFO) << "ADD: x" << rs1 << " + x" << rs2 << " -> x" << rd << endl;
} }
void Execute::SUB(Instruction &inst) { void Execute::SUB(Instruction &inst) {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
calc = regs->getValue(rs1) - regs->getValue(rs2); calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, calc); regs->setValue(rd, calc);
/* Can insert some arbitrary execution time */ /* Can insert some arbitrary execution time */
wait(sc_time(10, SC_NS)); wait(sc_time(10, SC_NS));
log->SC_log(Log::INFO) << "SUB: R" << rs1 << " - R" << rs2 << " -> R" << rd << endl; log->SC_log(Log::INFO) << "SUB: x" << rs1 << " - x" << rs2 << " -> x" << rd << endl;
} }
void Execute::SLL(Instruction &inst) { void Execute::SLL(Instruction &inst) {
@ -523,16 +523,16 @@ void Execute::SLL(Instruction &inst) {
uint32_t shift; uint32_t shift;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
shift = regs->getValue(rs2) & 0x1F; shift = regs->getValue(rs2) & 0x1F;
calc = ((uint32_t)regs->getValue(rs1)) << shift; calc = ((uint32_t)regs->getValue(rs1)) << shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "SLL: R" << rs1 << " << " << shift << " -> R" << rd << endl; log->SC_log(Log::INFO) << "SLL: x" << rs1 << " << " << shift << " -> x" << rd << endl;
} }
@ -540,18 +540,18 @@ void Execute::SLL(Instruction &inst) {
void Execute::SLT(Instruction &inst) { void Execute::SLT(Instruction &inst) {
int rd, rs1, rs2; int rd, rs1, rs2;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
if (regs->getValue(rs1) < regs->getValue(rs2)) { if (regs->getValue(rs1) < regs->getValue(rs2)) {
regs->setValue(rd, 1); regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLT: R" << rs1 << " < R" << rs2 log->SC_log(Log::INFO) << "SLT: x" << rs1 << " < x" << rs2
<< " => " << "1 -> R" << rd << endl; << " => " << "1 -> x" << rd << endl;
} else { } else {
regs->setValue(rd, 0); regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLT: R" << rs1 << " < R" << rs2 log->SC_log(Log::INFO) << "SLT: x" << rs1 << " < x" << rs2
<< " => " << "0 -> R" << rd << endl; << " => " << "0 -> x" << rd << endl;
} }
} }
@ -559,18 +559,18 @@ void Execute::SLT(Instruction &inst) {
void Execute::SLTU(Instruction &inst) { void Execute::SLTU(Instruction &inst) {
int rd, rs1, rs2; int rd, rs1, rs2;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
if ( (uint32_t)regs->getValue(rs1) < (uint32_t)regs->getValue(rs2)) { if ( (uint32_t)regs->getValue(rs1) < (uint32_t)regs->getValue(rs2)) {
regs->setValue(rd, 1); regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTU: R" << rs1 << " < R" << rs2 log->SC_log(Log::INFO) << "SLTU: x" << rs1 << " < x" << rs2
<< " => " << "1 -> R" << rd << endl; << " => " << "1 -> x" << rd << endl;
} else { } else {
regs->setValue(rd, 0); regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTU: R" << rs1 << " < R" << rs2 log->SC_log(Log::INFO) << "SLTU: x" << rs1 << " < x" << rs2
<< " => " << "0 -> R" << rd << endl; << " => " << "0 -> x" << rd << endl;
} }
} }
@ -579,15 +579,15 @@ void Execute::XOR(Instruction &inst) {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
calc = regs->getValue(rs1) ^ regs->getValue(rs2); calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "XOR: R" << rs1 << " XOR R" << rs2 log->SC_log(Log::INFO) << "XOR: x" << rs1 << " XOR x" << rs2
<< "-> R" << rd << endl; << "-> x" << rd << endl;
} }
@ -597,16 +597,16 @@ void Execute::SRL(Instruction &inst) {
uint32_t shift; uint32_t shift;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
shift = regs->getValue(rs2) & 0x1F; shift = regs->getValue(rs2) & 0x1F;
calc = ((uint32_t)regs->getValue(rs1)) >> shift; calc = ((uint32_t)regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "SRL: R" << rs1 << " >> " << shift << " -> R" << rd << endl; log->SC_log(Log::INFO) << "SRL: x" << rs1 << " >> " << shift << " -> x" << rd << endl;
} }
void Execute::SRA(Instruction &inst) { void Execute::SRA(Instruction &inst) {
@ -614,16 +614,16 @@ void Execute::SRA(Instruction &inst) {
uint32_t shift; uint32_t shift;
int32_t calc; int32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
shift = regs->getValue(rs2) & 0x1F; shift = regs->getValue(rs2) & 0x1F;
calc = regs->getValue(rs1) >> shift; calc = regs->getValue(rs1) >> shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "SRA: R" << rs1 << " >> " << shift << " -> R" << rd << endl; log->SC_log(Log::INFO) << "SRA: x" << rs1 << " >> " << shift << " -> x" << rd << endl;
} }
@ -631,15 +631,15 @@ void Execute::OR(Instruction &inst) {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
calc = regs->getValue(rs1) | regs->getValue(rs2); calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "OR: R" << rs1 << " OR R" << rs2 log->SC_log(Log::INFO) << "OR: x" << rs1 << " OR x" << rs2
<< "-> R" << rd << endl; << "-> x" << rd << endl;
} }
@ -647,15 +647,15 @@ void Execute::AND(Instruction &inst) {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
rs2 = inst.rs2(); rs2 = inst.get_rs2();
calc = regs->getValue(rs1) & regs->getValue(rs2); calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, calc); regs->setValue(rd, calc);
log->SC_log(Log::INFO) << "AND: R" << rs1 << " AND R" << rs2 log->SC_log(Log::INFO) << "AND: x" << rs1 << " AND x" << rs2
<< "-> R" << rd << endl; << "-> x" << rd << endl;
} }
void Execute::CSRRW(Instruction &inst) { void Execute::CSRRW(Instruction &inst) {
@ -663,9 +663,9 @@ void Execute::CSRRW(Instruction &inst) {
int csr; int csr;
uint32_t aux; uint32_t aux;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
csr = inst.csr(); csr = inst.get_csr();
if (rd == 0) { if (rd == 0) {
return; return;
@ -677,8 +677,8 @@ void Execute::CSRRW(Instruction &inst) {
aux = regs->getValue(rs1); aux = regs->getValue(rs1);
regs->setCSR(csr, aux); regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRW: CSR #" << csr << " -> R" << rd log->SC_log(Log::INFO) << "CSRRW: CSR #" << csr << " -> x" << rd
<< ". R" << rs1 << "-> CSR #" << csr << endl; << ". x" << rs1 << "-> CSR #" << csr << endl;
} }
void Execute::CSRRS(Instruction &inst) { void Execute::CSRRS(Instruction &inst) {
@ -686,9 +686,9 @@ void Execute::CSRRS(Instruction &inst) {
int csr; int csr;
uint32_t bitmask, aux; uint32_t bitmask, aux;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
csr = inst.csr(); csr = inst.get_csr();
if (rd == 0) { if (rd == 0) {
return; return;
@ -702,8 +702,8 @@ void Execute::CSRRS(Instruction &inst) {
aux = aux | bitmask; aux = aux | bitmask;
regs->setCSR(csr, aux); regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRS: CSR #" << csr << " -> R" << rd log->SC_log(Log::INFO) << "CSRRS: CSR #" << csr << " -> x" << rd
<< ". R" << rs1 << " & CSR #" << csr << endl; << ". x" << rs1 << " & CSR #" << csr << endl;
} }
void Execute::CSRRC(Instruction &inst) { void Execute::CSRRC(Instruction &inst) {
@ -711,9 +711,9 @@ void Execute::CSRRC(Instruction &inst) {
int csr; int csr;
uint32_t bitmask, aux; uint32_t bitmask, aux;
rd = inst.rd(); rd = inst.get_rd();
rs1 = inst.rs1(); rs1 = inst.get_rs1();
csr = inst.csr(); csr = inst.get_csr();
if (rd == 0) { if (rd == 0) {
return; return;
@ -727,8 +727,8 @@ void Execute::CSRRC(Instruction &inst) {
aux = aux & ~bitmask; aux = aux & ~bitmask;
regs->setCSR(csr, aux); regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRC: CSR #" << csr << " -> R" << rd log->SC_log(Log::INFO) << "CSRRC: CSR #" << csr << " -> x" << rd
<< ". R" << rs1 << " & CSR #" << csr << endl; << ". x" << rs1 << " & CSR #" << csr << endl;
} }
void Execute::NOP(Instruction &inst) { void Execute::NOP(Instruction &inst) {

18
src/Instruction.cpp
View File

@ -1,7 +1,7 @@
#include "Instruction.h" #include "Instruction.h"
Instruction::Instruction(sc_int<32> instr) { Instruction::Instruction(sc_uint<32> instr) {
m_instr = instr; m_instr = instr;
} }
@ -16,7 +16,7 @@ opCodes Instruction::decode() {
case JALR: case JALR:
return OP_JALR; return OP_JALR;
case BEQ: case BEQ:
switch(funct3()) { switch(get_funct3()) {
case BEQ_F: case BEQ_F:
return OP_BEQ; return OP_BEQ;
case BNE_F: case BNE_F:
@ -32,7 +32,7 @@ opCodes Instruction::decode() {
} }
return OP_ERROR; return OP_ERROR;
case LB: case LB:
switch(funct3()) { switch(get_funct3()) {
case LB_F: case LB_F:
return OP_LB; return OP_LB;
case LH_F: case LH_F:
@ -46,7 +46,7 @@ opCodes Instruction::decode() {
} }
return OP_ERROR; return OP_ERROR;
case SB: case SB:
switch(funct3()) { switch(get_funct3()) {
case SB_F: case SB_F:
return OP_SB; return OP_SB;
case SH_F: case SH_F:
@ -56,7 +56,7 @@ opCodes Instruction::decode() {
} }
return OP_ERROR; return OP_ERROR;
case ADDI: case ADDI:
switch(funct3()) { switch(get_funct3()) {
case ADDI_F: case ADDI_F:
return OP_ADDI; return OP_ADDI;
case SLTI_F: case SLTI_F:
@ -72,7 +72,7 @@ opCodes Instruction::decode() {
case SLLI_F: case SLLI_F:
return OP_SLLI; return OP_SLLI;
case SRLI_F: case SRLI_F:
switch(funct7()) { switch(get_funct7()) {
case SRLI_F7: case SRLI_F7:
return OP_SRLI; return OP_SRLI;
case SRAI_F7: case SRAI_F7:
@ -82,9 +82,9 @@ opCodes Instruction::decode() {
} }
return OP_ERROR; return OP_ERROR;
case ADD: { case ADD: {
switch(funct3()) { switch(get_funct3()) {
case ADD_F: case ADD_F:
switch (funct7()) { switch (get_funct7()) {
case ADD_F7: case ADD_F7:
return OP_ADD; return OP_ADD;
case SUB_F7: case SUB_F7:
@ -100,7 +100,7 @@ opCodes Instruction::decode() {
case XOR_F: case XOR_F:
return OP_XOR; return OP_XOR;
case SRL_F: case SRL_F:
switch(funct7()) { switch(get_funct7()) {
case SRL_F7: case SRL_F7:
return OP_SRL; return OP_SRL;
case SRA_F7: case SRA_F7: