* Instruction: changed name to accessors
* CPU: moved huge switch case to a new function * Execute: changed to use instruction new accessors
This commit is contained in:
mariusmonton
parent
557e3c1ba4
commit
08044ac626
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@ -47,6 +47,15 @@ private:
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Performance *perf;
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Log *log;
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/**
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* @brief Executes default ISA instruction
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* @param inst instruction to execute
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* @return true if PC is affected by instruction
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*/
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bool process_default_instruction(Instruction &inst);
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void CPU_thread(void);
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};
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@ -128,7 +128,7 @@ public:
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* @brief Constructor
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* @param instr Instruction to decode
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*/
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Instruction(sc_int<32> instr);
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Instruction(sc_uint<32> instr);
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/**
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* @brief Access to opcode field
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@ -143,7 +143,7 @@ public:
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* @brief Access to rd field
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* @return rd field
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*/
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inline int32_t rd() {
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inline int32_t get_rd() {
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return m_instr.range(11, 7);
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}
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@ -151,7 +151,7 @@ public:
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* @brief Access to funct3 field
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* @return funct3 field
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*/
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inline int32_t funct3() {
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inline int32_t get_funct3() {
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return m_instr.range(14, 12);
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}
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@ -159,7 +159,7 @@ public:
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* @brief Access to rs1 field
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* @return rs1 field
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*/
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inline int32_t rs1() {
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inline int32_t get_rs1() {
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return m_instr.range(19, 15);
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}
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@ -167,7 +167,7 @@ public:
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* @brief Access to rs2 field
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* @return rs2 field
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*/
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inline int32_t rs2() {
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inline int32_t get_rs2() {
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return m_instr.range(24, 20);
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}
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@ -175,7 +175,7 @@ public:
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* @brief Access to funct7 field
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* @return funct7 field
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*/
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inline int32_t funct7() {
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inline int32_t get_funct7() {
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return m_instr.range(31, 25);
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}
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@ -183,7 +183,7 @@ public:
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* @brief Access to immediate field for I-type
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* @return immediate_I field
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*/
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inline int32_t imm_I() {
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inline int32_t get_imm_I() {
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int32_t aux = 0;
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aux = m_instr.range(31, 20);
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@ -200,7 +200,7 @@ public:
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* @brief Access to immediate field for S-type
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* @return immediate_S field
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*/
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inline int32_t imm_S() {
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inline int32_t get_imm_S() {
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int32_t aux = 0;
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aux = m_instr.range(31, 25) << 5;
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@ -217,7 +217,7 @@ public:
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* @brief Access to immediate field for U-type
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* @return immediate_U field
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*/
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inline int32_t imm_U() {
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inline int32_t get_imm_U() {
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return m_instr.range(31, 12);
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}
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@ -225,7 +225,7 @@ public:
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* @brief Access to immediate field for B-type
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* @return immediate_B field
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*/
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inline int32_t imm_B() {
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inline int32_t get_imm_B() {
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int32_t aux = 0;
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aux |= m_instr[7] << 11;
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@ -244,7 +244,7 @@ public:
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* @brief Access to immediate field for J-type
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* @return immediate_J field
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*/
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inline int32_t imm_J() {
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inline int32_t get_imm_J() {
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int32_t aux = 0;
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aux = m_instr[31] << 20;
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@ -259,8 +259,8 @@ public:
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return aux;
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}
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inline int32_t csr() {
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return imm_I();
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inline int32_t get_csr() {
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return get_imm_I();
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}
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/**
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@ -273,7 +273,7 @@ public:
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cout << hex << "0x" << m_instr << dec << endl;
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}
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private:
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sc_int<32> m_instr;
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sc_uint<32> m_instr;
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};
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#endif
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93
src/CPU.cpp
93
src/CPU.cpp
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@ -22,42 +22,9 @@ CPU::~CPU() {
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cout << "*********************************************" << endl;
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}
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/**
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* main thread for CPU simulation
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* @brief CPU mai thread
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*/
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void CPU::CPU_thread(void) {
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tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
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int32_t INSTR;
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sc_time delay = SC_ZERO_TIME;
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bool CPU::process_default_instruction(Instruction &inst) {
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bool PC_not_affected = true;
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trans->set_command( tlm::TLM_READ_COMMAND );
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trans->set_data_ptr( reinterpret_cast<unsigned char*>(&INSTR) );
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trans->set_data_length( 4 );
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trans->set_streaming_width( 4 ); // = data_length to indicate no streaming
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trans->set_byte_enable_ptr( 0 ); // 0 indicates unused
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trans->set_dmi_allowed( false ); // Mandatory initial value
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trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE );
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register_bank->dump();
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while(1) {
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/* Get new PC value */
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trans->set_address( register_bank->getPC() );
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instr_bus->b_transport( *trans, delay);
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perf->codeMemoryRead();
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if ( trans->is_response_error() ) {
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SC_REPORT_ERROR("CPU base", "Read memory");
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} else {
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log->SC_log(Log::INFO) << "PC: " << hex << register_bank->getPC()
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<< dec << endl;
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Instruction inst(INSTR);
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PC_not_affected = true;
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switch(inst.decode()) {
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case OP_LUI:
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exec->LUI(inst);
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@ -190,15 +157,65 @@ void CPU::CPU_thread(void) {
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break;
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#endif
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default:
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cout << endl << "Instruction not implemented: ";
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inst.dump();
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exec->NOP(inst);
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break;
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}
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return PC_not_affected;
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}
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/**
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* main thread for CPU simulation
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* @brief CPU mai thread
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*/
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void CPU::CPU_thread(void) {
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tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
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uint32_t INSTR;
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sc_time delay = SC_ZERO_TIME;
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bool PC_not_affected;
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trans->set_command( tlm::TLM_READ_COMMAND );
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trans->set_data_ptr( reinterpret_cast<unsigned char*>(&INSTR) );
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trans->set_data_length( 4 );
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trans->set_streaming_width( 4 ); // = data_length to indicate no streaming
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trans->set_byte_enable_ptr( 0 ); // 0 indicates unused
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trans->set_dmi_allowed( false ); // Mandatory initial value
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trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE );
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register_bank->dump();
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while(1) {
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/* Get new PC value */
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trans->set_address( register_bank->getPC() );
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instr_bus->b_transport( *trans, delay);
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perf->codeMemoryRead();
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if ( trans->is_response_error() ) {
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SC_REPORT_ERROR("CPU base", "Read memory");
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} else {
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log->SC_log(Log::INFO) << "PC: " << hex << register_bank->getPC()
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<< dec << endl;
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Instruction inst(INSTR);
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/* check what type of instruction is and execute it */
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PC_not_affected = process_default_instruction(inst);
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// default:
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// cout << endl << "Instruction not implemented: ";
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// inst.dump();
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// exec->NOP(inst);
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}
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perf->instructionsInc();
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if (PC_not_affected == true) {
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register_bank->incPC();
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}
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}
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} // while(1)
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} // CPU_thread
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372
src/Execute.cpp
372
src/Execute.cpp
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@ -14,10 +14,10 @@ void Execute::LUI(Instruction &inst) {
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int rd;
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uint32_t imm = 0;
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rd = inst.rd();
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imm = inst.imm_U() << 12;
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rd = inst.get_rd();
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imm = inst.get_imm_U() << 12;
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regs->setValue(rd, imm);
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log->SC_log(Log::INFO) << "LUI R" << rd << " <- 0x" << hex << imm << endl;
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log->SC_log(Log::INFO) << "LUI x" << rd << " <- 0x" << hex << imm << endl;
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}
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@ -26,14 +26,14 @@ void Execute::AUIPC(Instruction &inst) {
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uint32_t imm = 0;
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int new_pc;
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rd = inst.rd();
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imm = inst.imm_U() << 12;
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rd = inst.get_rd();
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imm = inst.get_imm_U() << 12;
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new_pc = regs->getPC() + imm;
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regs->setPC(new_pc);
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regs->setValue(rd, new_pc);
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log->SC_log(Log::INFO) << "AUIPC R" << rd << " + PC -> PC (" << new_pc << ")" << endl;
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log->SC_log(Log::INFO) << "AUIPC x" << rd << " + PC -> PC (" << new_pc << ")" << endl;
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}
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void Execute::JAL(Instruction &inst) {
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@ -41,8 +41,8 @@ void Execute::JAL(Instruction &inst) {
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int rd;
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int new_pc, old_pc;
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rd = inst.rd();
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mem_addr = inst.imm_J();
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rd = inst.get_rd();
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mem_addr = inst.get_imm_J();
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old_pc = regs->getPC();
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@ -53,7 +53,7 @@ void Execute::JAL(Instruction &inst) {
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old_pc = old_pc + 4;
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regs->setValue(rd, old_pc);
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log->SC_log(Log::INFO) << dec << "JAL: R" << rd << " <- 0x" << hex << old_pc
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log->SC_log(Log::INFO) << dec << "JAL: x" << rd << " <- 0x" << hex << old_pc
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<< dec << " PC + " << mem_addr << " -> PC (0x"
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<< hex << new_pc << ")" << endl;
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}
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@ -63,9 +63,9 @@ void Execute::JALR(Instruction &inst) {
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int rd, rs1;
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int new_pc, old_pc;
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rd = inst.rd();
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rs1 = inst.rs1();
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mem_addr = inst.imm_I();
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rd = inst.get_rd();
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rs1 = inst.get_rs1();
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mem_addr = inst.get_imm_I();
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old_pc = regs->getPC();
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regs->setValue(rd, old_pc + 4);
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@ -74,7 +74,7 @@ void Execute::JALR(Instruction &inst) {
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new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
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regs->setPC(new_pc);
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log->SC_log(Log::INFO) << "JALR: R" << dec << rd << " <- 0x" << hex << old_pc + 4
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log->SC_log(Log::INFO) << "JALR: x" << dec << rd << " <- 0x" << hex << old_pc + 4
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<< " PC <- 0x" << hex << new_pc << endl;
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}
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@ -82,17 +82,17 @@ void Execute::BEQ(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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rs1 = inst.rs1();
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rs2 = inst.rs2();
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rs1 = inst.get_rs1();
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rs2 = inst.get_rs2();
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if (regs->getValue(rs1) == regs->getValue(rs2)) {
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new_pc = regs->getPC() + inst.imm_B();
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new_pc = regs->getPC() + inst.get_imm_B();
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regs->setPC(new_pc);
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} else {
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regs->incPC();
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}
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log->SC_log(Log::INFO) << "BEQ R" << rs1 << " == R" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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log->SC_log(Log::INFO) << "BEQ x" << rs1 << " == x" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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}
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@ -101,21 +101,21 @@ void Execute::BNE(Instruction &inst) {
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int new_pc = 0;
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uint32_t val1, val2;
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rs1 = inst.rs1();
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rs2 = inst.rs2();
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rs1 = inst.get_rs1();
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rs2 = inst.get_rs2();
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val1 = regs->getValue(rs1);
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val2 = regs->getValue(rs2);
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if (val1 != val2) {
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new_pc = regs->getPC() + inst.imm_B();
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new_pc = regs->getPC() + inst.get_imm_B();
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regs->setPC(new_pc);
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} else {
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regs->incPC();
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}
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log->SC_log(Log::INFO) << "BNE: R" << rs1 << "(" << val1
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<< ") == R" << rs2 << "(" << val2 << ")? -> PC ("
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log->SC_log(Log::INFO) << "BNE: x" << rs1 << "(" << val1
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<< ") == x" << rs2 << "(" << val2 << ")? -> PC ("
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<< new_pc << ")" << endl;
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}
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@ -123,35 +123,35 @@ void Execute::BLT(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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rs1 = inst.rs1();
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rs2 = inst.rs2();
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rs1 = inst.get_rs1();
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rs2 = inst.get_rs2();
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if ((int32_t)regs->getValue(rs1) < (int32_t)regs->getValue(rs2)) {
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new_pc = regs->getPC() + inst.imm_B();
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new_pc = regs->getPC() + inst.get_imm_B();
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regs->setPC(new_pc);
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} else {
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regs->incPC();
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}
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log->SC_log(Log::INFO) << "BLT R" << rs1 << " < R" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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log->SC_log(Log::INFO) << "BLT x" << rs1 << " < x" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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}
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void Execute::BGE(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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rs1 = inst.rs1();
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rs2 = inst.rs2();
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rs1 = inst.get_rs1();
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rs2 = inst.get_rs2();
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if ((int32_t)regs->getValue(rs1) >= (int32_t)regs->getValue(rs2)) {
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new_pc = regs->getPC() + inst.imm_B();
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new_pc = regs->getPC() + inst.get_imm_B();
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regs->setPC(new_pc);
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} else {
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regs->incPC();
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}
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log->SC_log(Log::INFO) << "BGE R" << rs1 << "(" <<
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(int32_t)regs->getValue(rs1) << ") > R" <<
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log->SC_log(Log::INFO) << "BGE x" << rs1 << "(" <<
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(int32_t)regs->getValue(rs1) << ") > x" <<
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rs2 << "(" << (int32_t)regs->getValue(rs2)
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<< ")? -> PC (" << new_pc << ")" << endl;
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}
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@ -160,34 +160,34 @@ void Execute::BLTU(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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rs1 = inst.rs1();
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rs2 = inst.rs2();
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rs1 = inst.get_rs1();
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rs2 = inst.get_rs2();
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if (regs->getValue(rs1) < regs->getValue(rs2)) {
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new_pc = regs->getPC() + inst.imm_B();
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new_pc = regs->getPC() + inst.get_imm_B();
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regs->setPC(new_pc);
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} else {
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regs->incPC();
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}
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log->SC_log(Log::INFO) << "BLTU R" << rs1 << " < R" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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log->SC_log(Log::INFO) << "BLTU x" << rs1 << " < x" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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}
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void Execute::BGEU(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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rs1 = inst.rs1();
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rs2 = inst.rs2();
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rs1 = inst.get_rs1();
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rs2 = inst.get_rs2();
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if (regs->getValue(rs1) >= regs->getValue(rs2)) {
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new_pc = regs->getPC() + inst.imm_B();
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new_pc = regs->getPC() + inst.get_imm_B();
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regs->setPC(new_pc);
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} else {
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regs->incPC();
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}
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|
||||
log->SC_log(Log::INFO) << "BGEU R" << rs1 << " > R" << rs2 << "? -> PC (" << new_pc << ")" << endl;
|
||||
log->SC_log(Log::INFO) << "BGEU x" << rs1 << " > x" << rs2 << "? -> PC (" << new_pc << ")" << endl;
|
||||
}
|
||||
|
||||
void Execute::LB(Instruction &inst) {
|
||||
|
|
@ -196,16 +196,16 @@ void Execute::LB(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
int8_t data;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = readDataMem(mem_addr, 1);
|
||||
regs->setValue(rd, data);
|
||||
|
||||
log->SC_log(Log::INFO) << "LB: R" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "LB: x" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::LH(Instruction &inst) {
|
||||
|
|
@ -214,16 +214,16 @@ void Execute::LH(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
int16_t data;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = readDataMem(mem_addr, 2);
|
||||
regs->setValue(rd, data);
|
||||
|
||||
log->SC_log(Log::INFO) << "LH: R" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "LH: x" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::LW(Instruction &inst) {
|
||||
|
|
@ -232,16 +232,16 @@ void Execute::LW(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
uint32_t data;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = readDataMem(mem_addr, 4);
|
||||
regs->setValue(rd, data);
|
||||
|
||||
log->SC_log(Log::INFO) << "LW: R" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "LW: x" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::LBU(Instruction &inst) {
|
||||
|
|
@ -250,16 +250,16 @@ void Execute::LBU(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
uint8_t data;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = readDataMem(mem_addr, 1);
|
||||
regs->setValue(rd, data);
|
||||
|
||||
log->SC_log(Log::INFO) << "LBU: R" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "LBU: x" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::LHU(Instruction &inst) {
|
||||
|
|
@ -268,16 +268,16 @@ void Execute::LHU(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
uint16_t data;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = readDataMem(mem_addr, 2);
|
||||
regs->setValue(rd, data);
|
||||
|
||||
log->SC_log(Log::INFO) << "LHU: R" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "LHU: x" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::SB(Instruction &inst) {
|
||||
|
|
@ -286,16 +286,16 @@ void Execute::SB(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
uint32_t data;
|
||||
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
imm = inst.imm_S();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
imm = inst.get_imm_S();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = regs->getValue(rs2);
|
||||
|
||||
writeDataMem(mem_addr, data, 1);
|
||||
|
||||
log->SC_log(Log::INFO) << "SB: R" << rs2 << " -> R" << rs1 << " + "
|
||||
log->SC_log(Log::INFO) << "SB: x" << rs2 << " -> x" << rs1 << " + "
|
||||
<< imm << " (@0x" << hex <<mem_addr << dec << ")" << endl;
|
||||
}
|
||||
|
||||
|
|
@ -305,16 +305,16 @@ void Execute::SH(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
uint32_t data;
|
||||
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
imm = inst.imm_S();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
imm = inst.get_imm_S();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = regs->getValue(rs2);
|
||||
|
||||
writeDataMem(mem_addr, data, 2);
|
||||
|
||||
log->SC_log(Log::INFO) << "SH: R" << rs2 << " -> R" << rs1 << " + "
|
||||
log->SC_log(Log::INFO) << "SH: x" << rs2 << " -> x" << rs1 << " + "
|
||||
<< imm << " (@0x" << hex <<mem_addr << dec << ")" << endl;
|
||||
}
|
||||
|
||||
|
|
@ -324,17 +324,17 @@ void Execute::SW(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
uint32_t data;
|
||||
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
imm = inst.imm_S();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
imm = inst.get_imm_S();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = regs->getValue(rs2);
|
||||
|
||||
writeDataMem(mem_addr, data, 4);
|
||||
|
||||
log->SC_log(Log::INFO) << "SW: R" << dec << rs2 << "(0x" << hex << data
|
||||
<< ") -> R" << dec << rs1 << " + " << imm
|
||||
log->SC_log(Log::INFO) << "SW: x" << dec << rs2 << "(0x" << hex << data
|
||||
<< ") -> x" << dec << rs1 << " + " << imm
|
||||
<< " (@0x" << hex << mem_addr << dec << ")" << endl;
|
||||
}
|
||||
|
||||
|
|
@ -343,32 +343,32 @@ void Execute::ADDI(Instruction &inst) {
|
|||
int32_t imm = 0;
|
||||
int32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
calc = regs->getValue(rs1) + imm;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << dec << "ADDI: R" << rs1 << " + " << imm << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << dec << "ADDI: x" << rs1 << " + " << imm << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::SLTI(Instruction &inst) {
|
||||
int rd, rs1;
|
||||
int32_t imm;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
if (regs->getValue(rs1) < imm) {
|
||||
regs->setValue(rd, 1);
|
||||
log->SC_log(Log::INFO) << "SLTI: R" << rs1 << " < " << imm
|
||||
<< " => " << "1 -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLTI: x" << rs1 << " < " << imm
|
||||
<< " => " << "1 -> x" << rd << endl;
|
||||
} else {
|
||||
regs->setValue(rd, 0);
|
||||
log->SC_log(Log::INFO) << "SLTI: R" << rs1 << " < " << imm
|
||||
<< " => " << "0 -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLTI: x" << rs1 << " < " << imm
|
||||
<< " => " << "0 -> x" << rd << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -376,18 +376,18 @@ void Execute::SLTIU(Instruction &inst) {
|
|||
int rd, rs1;
|
||||
int32_t imm;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
if ((uint32_t) regs->getValue(rs1) < (uint32_t)imm) {
|
||||
regs->setValue(rd, 1);
|
||||
log->SC_log(Log::INFO) << "SLTIU: R" << rs1 << " < " << imm
|
||||
<< " => " << "1 -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLTIU: x" << rs1 << " < " << imm
|
||||
<< " => " << "1 -> x" << rd << endl;
|
||||
} else {
|
||||
regs->setValue(rd, 0);
|
||||
log->SC_log(Log::INFO) << "SLTIU: R" << rs1 << " < " << imm
|
||||
<< " => " << "0 -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLTIU: x" << rs1 << " < " << imm
|
||||
<< " => " << "0 -> x" << rd << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -396,15 +396,15 @@ void Execute::XORI(Instruction &inst) {
|
|||
int32_t imm;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
calc = regs->getValue(rs1) ^ imm;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "XORI: R" << rs1 << " XOR " << imm
|
||||
<< "-> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "XORI: x" << rs1 << " XOR " << imm
|
||||
<< "-> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::ORI(Instruction &inst) {
|
||||
|
|
@ -412,15 +412,15 @@ void Execute::ORI(Instruction &inst) {
|
|||
int32_t imm;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
calc = regs->getValue(rs1) | imm;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "ORI: R" << rs1 << " OR " << imm
|
||||
<< "-> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "ORI: x" << rs1 << " OR " << imm
|
||||
<< "-> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::ANDI(Instruction &inst) {
|
||||
|
|
@ -428,15 +428,15 @@ void Execute::ANDI(Instruction &inst) {
|
|||
int32_t imm;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
imm = inst.imm_I();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
imm = inst.get_imm_I();
|
||||
|
||||
calc = regs->getValue(rs1) & imm;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "ANDI: R" << rs1 << " AND " << imm
|
||||
<< " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "ANDI: x" << rs1 << " AND " << imm
|
||||
<< " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::SLLI(Instruction &inst) {
|
||||
|
|
@ -444,16 +444,16 @@ void Execute::SLLI(Instruction &inst) {
|
|||
uint32_t shift;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
shift = rs2 & 0x1F;
|
||||
|
||||
calc = ((uint32_t)regs->getValue(rs1)) << shift;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "SLLI: R" << rs1 << " << " << shift << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLLI: x" << rs1 << " << " << shift << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::SRLI(Instruction &inst) {
|
||||
|
|
@ -461,16 +461,16 @@ void Execute::SRLI(Instruction &inst) {
|
|||
uint32_t shift;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
shift = rs2 & 0x1F;
|
||||
|
||||
calc = ((uint32_t)regs->getValue(rs1)) >> shift;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "SRLI: R" << rs1 << " >> " << shift << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SRLI: x" << rs1 << " >> " << shift << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::SRAI(Instruction &inst) {
|
||||
|
|
@ -478,44 +478,44 @@ void Execute::SRAI(Instruction &inst) {
|
|||
uint32_t shift;
|
||||
int32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
shift = rs2 & 0x1F;
|
||||
|
||||
calc = regs->getValue(rs1) >> shift;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "SRAI: R" << rs1 << " >> " << shift << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SRAI: x" << rs1 << " >> " << shift << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::ADD(Instruction &inst) {
|
||||
int rd, rs1, rs2;
|
||||
uint32_t calc;
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
calc = regs->getValue(rs1) + regs->getValue(rs2);
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "ADD: R" << rs1 << " + R" << rs2 << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "ADD: x" << rs1 << " + x" << rs2 << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::SUB(Instruction &inst) {
|
||||
int rd, rs1, rs2;
|
||||
uint32_t calc;
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
calc = regs->getValue(rs1) - regs->getValue(rs2);
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
/* Can insert some arbitrary execution time */
|
||||
wait(sc_time(10, SC_NS));
|
||||
log->SC_log(Log::INFO) << "SUB: R" << rs1 << " - R" << rs2 << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SUB: x" << rs1 << " - x" << rs2 << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::SLL(Instruction &inst) {
|
||||
|
|
@ -523,16 +523,16 @@ void Execute::SLL(Instruction &inst) {
|
|||
uint32_t shift;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
shift = regs->getValue(rs2) & 0x1F;
|
||||
|
||||
calc = ((uint32_t)regs->getValue(rs1)) << shift;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "SLL: R" << rs1 << " << " << shift << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLL: x" << rs1 << " << " << shift << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -540,18 +540,18 @@ void Execute::SLL(Instruction &inst) {
|
|||
void Execute::SLT(Instruction &inst) {
|
||||
int rd, rs1, rs2;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
if (regs->getValue(rs1) < regs->getValue(rs2)) {
|
||||
regs->setValue(rd, 1);
|
||||
log->SC_log(Log::INFO) << "SLT: R" << rs1 << " < R" << rs2
|
||||
<< " => " << "1 -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLT: x" << rs1 << " < x" << rs2
|
||||
<< " => " << "1 -> x" << rd << endl;
|
||||
} else {
|
||||
regs->setValue(rd, 0);
|
||||
log->SC_log(Log::INFO) << "SLT: R" << rs1 << " < R" << rs2
|
||||
<< " => " << "0 -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLT: x" << rs1 << " < x" << rs2
|
||||
<< " => " << "0 -> x" << rd << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -559,18 +559,18 @@ void Execute::SLT(Instruction &inst) {
|
|||
void Execute::SLTU(Instruction &inst) {
|
||||
int rd, rs1, rs2;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
if ( (uint32_t)regs->getValue(rs1) < (uint32_t)regs->getValue(rs2)) {
|
||||
regs->setValue(rd, 1);
|
||||
log->SC_log(Log::INFO) << "SLTU: R" << rs1 << " < R" << rs2
|
||||
<< " => " << "1 -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLTU: x" << rs1 << " < x" << rs2
|
||||
<< " => " << "1 -> x" << rd << endl;
|
||||
} else {
|
||||
regs->setValue(rd, 0);
|
||||
log->SC_log(Log::INFO) << "SLTU: R" << rs1 << " < R" << rs2
|
||||
<< " => " << "0 -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SLTU: x" << rs1 << " < x" << rs2
|
||||
<< " => " << "0 -> x" << rd << endl;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -579,15 +579,15 @@ void Execute::XOR(Instruction &inst) {
|
|||
int rd, rs1, rs2;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "XOR: R" << rs1 << " XOR R" << rs2
|
||||
<< "-> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "XOR: x" << rs1 << " XOR x" << rs2
|
||||
<< "-> x" << rd << endl;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -597,16 +597,16 @@ void Execute::SRL(Instruction &inst) {
|
|||
uint32_t shift;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
shift = regs->getValue(rs2) & 0x1F;
|
||||
|
||||
calc = ((uint32_t)regs->getValue(rs1)) >> shift;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "SRL: R" << rs1 << " >> " << shift << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SRL: x" << rs1 << " >> " << shift << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::SRA(Instruction &inst) {
|
||||
|
|
@ -614,16 +614,16 @@ void Execute::SRA(Instruction &inst) {
|
|||
uint32_t shift;
|
||||
int32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
shift = regs->getValue(rs2) & 0x1F;
|
||||
|
||||
calc = regs->getValue(rs1) >> shift;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "SRA: R" << rs1 << " >> " << shift << " -> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "SRA: x" << rs1 << " >> " << shift << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -631,15 +631,15 @@ void Execute::OR(Instruction &inst) {
|
|||
int rd, rs1, rs2;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
calc = regs->getValue(rs1) | regs->getValue(rs2);
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "OR: R" << rs1 << " OR R" << rs2
|
||||
<< "-> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "OR: x" << rs1 << " OR x" << rs2
|
||||
<< "-> x" << rd << endl;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -647,15 +647,15 @@ void Execute::AND(Instruction &inst) {
|
|||
int rd, rs1, rs2;
|
||||
uint32_t calc;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
rs2 = inst.rs2();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
rs2 = inst.get_rs2();
|
||||
|
||||
calc = regs->getValue(rs1) & regs->getValue(rs2);
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "AND: R" << rs1 << " AND R" << rs2
|
||||
<< "-> R" << rd << endl;
|
||||
log->SC_log(Log::INFO) << "AND: x" << rs1 << " AND x" << rs2
|
||||
<< "-> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::CSRRW(Instruction &inst) {
|
||||
|
|
@ -663,9 +663,9 @@ void Execute::CSRRW(Instruction &inst) {
|
|||
int csr;
|
||||
uint32_t aux;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
csr = inst.csr();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
csr = inst.get_csr();
|
||||
|
||||
if (rd == 0) {
|
||||
return;
|
||||
|
|
@ -677,8 +677,8 @@ void Execute::CSRRW(Instruction &inst) {
|
|||
aux = regs->getValue(rs1);
|
||||
regs->setCSR(csr, aux);
|
||||
|
||||
log->SC_log(Log::INFO) << "CSRRW: CSR #" << csr << " -> R" << rd
|
||||
<< ". R" << rs1 << "-> CSR #" << csr << endl;
|
||||
log->SC_log(Log::INFO) << "CSRRW: CSR #" << csr << " -> x" << rd
|
||||
<< ". x" << rs1 << "-> CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void Execute::CSRRS(Instruction &inst) {
|
||||
|
|
@ -686,9 +686,9 @@ void Execute::CSRRS(Instruction &inst) {
|
|||
int csr;
|
||||
uint32_t bitmask, aux;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
csr = inst.csr();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
csr = inst.get_csr();
|
||||
|
||||
if (rd == 0) {
|
||||
return;
|
||||
|
|
@ -702,8 +702,8 @@ void Execute::CSRRS(Instruction &inst) {
|
|||
aux = aux | bitmask;
|
||||
regs->setCSR(csr, aux);
|
||||
|
||||
log->SC_log(Log::INFO) << "CSRRS: CSR #" << csr << " -> R" << rd
|
||||
<< ". R" << rs1 << " & CSR #" << csr << endl;
|
||||
log->SC_log(Log::INFO) << "CSRRS: CSR #" << csr << " -> x" << rd
|
||||
<< ". x" << rs1 << " & CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void Execute::CSRRC(Instruction &inst) {
|
||||
|
|
@ -711,9 +711,9 @@ void Execute::CSRRC(Instruction &inst) {
|
|||
int csr;
|
||||
uint32_t bitmask, aux;
|
||||
|
||||
rd = inst.rd();
|
||||
rs1 = inst.rs1();
|
||||
csr = inst.csr();
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
csr = inst.get_csr();
|
||||
|
||||
if (rd == 0) {
|
||||
return;
|
||||
|
|
@ -727,8 +727,8 @@ void Execute::CSRRC(Instruction &inst) {
|
|||
aux = aux & ~bitmask;
|
||||
regs->setCSR(csr, aux);
|
||||
|
||||
log->SC_log(Log::INFO) << "CSRRC: CSR #" << csr << " -> R" << rd
|
||||
<< ". R" << rs1 << " & CSR #" << csr << endl;
|
||||
log->SC_log(Log::INFO) << "CSRRC: CSR #" << csr << " -> x" << rd
|
||||
<< ". x" << rs1 << " & CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void Execute::NOP(Instruction &inst) {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#include "Instruction.h"
|
||||
|
||||
|
||||
Instruction::Instruction(sc_int<32> instr) {
|
||||
Instruction::Instruction(sc_uint<32> instr) {
|
||||
m_instr = instr;
|
||||
}
|
||||
|
||||
|
|
@ -16,7 +16,7 @@ opCodes Instruction::decode() {
|
|||
case JALR:
|
||||
return OP_JALR;
|
||||
case BEQ:
|
||||
switch(funct3()) {
|
||||
switch(get_funct3()) {
|
||||
case BEQ_F:
|
||||
return OP_BEQ;
|
||||
case BNE_F:
|
||||
|
|
@ -32,7 +32,7 @@ opCodes Instruction::decode() {
|
|||
}
|
||||
return OP_ERROR;
|
||||
case LB:
|
||||
switch(funct3()) {
|
||||
switch(get_funct3()) {
|
||||
case LB_F:
|
||||
return OP_LB;
|
||||
case LH_F:
|
||||
|
|
@ -46,7 +46,7 @@ opCodes Instruction::decode() {
|
|||
}
|
||||
return OP_ERROR;
|
||||
case SB:
|
||||
switch(funct3()) {
|
||||
switch(get_funct3()) {
|
||||
case SB_F:
|
||||
return OP_SB;
|
||||
case SH_F:
|
||||
|
|
@ -56,7 +56,7 @@ opCodes Instruction::decode() {
|
|||
}
|
||||
return OP_ERROR;
|
||||
case ADDI:
|
||||
switch(funct3()) {
|
||||
switch(get_funct3()) {
|
||||
case ADDI_F:
|
||||
return OP_ADDI;
|
||||
case SLTI_F:
|
||||
|
|
@ -72,7 +72,7 @@ opCodes Instruction::decode() {
|
|||
case SLLI_F:
|
||||
return OP_SLLI;
|
||||
case SRLI_F:
|
||||
switch(funct7()) {
|
||||
switch(get_funct7()) {
|
||||
case SRLI_F7:
|
||||
return OP_SRLI;
|
||||
case SRAI_F7:
|
||||
|
|
@ -82,9 +82,9 @@ opCodes Instruction::decode() {
|
|||
}
|
||||
return OP_ERROR;
|
||||
case ADD: {
|
||||
switch(funct3()) {
|
||||
switch(get_funct3()) {
|
||||
case ADD_F:
|
||||
switch (funct7()) {
|
||||
switch (get_funct7()) {
|
||||
case ADD_F7:
|
||||
return OP_ADD;
|
||||
case SUB_F7:
|
||||
|
|
@ -100,7 +100,7 @@ opCodes Instruction::decode() {
|
|||
case XOR_F:
|
||||
return OP_XOR;
|
||||
case SRL_F:
|
||||
switch(funct7()) {
|
||||
switch(get_funct7()) {
|
||||
case SRL_F7:
|
||||
return OP_SRL;
|
||||
case SRA_F7:
|
||||
|
|
|
|||
Loading…
Reference in New Issue