From 08d699d34ef7cb5376ca9fa194e75a49e9a482a3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?M=C3=A0rius=20Mont=C3=B3n?= <marius.monton@gmail.com>
Date: Mon, 8 Nov 2021 09:21:59 +0100
Subject: [PATCH] If write to HOST, stop simulation

---
 inc/BusCtrl.h   | 4 ++++
 src/BusCtrl.cpp | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/inc/BusCtrl.h b/inc/BusCtrl.h
index 5f06458..7391740 100644
--- a/inc/BusCtrl.h
+++ b/inc/BusCtrl.h
@@ -32,6 +32,8 @@
 #define TIMERCMP_MEMORY_ADDRESS_LO 0x40004008
 #define TIMERCMP_MEMORY_ADDRESS_HI 0x4000400C
 
+#define TO_HOST_ADDRESS 0x90000000
+
 /**
  * @brief Simple bus controller
  *
@@ -87,6 +89,8 @@ private:
 	bool instr_direct_mem_ptr(tlm::tlm_generic_payload&,
 			tlm::tlm_dmi &dmi_data);
 	void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
+
+    Log *log;
 };
 
 #endif
diff --git a/src/BusCtrl.cpp b/src/BusCtrl.cpp
index 712cfb4..e9c20a3 100644
--- a/src/BusCtrl.cpp
+++ b/src/BusCtrl.cpp
@@ -19,6 +19,7 @@ BusCtrl::BusCtrl(sc_core::sc_module_name const &name) :
 			&BusCtrl::instr_direct_mem_ptr);
 	memory_socket.register_invalidate_direct_mem_ptr(this,
 			&BusCtrl::invalidate_direct_mem_ptr);
+    log = Log::getInstance();
 }
 
 void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
@@ -26,6 +27,13 @@ void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
 
 	sc_dt::uint64 adr = trans.get_address() / 4;
 
+	if (adr >= TO_HOST_ADDRESS / 4) {
+	    std::cout << "To host\n" << std::flush;
+        log->SC_log(Log::ERROR) << std::flush;
+        sc_core::sc_stop();
+        return;
+	}
+
 	switch (adr) {
 	case TIMER_MEMORY_ADDRESS_HI / 4:
 	case TIMER_MEMORY_ADDRESS_LO / 4: