added time management and cycle counters

This commit is contained in:
mariusmonton 2018-11-25 12:07:08 +01:00
parent 81f61c52fc
commit 1b93e7f569
4 changed files with 15 additions and 2 deletions

View File

@ -41,6 +41,16 @@
#define CSR_MTVAL (0x343)
#define CSR_MIP (0x344)
#define CSR_CYCLE (0xC00)
#define CSR_TIME (0xC01)
#define CSR_INSTRET (0xC02)
#define CSR_CYCLEH (0xC80)
#define CSR_TIMEH (0xC81)
#define CSR_INSTRETH (0xC02)
/* 1 ns tick in CYCLE & TIME counters */
#define TICKS_PER_SECOND (1000000)
using namespace sc_core;
using namespace sc_dt;

View File

@ -393,6 +393,8 @@ void CPU::CPU_thread(void) {
inst.dump();
exec->NOP(inst);
} // switch (inst.check_extension())
/* Fixed instruction time to 10 ns (i.e. 100 MHz)*/
sc_core::wait(10, SC_NS);
}
perf->instructionsInc();

View File

@ -99,12 +99,10 @@ uint32_t Registers::getCSR(int csr) {
case CSR_TIME:
ret_value = (uint64_t)(sc_time(sc_time_stamp()
- sc_time(SC_ZERO_TIME)).to_double()) & 0x00000000FFFFFFFF;
cout << "TIME " << ret_value << endl;
break;
case CSR_TIMEH:
ret_value = (uint32_t)((uint64_t)(sc_time(sc_time_stamp()
- sc_time(SC_ZERO_TIME)).to_double()) >> 32 & 0x00000000FFFFFFFF);
cout << "TIMEH " << ret_value << endl;
break;
default:
ret_value = CSR[csr];

View File

@ -82,6 +82,9 @@ int sc_main(int argc, char* argv[])
signal(SIGINT, intHandler);
/* SystemC time resolution set to 1 ns*/
sc_set_time_resolution(1, SC_NS);
if (argv[1] == nullptr) {
cerr << "Filename needed for hex memory" << endl;
return -1;