From 1d271cbb0ae0b8c44c2e7caf0529299ca50c1c4b Mon Sep 17 00:00:00 2001 From: mariusmonton Date: Sun, 19 Jul 2020 11:18:58 +0200 Subject: [PATCH] explicit sc_core::wait, typos and newline --- src/A_extension.cpp | 1 + src/Memory.cpp | 2 +- src/Registers.cpp | 3 +-- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/A_extension.cpp b/src/A_extension.cpp index 595da0b..8c2e91a 100644 --- a/src/A_extension.cpp +++ b/src/A_extension.cpp @@ -235,6 +235,7 @@ bool A_extension::Exec_A_AMOOR() { log->SC_log(Log::INFO) << std::dec << "AMOOR " << std::endl; return true; } + bool A_extension::Exec_A_AMOMIN() { uint32_t mem_addr = 0; int rd, rs1, rs2; diff --git a/src/Memory.cpp b/src/Memory.cpp index cad9da0..6edf358 100644 --- a/src/Memory.cpp +++ b/src/Memory.cpp @@ -86,7 +86,7 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans, memcpy(&mem[adr], ptr, len); // Illustrates that b_transport may block - wait(delay); + sc_core::wait(delay); // Reset timing annotation after waiting delay = sc_core::SC_ZERO_TIME; diff --git a/src/Registers.cpp b/src/Registers.cpp index cc7dc09..fb08355 100644 --- a/src/Registers.cpp +++ b/src/Registers.cpp @@ -165,7 +165,7 @@ uint32_t Registers::getCSR(int csr) { void Registers::setCSR(int csr, uint32_t value) { /* @FIXME: rv32mi-p-ma_fetch tests doesn't allow MISA to writable, - * but Volume II: Privileged Architectura v1.10 says MISRA is writable (?) + * but Volume II: Privileged Architecture v1.10 says MISA is writable (?) */ if (csr != CSR_MISA) { CSR[csr] = value; @@ -176,5 +176,4 @@ void Registers::initCSR() { CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION | MISA_A_EXTENSION | MISA_I_BASE; CSR[CSR_MSTATUS] = MISA_MXL; - }