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This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2.
It supports RV32IMAC Instruction set by now.
[![travis](https://travis-ci.org/mariusmm/RISC-V-TLM.svg?branch=master)](https://travis-ci.org/mariusmm/RISC-V-TLM)
[![travis](https://api.travis-ci.com/mariusmm/RISC-V-TLM.svg?branch=master](https://travis-ci.org/mariusmm/RISC-V-TLM)
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