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added const keyword to const methods

This commit is contained in:
mariusmonton 2021-01-17 15:40:47 +01:00
parent a019de5eb3
commit 286dbf07a6
10 changed files with 199 additions and 194 deletions
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32
inc/A_extension.h
View File

@ -63,7 +63,7 @@ public:
* @brief Access to opcode field * @brief Access to opcode field
* @return return opcode field * @return return opcode field
*/ */
inline int32_t opcode() { inline int32_t opcode() const {
return m_instr.range(31, 27); return m_instr.range(31, 27);
} }
@ -71,7 +71,7 @@ public:
* @brief Access to rd field * @brief Access to rd field
* @return rd field * @return rd field
*/ */
inline int32_t get_rd() { inline int32_t get_rd() const {
return m_instr.range(11, 7); return m_instr.range(11, 7);
} }
@ -83,7 +83,7 @@ public:
* @brief Access to rs1 field * @brief Access to rs1 field
* @return rs1 field * @return rs1 field
*/ */
inline int32_t get_rs1() { inline int32_t get_rs1() const {
return m_instr.range(19, 15); return m_instr.range(19, 15);
} }
@ -95,7 +95,7 @@ public:
* @brief Access to rs2 field * @brief Access to rs2 field
* @return rs2 field * @return rs2 field
*/ */
inline int32_t get_rs2() { inline int32_t get_rs2() const {
return m_instr.range(24, 20); return m_instr.range(24, 20);
} }
@ -103,7 +103,7 @@ public:
m_instr.range(24, 20) = value; m_instr.range(24, 20) = value;
} }
inline int32_t get_funct3() { inline int32_t get_funct3() const {
return m_instr.range(14, 12); return m_instr.range(14, 12);
} }
@ -115,23 +115,23 @@ public:
* @brief Decodes opcode of instruction * @brief Decodes opcode of instruction
* @return opcode of instruction * @return opcode of instruction
*/ */
op_A_Codes decode(); op_A_Codes decode() const;
inline void dump() { inline void dump() const{
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl; std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
} }
bool Exec_A_LR(); bool Exec_A_LR();
bool Exec_A_SC(); bool Exec_A_SC();
bool Exec_A_AMOSWAP(); bool Exec_A_AMOSWAP() const;
bool Exec_A_AMOADD(); bool Exec_A_AMOADD() const;
bool Exec_A_AMOXOR(); bool Exec_A_AMOXOR() const;
bool Exec_A_AMOAND(); bool Exec_A_AMOAND() const;
bool Exec_A_AMOOR(); bool Exec_A_AMOOR() const;
bool Exec_A_AMOMIN(); bool Exec_A_AMOMIN() const;
bool Exec_A_AMOMAX(); bool Exec_A_AMOMAX() const;
bool Exec_A_AMOMINU(); bool Exec_A_AMOMINU() const;
bool Exec_A_AMOMAXU(); bool Exec_A_AMOMAXU() const;
bool process_instruction(Instruction *inst); bool process_instruction(Instruction *inst);

126
inc/BASE_ISA.h
View File

@ -104,7 +104,7 @@ public:
* @brief Access to rd field * @brief Access to rd field
* @return rd field * @return rd field
*/ */
inline int32_t get_rd() { inline int32_t get_rd() const {
return m_instr.range(11, 7); return m_instr.range(11, 7);
} }
@ -120,7 +120,7 @@ public:
* @brief Access to rs1 field * @brief Access to rs1 field
* @return rs1 field * @return rs1 field
*/ */
inline int32_t get_rs1() { inline int32_t get_rs1() const {
return m_instr.range(19, 15); return m_instr.range(19, 15);
} }
@ -136,7 +136,7 @@ public:
* @brief Access to rs2 field * @brief Access to rs2 field
* @return rs2 field * @return rs2 field
*/ */
inline int32_t get_rs2() { inline int32_t get_rs2() const {
return m_instr.range(24, 20); return m_instr.range(24, 20);
} }
@ -152,7 +152,7 @@ public:
* @brief Access to funct3 field * @brief Access to funct3 field
* @return funct3 field * @return funct3 field
*/ */
inline int32_t get_funct3() { inline int32_t get_funct3() const {
return m_instr.range(14, 12); return m_instr.range(14, 12);
} }
@ -168,7 +168,7 @@ public:
* @brief Access to funct7 field * @brief Access to funct7 field
* @return funct7 field * @return funct7 field
*/ */
inline int32_t get_funct7() { inline int32_t get_funct7() const {
return m_instr.range(31, 25); return m_instr.range(31, 25);
} }
@ -184,7 +184,7 @@ public:
* @brief Gets immediate field value for I-type * @brief Gets immediate field value for I-type
* @return immediate_I field * @return immediate_I field
*/ */
inline int32_t get_imm_I() { inline int32_t get_imm_I() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(31, 20); aux = m_instr.range(31, 20);
@ -209,7 +209,7 @@ public:
* @brief Gets immediate field value for S-type * @brief Gets immediate field value for S-type
* @return immediate_S field * @return immediate_S field
*/ */
inline int32_t get_imm_S() { inline int32_t get_imm_S() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(31, 25) << 5; aux = m_instr.range(31, 25) << 5;
@ -237,7 +237,7 @@ public:
* @brief Gets immediate field value for U-type * @brief Gets immediate field value for U-type
* @return immediate_U field * @return immediate_U field
*/ */
inline int32_t get_imm_U() { inline int32_t get_imm_U() const {
return m_instr.range(31, 12); return m_instr.range(31, 12);
} }
@ -253,7 +253,7 @@ public:
* @brief Gets immediate field value for B-type * @brief Gets immediate field value for B-type
* @return immediate_B field * @return immediate_B field
*/ */
inline int32_t get_imm_B() { inline int32_t get_imm_B() const {
int32_t aux = 0; int32_t aux = 0;
aux |= m_instr[7] << 11; aux |= m_instr[7] << 11;
@ -285,7 +285,7 @@ public:
* @brief Gets immediate field value for J-type * @brief Gets immediate field value for J-type
* @return immediate_J field * @return immediate_J field
*/ */
inline int32_t get_imm_J() { inline int32_t get_imm_J() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr[31] << 20; aux = m_instr[31] << 20;
@ -318,7 +318,7 @@ public:
* @brief Returns shamt field for Shifts instructions * @brief Returns shamt field for Shifts instructions
* @return value corresponding to inst(25:20) * @return value corresponding to inst(25:20)
*/ */
inline int32_t get_shamt() { inline int32_t get_shamt() const {
return m_instr.range(25, 20); return m_instr.range(25, 20);
} }
@ -326,7 +326,7 @@ public:
* @brief Returns CSR field for CSR instructions * @brief Returns CSR field for CSR instructions
* @return value corresponding to instr(31:20) * @return value corresponding to instr(31:20)
*/ */
inline int32_t get_csr() { inline int32_t get_csr() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(31, 20); aux = m_instr.range(31, 20);
@ -338,73 +338,73 @@ public:
* @brief Access to opcode field * @brief Access to opcode field
* @return return opcode field * @return return opcode field
*/ */
inline int32_t opcode() { inline int32_t opcode() const {
return m_instr.range(6, 0); return m_instr.range(6, 0);
} }
bool Exec_LUI(); bool Exec_LUI() const;
bool Exec_AUIPC(); bool Exec_AUIPC() const;
bool Exec_JAL(); bool Exec_JAL() const;
bool Exec_JALR(); bool Exec_JALR() const;
bool Exec_BEQ(); bool Exec_BEQ() const;
bool Exec_BNE(); bool Exec_BNE() const;
bool Exec_BLT(); bool Exec_BLT() const;
bool Exec_BGE(); bool Exec_BGE() const;
bool Exec_BLTU(); bool Exec_BLTU() const;
bool Exec_BGEU(); bool Exec_BGEU() const;
bool Exec_LB(); bool Exec_LB() const;
bool Exec_LH(); bool Exec_LH() const;
bool Exec_LW(); bool Exec_LW() const;
bool Exec_LBU(); bool Exec_LBU() const;
bool Exec_LHU(); bool Exec_LHU() const;
bool Exec_SB(); bool Exec_SB() const;
bool Exec_SH(); bool Exec_SH() const;
bool Exec_SW(); bool Exec_SW() const;
bool Exec_SBU(); bool Exec_SBU() const;
bool Exec_SHU(); bool Exec_SHU() const;
bool Exec_ADDI(); bool Exec_ADDI() const;
bool Exec_SLTI(); bool Exec_SLTI() const;
bool Exec_SLTIU(); bool Exec_SLTIU() const;
bool Exec_XORI(); bool Exec_XORI() const;
bool Exec_ORI(); bool Exec_ORI() const;
bool Exec_ANDI(); bool Exec_ANDI() const;
bool Exec_SLLI(); bool Exec_SLLI();
bool Exec_SRLI(); bool Exec_SRLI() const;
bool Exec_SRAI(); bool Exec_SRAI() const;
bool Exec_ADD(); bool Exec_ADD() const;
bool Exec_SUB(); bool Exec_SUB() const;
bool Exec_SLL(); bool Exec_SLL() const;
bool Exec_SLT(); bool Exec_SLT() const;
bool Exec_SLTU(); bool Exec_SLTU() const;
bool Exec_XOR(); bool Exec_XOR() const;
bool Exec_SRL(); bool Exec_SRL() const;
bool Exec_SRA(); bool Exec_SRA() const;
bool Exec_OR(); bool Exec_OR() const;
bool Exec_AND(); bool Exec_AND() const;
bool Exec_FENCE(); bool Exec_FENCE() const;
bool Exec_ECALL(); bool Exec_ECALL() const;
bool Exec_EBREAK(); bool Exec_EBREAK();
bool Exec_CSRRW(); bool Exec_CSRRW() const;
bool Exec_CSRRS(); bool Exec_CSRRS() const;
bool Exec_CSRRC(); bool Exec_CSRRC() const;
bool Exec_CSRRWI(); bool Exec_CSRRWI() const;
bool Exec_CSRRSI(); bool Exec_CSRRSI() const;
bool Exec_CSRRCI(); bool Exec_CSRRCI() const;
/*********************** Privileged Instructions ******************************/ /*********************** Privileged Instructions ******************************/
bool Exec_MRET(); bool Exec_MRET() const;
bool Exec_SRET(); bool Exec_SRET() const;
bool Exec_WFI(); bool Exec_WFI() const;
bool Exec_SFENCE(); bool Exec_SFENCE() const;
/** /**
* @brief Executes default ISA instruction * @brief Executes default ISA instruction

48
inc/C_extension.h
View File

@ -105,7 +105,7 @@ public:
* @brief Access to opcode field * @brief Access to opcode field
* @return return opcode field * @return return opcode field
*/ */
inline int32_t opcode() { inline int32_t opcode() const {
return m_instr.range(1, 0); return m_instr.range(1, 0);
} }
@ -113,7 +113,7 @@ public:
* @brief Access to rd field * @brief Access to rd field
* @return rd field * @return rd field
*/ */
inline int32_t get_rd() { inline int32_t get_rd () const {
return m_instr.range(11, 7); return m_instr.range(11, 7);
} }
@ -121,7 +121,7 @@ public:
m_instr.range(11, 7) = value; m_instr.range(11, 7) = value;
} }
inline int32_t get_rdp() { inline int32_t get_rdp() const {
return m_instr.range(4, 2) + 8; return m_instr.range(4, 2) + 8;
} }
@ -129,7 +129,7 @@ public:
* @brief Access to rs1 field * @brief Access to rs1 field
* @return rs1 field * @return rs1 field
*/ */
inline int32_t get_rs1() { inline int32_t get_rs1() const {
return m_instr.range(11, 7); return m_instr.range(11, 7);
} }
@ -137,7 +137,7 @@ public:
m_instr.range(11, 7) = value; m_instr.range(11, 7) = value;
} }
inline int32_t get_rs1p() { inline int32_t get_rs1p() const {
return m_instr.range(9, 7) + 8; return m_instr.range(9, 7) + 8;
} }
@ -145,7 +145,7 @@ public:
* @brief Access to rs2 field * @brief Access to rs2 field
* @return rs2 field * @return rs2 field
*/ */
inline int32_t get_rs2() { inline int32_t get_rs2() const {
return m_instr.range(6, 2); return m_instr.range(6, 2);
} }
@ -153,11 +153,11 @@ public:
m_instr.range(6, 2) = value; m_instr.range(6, 2) = value;
} }
inline int32_t get_rs2p() { inline int32_t get_rs2p() const {
return m_instr.range(4, 2) + 8; return m_instr.range(4, 2) + 8;
} }
inline int32_t get_funct3() { inline int32_t get_funct3() const {
return m_instr.range(15, 13); return m_instr.range(15, 13);
} }
@ -169,7 +169,7 @@ public:
* @brief Access to immediate field for I-type * @brief Access to immediate field for I-type
* @return immediate_I field * @return immediate_I field
*/ */
inline int32_t get_imm_I() { inline int32_t get_imm_I() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(31, 20); aux = m_instr.range(31, 20);
@ -190,7 +190,7 @@ public:
* @brief Access to immediate field for S-type * @brief Access to immediate field for S-type
* @return immediate_S field * @return immediate_S field
*/ */
inline int32_t get_imm_S() { inline int32_t get_imm_S() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(31, 25) << 5; aux = m_instr.range(31, 25) << 5;
@ -214,7 +214,7 @@ public:
* @brief Access to immediate field for U-type * @brief Access to immediate field for U-type
* @return immediate_U field * @return immediate_U field
*/ */
inline int32_t get_imm_U() { inline int32_t get_imm_U() const {
return m_instr.range(31, 12); return m_instr.range(31, 12);
} }
@ -226,7 +226,7 @@ public:
* @brief Access to immediate field for B-type * @brief Access to immediate field for B-type
* @return immediate_B field * @return immediate_B field
*/ */
inline int32_t get_imm_B() { inline int32_t get_imm_B() const {
int32_t aux = 0; int32_t aux = 0;
aux |= m_instr[7] << 11; aux |= m_instr[7] << 11;
@ -253,7 +253,7 @@ public:
* @brief Access to immediate field for J-type * @brief Access to immediate field for J-type
* @return immediate_J field * @return immediate_J field
*/ */
inline int32_t get_imm_J() { inline int32_t get_imm_J() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr[12] << 11; aux = m_instr[12] << 11;
@ -282,7 +282,7 @@ public:
m_instr.range(19, 12) = aux.range(19, 12); m_instr.range(19, 12) = aux.range(19, 12);
} }
inline int32_t get_imm_L() { inline int32_t get_imm_L() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(12, 10) << 3; aux = m_instr.range(12, 10) << 3;
@ -292,7 +292,7 @@ public:
return aux; return aux;
} }
inline int32_t get_imm_LWSP() { inline int32_t get_imm_LWSP() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr[12] << 5; aux = m_instr[12] << 5;
@ -302,7 +302,7 @@ public:
return aux; return aux;
} }
inline int32_t get_imm_ADDI() { inline int32_t get_imm_ADDI () const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr[12] << 5; aux = m_instr[12] << 5;
@ -314,7 +314,7 @@ public:
return aux; return aux;
} }
inline int32_t get_imm_ADDI4SPN() { inline int32_t get_imm_ADDI4SPN() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(12, 11) << 4; aux = m_instr.range(12, 11) << 4;
@ -325,7 +325,7 @@ public:
return aux; return aux;
} }
inline int32_t get_imm_ADDI16SP() { inline int32_t get_imm_ADDI16SP() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr[12] << 9; aux = m_instr[12] << 9;
@ -341,7 +341,7 @@ public:
return aux; return aux;
} }
inline int32_t get_imm_CSS() { inline int32_t get_imm_CSS() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr.range(12, 9) << 2; aux = m_instr.range(12, 9) << 2;
aux |= m_instr.range(8, 7) << 6; aux |= m_instr.range(8, 7) << 6;
@ -349,7 +349,7 @@ public:
return aux; return aux;
} }
inline int32_t get_imm_CB() { inline int32_t get_imm_CB() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr[12] << 8; aux = m_instr[12] << 8;
@ -368,7 +368,7 @@ public:
return aux; return aux;
} }
inline int32_t get_imm_LUI() { inline int32_t get_imm_LUI() const {
int32_t aux = 0; int32_t aux = 0;
aux = m_instr[12] << 17; aux = m_instr[12] << 17;
@ -381,7 +381,7 @@ public:
return aux; return aux;
} }
inline int32_t get_csr() { inline int32_t get_csr() const {
return get_imm_I(); return get_imm_I();
} }
@ -389,7 +389,7 @@ public:
* @brief Decodes opcode of instruction * @brief Decodes opcode of instruction
* @return opcode of instruction * @return opcode of instruction
*/ */
op_C_Codes decode(); op_C_Codes decode() const;
bool Exec_C_JR(); bool Exec_C_JR();
bool Exec_C_MV(); bool Exec_C_MV();
@ -410,7 +410,7 @@ public:
bool Exec_C_OR(); bool Exec_C_OR();
bool Exec_C_AND(); bool Exec_C_AND();
bool Exec_C_ADDI(); bool Exec_C_ADDI() const;
bool Exec_C_JALR(); bool Exec_C_JALR();
bool Exec_C_LW(); bool Exec_C_LW();
bool Exec_C_SW(); bool Exec_C_SW();

30
inc/M_extension.h
View File

@ -54,20 +54,20 @@ public:
* @brief Decodes opcode of instruction * @brief Decodes opcode of instruction
* @return opcode of instruction * @return opcode of instruction
*/ */
op_M_Codes decode(); op_M_Codes decode() const;
inline void dump() { inline void dump() const{
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl; std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
} }
bool Exec_M_MUL(); bool Exec_M_MUL() const;
bool Exec_M_MULH(); bool Exec_M_MULH() const;
bool Exec_M_MULHSU(); bool Exec_M_MULHSU() const;
bool Exec_M_MULHU(); bool Exec_M_MULHU() const;
bool Exec_M_DIV(); bool Exec_M_DIV() const;
bool Exec_M_DIVU(); bool Exec_M_DIVU() const;
bool Exec_M_REM(); bool Exec_M_REM() const;
bool Exec_M_REMU(); bool Exec_M_REMU() const;
bool process_instruction(Instruction *inst); bool process_instruction(Instruction *inst);
@ -77,7 +77,7 @@ private:
* @brief Access to opcode field * @brief Access to opcode field
* @return return opcode field * @return return opcode field
*/ */
inline int32_t opcode() { inline int32_t opcode() const {
return m_instr.range(14, 12); return m_instr.range(14, 12);
} }
@ -85,7 +85,7 @@ private:
* @brief Access to rd field * @brief Access to rd field
* @return rd field * @return rd field
*/ */
inline int32_t get_rd() { inline int32_t get_rd() const {
return m_instr.range(11, 7); return m_instr.range(11, 7);
} }
@ -97,7 +97,7 @@ private:
* @brief Access to rs1 field * @brief Access to rs1 field
* @return rs1 field * @return rs1 field
*/ */
inline int32_t get_rs1() { inline int32_t get_rs1() const {
return m_instr.range(19, 15); return m_instr.range(19, 15);
} }
@ -109,7 +109,7 @@ private:
* @brief Access to rs2 field * @brief Access to rs2 field
* @return rs2 field * @return rs2 field
*/ */
inline int32_t get_rs2() { inline int32_t get_rs2() const {
return m_instr.range(24, 20); return m_instr.range(24, 20);
} }
@ -117,7 +117,7 @@ private:
m_instr.range(24, 20) = value; m_instr.range(24, 20) = value;
} }
inline int32_t get_funct3() { inline int32_t get_funct3() const {
return m_instr.range(14, 12); return m_instr.range(14, 12);
} }

2
inc/Memory.h
View File

@ -83,6 +83,6 @@ private:
* @brief Read Intel hex file * @brief Read Intel hex file
* @param filename file name to read * @param filename file name to read
*/ */
virtual void readHexFile(std::string filename); void readHexFile(std::string filename);
}; };
#endif /* __MEMORY_H__ */ #endif /* __MEMORY_H__ */

10
inc/extension_base.h
View File

@ -35,14 +35,14 @@ public:
bool NOP(); bool NOP();
/* pure virtual functions */ /* pure virtual functions */
virtual int32_t opcode() = 0; virtual int32_t opcode() const = 0;
virtual int32_t get_rd() = 0; virtual int32_t get_rd() const = 0;
virtual void set_rd(int32_t value) = 0; virtual void set_rd(int32_t value) = 0;
virtual int32_t get_rs1() = 0; virtual int32_t get_rs1() const = 0;
virtual void set_rs1(int32_t value) = 0; virtual void set_rs1(int32_t value) = 0;
virtual int32_t get_rs2() = 0; virtual int32_t get_rs2() const = 0;
virtual void set_rs2(int32_t value) = 0; virtual void set_rs2(int32_t value) = 0;
virtual int32_t get_funct3() = 0; virtual int32_t get_funct3() const = 0;
virtual void set_funct3(int32_t value) = 0; virtual void set_funct3(int32_t value) = 0;
void dump(); void dump();

20
src/A_extension.cpp
View File

@ -8,7 +8,7 @@
#include "A_extension.h" #include "A_extension.h"
op_A_Codes A_extension::decode() { op_A_Codes A_extension::decode() const {
switch (opcode()) { switch (opcode()) {
case A_LR: case A_LR:
@ -107,7 +107,7 @@ bool A_extension::Exec_A_SC() {
return true; return true;
} }
bool A_extension::Exec_A_AMOSWAP() { bool A_extension::Exec_A_AMOSWAP() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;
@ -134,7 +134,7 @@ bool A_extension::Exec_A_AMOSWAP() {
return true; return true;
} }
bool A_extension::Exec_A_AMOADD() { bool A_extension::Exec_A_AMOADD() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;
@ -160,7 +160,7 @@ bool A_extension::Exec_A_AMOADD() {
return true; return true;
} }
bool A_extension::Exec_A_AMOXOR() { bool A_extension::Exec_A_AMOXOR() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;
@ -185,7 +185,7 @@ bool A_extension::Exec_A_AMOXOR() {
return true; return true;
} }
bool A_extension::Exec_A_AMOAND() { bool A_extension::Exec_A_AMOAND() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;
@ -211,7 +211,7 @@ bool A_extension::Exec_A_AMOAND() {
return true; return true;
} }
bool A_extension::Exec_A_AMOOR() { bool A_extension::Exec_A_AMOOR() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;
@ -236,7 +236,7 @@ bool A_extension::Exec_A_AMOOR() {
return true; return true;
} }
bool A_extension::Exec_A_AMOMIN() { bool A_extension::Exec_A_AMOMIN() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;
@ -265,7 +265,7 @@ bool A_extension::Exec_A_AMOMIN() {
return true; return true;
} }
bool A_extension::Exec_A_AMOMAX() { bool A_extension::Exec_A_AMOMAX() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;
@ -294,7 +294,7 @@ bool A_extension::Exec_A_AMOMAX() {
return true; return true;
} }
bool A_extension::Exec_A_AMOMINU() { bool A_extension::Exec_A_AMOMINU() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;
@ -323,7 +323,7 @@ bool A_extension::Exec_A_AMOMINU() {
return true; return true;
} }
bool A_extension::Exec_A_AMOMAXU() { bool A_extension::Exec_A_AMOMAXU() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t data; uint32_t data;

103
src/BASE_ISA.cpp
View File

@ -82,7 +82,7 @@ typedef enum {
CSRRCI = 0b111, CSRRCI = 0b111,
} Codes; } Codes;
bool BASE_ISA::Exec_LUI() { bool BASE_ISA::Exec_LUI() const {
int rd; int rd;
uint32_t imm = 0; uint32_t imm = 0;
@ -98,7 +98,7 @@ bool BASE_ISA::Exec_LUI() {
return true; return true;
} }
bool BASE_ISA::Exec_AUIPC() { bool BASE_ISA::Exec_AUIPC() const {
int rd; int rd;
uint32_t imm = 0; uint32_t imm = 0;
int new_pc; int new_pc;
@ -117,7 +117,7 @@ bool BASE_ISA::Exec_AUIPC() {
return true; return true;
} }
bool BASE_ISA::Exec_JAL() { bool BASE_ISA::Exec_JAL() const {
int32_t mem_addr = 0; int32_t mem_addr = 0;
int rd; int rd;
int new_pc, old_pc; int new_pc, old_pc;
@ -141,7 +141,7 @@ bool BASE_ISA::Exec_JAL() {
return true; return true;
} }
bool BASE_ISA::Exec_JALR() { bool BASE_ISA::Exec_JALR() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1; int rd, rs1;
int new_pc, old_pc; int new_pc, old_pc;
@ -163,7 +163,7 @@ bool BASE_ISA::Exec_JALR() {
return true; return true;
} }
bool BASE_ISA::Exec_BEQ() { bool BASE_ISA::Exec_BEQ() const {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
@ -188,7 +188,7 @@ bool BASE_ISA::Exec_BEQ() {
return true; return true;
} }
bool BASE_ISA::Exec_BNE() { bool BASE_ISA::Exec_BNE() const {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
uint32_t val1, val2; uint32_t val1, val2;
@ -217,7 +217,7 @@ bool BASE_ISA::Exec_BNE() {
return true; return true;
} }
bool BASE_ISA::Exec_BLT() { bool BASE_ISA::Exec_BLT() const {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
@ -242,7 +242,7 @@ bool BASE_ISA::Exec_BLT() {
return true; return true;
} }
bool BASE_ISA::Exec_BGE() { bool BASE_ISA::Exec_BGE() const {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
@ -267,7 +267,7 @@ bool BASE_ISA::Exec_BGE() {
return true; return true;
} }
bool BASE_ISA::Exec_BLTU() { bool BASE_ISA::Exec_BLTU() const {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
@ -292,7 +292,7 @@ bool BASE_ISA::Exec_BLTU() {
return true; return true;
} }
bool BASE_ISA::Exec_BGEU() { bool BASE_ISA::Exec_BGEU() const {
int rs1, rs2; int rs1, rs2;
int new_pc = 0; int new_pc = 0;
@ -316,7 +316,7 @@ bool BASE_ISA::Exec_BGEU() {
return true; return true;
} }
bool BASE_ISA::Exec_LB() { bool BASE_ISA::Exec_LB() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1; int rd, rs1;
int32_t imm = 0; int32_t imm = 0;
@ -338,7 +338,7 @@ bool BASE_ISA::Exec_LB() {
return true; return true;
} }
bool BASE_ISA::Exec_LH() { bool BASE_ISA::Exec_LH() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1; int rd, rs1;
int32_t imm = 0; int32_t imm = 0;
@ -360,7 +360,7 @@ bool BASE_ISA::Exec_LH() {
return true; return true;
} }
bool BASE_ISA::Exec_LW() { bool BASE_ISA::Exec_LW() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1; int rd, rs1;
int32_t imm = 0; int32_t imm = 0;
@ -383,7 +383,7 @@ bool BASE_ISA::Exec_LW() {
return true; return true;
} }
bool BASE_ISA::Exec_LBU() { bool BASE_ISA::Exec_LBU() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1; int rd, rs1;
int32_t imm = 0; int32_t imm = 0;
@ -404,7 +404,7 @@ bool BASE_ISA::Exec_LBU() {
return true; return true;
} }
bool BASE_ISA::Exec_LHU() { bool BASE_ISA::Exec_LHU() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rd, rs1; int rd, rs1;
int32_t imm = 0; int32_t imm = 0;
@ -427,7 +427,7 @@ bool BASE_ISA::Exec_LHU() {
return true; return true;
} }
bool BASE_ISA::Exec_SB() { bool BASE_ISA::Exec_SB() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rs1, rs2; int rs1, rs2;
int32_t imm = 0; int32_t imm = 0;
@ -451,7 +451,7 @@ bool BASE_ISA::Exec_SB() {
return true; return true;
} }
bool BASE_ISA::Exec_SH() { bool BASE_ISA::Exec_SH() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rs1, rs2; int rs1, rs2;
int32_t imm = 0; int32_t imm = 0;
@ -475,7 +475,7 @@ bool BASE_ISA::Exec_SH() {
return true; return true;
} }
bool BASE_ISA::Exec_SW() { bool BASE_ISA::Exec_SW() const {
uint32_t mem_addr = 0; uint32_t mem_addr = 0;
int rs1, rs2; int rs1, rs2;
int32_t imm = 0; int32_t imm = 0;
@ -498,7 +498,7 @@ bool BASE_ISA::Exec_SW() {
return true; return true;
} }
bool BASE_ISA::Exec_ADDI() { bool BASE_ISA::Exec_ADDI() const {
int rd, rs1; int rd, rs1;
int32_t imm = 0; int32_t imm = 0;
int32_t calc; int32_t calc;
@ -519,7 +519,7 @@ bool BASE_ISA::Exec_ADDI() {
return true; return true;
} }
bool BASE_ISA::Exec_SLTI() { bool BASE_ISA::Exec_SLTI() const {
int rd, rs1; int rd, rs1;
int32_t imm; int32_t imm;
@ -540,7 +540,7 @@ bool BASE_ISA::Exec_SLTI() {
return true; return true;
} }
bool BASE_ISA::Exec_SLTIU() { bool BASE_ISA::Exec_SLTIU() const {
int rd, rs1; int rd, rs1;
int32_t imm; int32_t imm;
@ -561,7 +561,7 @@ bool BASE_ISA::Exec_SLTIU() {
return true; return true;
} }
bool BASE_ISA::Exec_XORI() { bool BASE_ISA::Exec_XORI() const {
int rd, rs1; int rd, rs1;
int32_t imm; int32_t imm;
uint32_t calc; uint32_t calc;
@ -581,7 +581,7 @@ bool BASE_ISA::Exec_XORI() {
return true; return true;
} }
bool BASE_ISA::Exec_ORI() { bool BASE_ISA::Exec_ORI() const {
int rd, rs1; int rd, rs1;
int32_t imm; int32_t imm;
uint32_t calc; uint32_t calc;
@ -601,7 +601,7 @@ bool BASE_ISA::Exec_ORI() {
return true; return true;
} }
bool BASE_ISA::Exec_ANDI() { bool BASE_ISA::Exec_ANDI() const {
int rd, rs1; int rd, rs1;
uint32_t imm; uint32_t imm;
uint32_t calc; uint32_t calc;
@ -653,7 +653,7 @@ bool BASE_ISA::Exec_SLLI() {
return true; return true;
} }
bool BASE_ISA::Exec_SRLI() { bool BASE_ISA::Exec_SRLI() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t shift; uint32_t shift;
uint32_t calc; uint32_t calc;
@ -675,7 +675,7 @@ bool BASE_ISA::Exec_SRLI() {
return true; return true;
} }
bool BASE_ISA::Exec_SRAI() { bool BASE_ISA::Exec_SRAI() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t shift; uint32_t shift;
int32_t calc; int32_t calc;
@ -697,7 +697,7 @@ bool BASE_ISA::Exec_SRAI() {
return true; return true;
} }
bool BASE_ISA::Exec_ADD() { bool BASE_ISA::Exec_ADD() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
rd = get_rd(); rd = get_rd();
@ -716,7 +716,7 @@ bool BASE_ISA::Exec_ADD() {
return true; return true;
} }
bool BASE_ISA::Exec_SUB() { bool BASE_ISA::Exec_SUB() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
rd = get_rd(); rd = get_rd();
@ -734,7 +734,7 @@ bool BASE_ISA::Exec_SUB() {
return true; return true;
} }
bool BASE_ISA::Exec_SLL() { bool BASE_ISA::Exec_SLL() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t shift; uint32_t shift;
uint32_t calc; uint32_t calc;
@ -756,7 +756,7 @@ bool BASE_ISA::Exec_SLL() {
return true; return true;
} }
bool BASE_ISA::Exec_SLT() { bool BASE_ISA::Exec_SLT() const {
int rd, rs1, rs2; int rd, rs1, rs2;
rd = get_rd(); rd = get_rd();
@ -776,7 +776,7 @@ bool BASE_ISA::Exec_SLT() {
return true; return true;
} }
bool BASE_ISA::Exec_SLTU() { bool BASE_ISA::Exec_SLTU() const {
int rd, rs1, rs2; int rd, rs1, rs2;
rd = get_rd(); rd = get_rd();
@ -796,7 +796,7 @@ bool BASE_ISA::Exec_SLTU() {
return true; return true;
} }
bool BASE_ISA::Exec_XOR() { bool BASE_ISA::Exec_XOR() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
@ -815,7 +815,7 @@ bool BASE_ISA::Exec_XOR() {
return true; return true;
} }
bool BASE_ISA::Exec_SRL() { bool BASE_ISA::Exec_SRL() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t shift; uint32_t shift;
uint32_t calc; uint32_t calc;
@ -837,7 +837,7 @@ bool BASE_ISA::Exec_SRL() {
return true; return true;
} }
bool BASE_ISA::Exec_SRA() { bool BASE_ISA::Exec_SRA() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t shift; uint32_t shift;
int32_t calc; int32_t calc;
@ -859,7 +859,7 @@ bool BASE_ISA::Exec_SRA() {
return true; return true;
} }
bool BASE_ISA::Exec_OR() { bool BASE_ISA::Exec_OR() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
@ -878,7 +878,7 @@ bool BASE_ISA::Exec_OR() {
return true; return true;
} }
bool BASE_ISA::Exec_AND() { bool BASE_ISA::Exec_AND() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t calc; uint32_t calc;
@ -897,13 +897,13 @@ bool BASE_ISA::Exec_AND() {
return true; return true;
} }
bool BASE_ISA::Exec_FENCE() { bool BASE_ISA::Exec_FENCE() const {
log->SC_log(Log::INFO) << "FENCE" << "\n"; log->SC_log(Log::INFO) << "FENCE" << "\n";
return true; return true;
} }
bool BASE_ISA::Exec_ECALL() { bool BASE_ISA::Exec_ECALL() const {
log->SC_log(Log::INFO) << "ECALL" << "\n"; log->SC_log(Log::INFO) << "ECALL" << "\n";
std::cout << "\n" << "ECALL Instruction called, stopping simulation" std::cout << "\n" << "ECALL Instruction called, stopping simulation"
@ -937,7 +937,7 @@ bool BASE_ISA::Exec_EBREAK() {
return true; return true;
} }
bool BASE_ISA::Exec_CSRRW() { bool BASE_ISA::Exec_CSRRW() const {
int rd, rs1; int rd, rs1;
int csr; int csr;
uint32_t aux; uint32_t aux;
@ -962,7 +962,7 @@ bool BASE_ISA::Exec_CSRRW() {
return true; return true;
} }
bool BASE_ISA::Exec_CSRRS() { bool BASE_ISA::Exec_CSRRS() const {
int rd, rs1; int rd, rs1;
int csr; int csr;
uint32_t bitmask, aux, aux2; uint32_t bitmask, aux, aux2;
@ -993,7 +993,7 @@ bool BASE_ISA::Exec_CSRRS() {
return true; return true;
} }
bool BASE_ISA::Exec_CSRRC() { bool BASE_ISA::Exec_CSRRC() const {
int rd, rs1; int rd, rs1;
int csr; int csr;
uint32_t bitmask, aux, aux2; uint32_t bitmask, aux, aux2;
@ -1024,7 +1024,7 @@ bool BASE_ISA::Exec_CSRRC() {
return true; return true;
} }
bool BASE_ISA::Exec_CSRRWI() { bool BASE_ISA::Exec_CSRRWI() const {
int rd, rs1; int rd, rs1;
int csr; int csr;
uint32_t aux; uint32_t aux;
@ -1047,7 +1047,7 @@ bool BASE_ISA::Exec_CSRRWI() {
return true; return true;
} }
bool BASE_ISA::Exec_CSRRSI() { bool BASE_ISA::Exec_CSRRSI() const {
int rd, rs1; int rd, rs1;
int csr; int csr;
uint32_t bitmask, aux; uint32_t bitmask, aux;
@ -1075,7 +1075,7 @@ bool BASE_ISA::Exec_CSRRSI() {
return true; return true;
} }
bool BASE_ISA::Exec_CSRRCI() { bool BASE_ISA::Exec_CSRRCI() const {
int rd, rs1; int rd, rs1;
int csr; int csr;
uint32_t bitmask, aux; uint32_t bitmask, aux;
@ -1105,7 +1105,7 @@ bool BASE_ISA::Exec_CSRRCI() {
/*********************** Privileged Instructions ******************************/ /*********************** Privileged Instructions ******************************/
bool BASE_ISA::Exec_MRET() { bool BASE_ISA::Exec_MRET() const {
uint32_t new_pc = 0; uint32_t new_pc = 0;
new_pc = regs->getCSR(CSR_MEPC); new_pc = regs->getCSR(CSR_MEPC);
@ -1126,7 +1126,7 @@ bool BASE_ISA::Exec_MRET() {
return true; return true;
} }
bool BASE_ISA::Exec_SRET() { bool BASE_ISA::Exec_SRET() const {
uint32_t new_pc = 0; uint32_t new_pc = 0;
new_pc = regs->getCSR(CSR_SEPC); new_pc = regs->getCSR(CSR_SEPC);
@ -1138,13 +1138,13 @@ bool BASE_ISA::Exec_SRET() {
return true; return true;
} }
bool BASE_ISA::Exec_WFI() { bool BASE_ISA::Exec_WFI() const {
log->SC_log(Log::INFO) << "WFI" << "\n"; log->SC_log(Log::INFO) << "WFI" << "\n";
return true; return true;
} }
bool BASE_ISA::Exec_SFENCE() { bool BASE_ISA::Exec_SFENCE() const {
log->SC_log(Log::INFO) << "SFENCE" << "\n"; log->SC_log(Log::INFO) << "SFENCE" << "\n";
return true; return true;
@ -1411,8 +1411,9 @@ opCodes BASE_ISA::decode() {
return OP_ADD; return OP_ADD;
case SUB_F7: case SUB_F7:
return OP_SUB; return OP_SUB;
default:
return OP_ADD;
} }
;
break; break;
case SLL_F: case SLL_F:
return OP_SLL; return OP_SLL;
@ -1428,11 +1429,15 @@ opCodes BASE_ISA::decode() {
return OP_SRL; return OP_SRL;
case SRA_F7: case SRA_F7:
return OP_SRA; return OP_SRA;
default:
return OP_ERROR;
} }
case OR_F: case OR_F:
return OP_OR; return OP_OR;
case AND_F: case AND_F:
return OP_AND; return OP_AND;
default:
return OP_ERROR;
} }
} /* ADD */ } /* ADD */
case FENCE: case FENCE:

4
src/C_extension.cpp
View File

@ -6,7 +6,7 @@
*/ */
#include "C_extension.h" #include "C_extension.h"
op_C_Codes C_extension::decode() { op_C_Codes C_extension::decode() const {
switch (opcode()) { switch (opcode()) {
@ -547,7 +547,7 @@ bool C_extension::Exec_C_AND() {
return true; return true;
} }
bool C_extension::Exec_C_ADDI() { bool C_extension::Exec_C_ADDI() const {
int rd, rs1; int rd, rs1;
int32_t imm = 0; int32_t imm = 0;
int32_t calc; int32_t calc;

18
src/M_extension.cpp
View File

@ -8,7 +8,7 @@
#include "M_extension.h" #include "M_extension.h"
op_M_Codes M_extension::decode() { op_M_Codes M_extension::decode() const {
switch (opcode()) { switch (opcode()) {
case M_MUL: case M_MUL:
@ -43,7 +43,7 @@ op_M_Codes M_extension::decode() {
return OP_M_ERROR; return OP_M_ERROR;
} }
bool M_extension::Exec_M_MUL() { bool M_extension::Exec_M_MUL() const {
int rd, rs1, rs2; int rd, rs1, rs2;
int32_t multiplier, multiplicand; int32_t multiplier, multiplicand;
int64_t result; int64_t result;
@ -65,7 +65,7 @@ bool M_extension::Exec_M_MUL() {
return true; return true;
} }
bool M_extension::Exec_M_MULH() { bool M_extension::Exec_M_MULH() const {
int rd, rs1, rs2; int rd, rs1, rs2;
int32_t multiplier, multiplicand; int32_t multiplier, multiplicand;
int64_t result; int64_t result;
@ -89,7 +89,7 @@ bool M_extension::Exec_M_MULH() {
return true; return true;
} }
bool M_extension::Exec_M_MULHSU() { bool M_extension::Exec_M_MULHSU() const {
int rd, rs1, rs2; int rd, rs1, rs2;
int32_t multiplier; int32_t multiplier;
uint32_t multiplicand; uint32_t multiplicand;
@ -112,7 +112,7 @@ bool M_extension::Exec_M_MULHSU() {
return true; return true;
} }
bool M_extension::Exec_M_MULHU() { bool M_extension::Exec_M_MULHU() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t multiplier, multiplicand; uint32_t multiplier, multiplicand;
uint64_t result; uint64_t result;
@ -135,7 +135,7 @@ bool M_extension::Exec_M_MULHU() {
return true; return true;
} }
bool M_extension::Exec_M_DIV() { bool M_extension::Exec_M_DIV() const {
int rd, rs1, rs2; int rd, rs1, rs2;
int32_t divisor, dividend; int32_t divisor, dividend;
int64_t result; int64_t result;
@ -164,7 +164,7 @@ bool M_extension::Exec_M_DIV() {
return true; return true;
} }
bool M_extension::Exec_M_DIVU() { bool M_extension::Exec_M_DIVU() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t divisor, dividend; uint32_t divisor, dividend;
uint64_t result; uint64_t result;
@ -191,7 +191,7 @@ bool M_extension::Exec_M_DIVU() {
return true; return true;
} }
bool M_extension::Exec_M_REM() { bool M_extension::Exec_M_REM() const {
int rd, rs1, rs2; int rd, rs1, rs2;
int32_t divisor, dividend; int32_t divisor, dividend;
int32_t result; int32_t result;
@ -219,7 +219,7 @@ bool M_extension::Exec_M_REM() {
return true; return true;
} }
bool M_extension::Exec_M_REMU() { bool M_extension::Exec_M_REMU() const {
int rd, rs1, rs2; int rd, rs1, rs2;
uint32_t divisor, dividend; uint32_t divisor, dividend;
uint32_t result; uint32_t result;