typos, register definitions
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@ -71,7 +71,7 @@ private:
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/**
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*
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* @brief Process and triggers IRQ if all conditions memory_socket
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* @brief Process and triggers IRQ if all conditions met
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* @return true if IRQ is triggered, false otherwise
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*/
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bool cpu_process_IRQ();
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@ -95,6 +95,8 @@ private:
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* @brief callback for IRQ simple socket
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* @param trans transaction to perform (empty)
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* @param delay time to annotate
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*
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* When called it triggers an IRQ
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*/
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void call_interrupt(tlm::tlm_generic_payload &trans, sc_time &delay);
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};
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@ -59,6 +59,45 @@
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#define CSR_STVEC (0x105)
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#define MSTATUS_UIE (1 << 0)
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#define MSTATUS_SIE (1 << 1)
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#define MSTATUS_MIE (1 << 3)
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#define MSTATUS_UPIE (1 << 4)
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#define MSTATUS_SPIE (1 << 5)
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#define MSTATUS_MPIE (1 << 7)
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#define MSTATUS_SPP (1 << 8)
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#define MSTATUS_MPP (1 << 11)
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#define MSTATUS_FS (1 << 13)
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#define MSTATUS_XS (1 << 15)
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#define MSTATUS_MPRV (1 << 17)
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#define MSTATUS_SUM (1 << 18)
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#define MSTATUS_MXR (1 << 19)
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#define MSTATUS_TVM (1 << 20)
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#define MSTATUS_TW (1 << 21)
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#define MSTATUS_TSR (1 << 22)
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#define MIP_USIP (1 << 0)
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#define MIP_SSIP (1 << 1)
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#define MIP_MSIP (1 << 3)
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#define MIP_UTIP (1 << 4)
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#define MIP_STIP (1 << 5)
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#define MIP_MTIP (1 << 7)
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#define MIP_UEIP (1 << 8)
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#define MIP_SEIP (1 << 9)
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#define MIP_MEIP (1 << 11)
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#define MIE_USIE (1 << 0)
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#define MIE_SSIE (1 << 1)
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#define MIE_MSIE (1 << 3)
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#define MIE_UTIE (1 << 4)
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#define MIE_STIE (1 << 5)
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#define MIE_MTIE (1 << 7)
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#define MIE_UEIE (1 << 8)
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#define MIE_SEIE (1 << 9)
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#define MIE_MEIE (1 << 11)
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/* 1 ns tick in CYCLE & TIME counters */
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#define TICKS_PER_SECOND (1000000)
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@ -58,9 +58,9 @@ public:
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/**
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*
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* @brief TLM-2.0 socket implementaiton
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* @brief TLM-2.0 socket implementation
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* @param trans TLM-2.0 transaction
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* @param delay transactino delay time
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* @param delay transaction delay time
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*/
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virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay );
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