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update

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mariusmonton 2019-01-10 14:58:27 +01:00
parent f1f98faf13
commit 2db8092a04
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@ -45,17 +45,20 @@ i5-5200<span>@</span>2.2Ghz
This is a preliminar and incomplete version. This is a preliminar and incomplete version.
Task to do: Task to do:
* ~~Iimplement all missing instructions (Execute)~~ - [x] Implement all missing instructions (Execute)
* ~~Implement CSRs (where/how?)~~ - [x] Implement CSRs (where/how?)
* Add full support to .elf ~~and .hex~~ filetypes to memory.h - [ ] Add full support to read file with memory contents (to memory.h)
(only partial .hex support) - [ ] .elf files
* Connect some TLM peripherals - [x] .hex files (only partial .hex support)
* ~~Debug module similiar to ARM's ITM~~ - [ ] Connect some TLM peripherals
* Some standard UART model - [x] Debug module similiar to ARM's ITM
* ... - [ ] Some standard UART model
* Test, test, test & test. I'm sure there are a lot of bugs in the code - [ ] ...
* riscv-test almost incomplete - [ ] Implement interrupts
* riscv-compliance WiP - [ ] implement timer (mtimecmp) & timer interrupt
- [x] Test, test, test & test. I'm sure there are a ~~lot of~~ some bugs in the code
- [x] riscv-test almost complete (see [Test](Tests.md))
- [ ] riscv-compliance WiP
* Improve structure and modules hierarchy * Improve structure and modules hierarchy
* Add 64 & 128 bits architecture (RV64I, RV128I) * Add 64 & 128 bits architecture (RV64I, RV128I)