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risc-v-tlm
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code clean-up (using clang-tidy)

This commit is contained in:
Màrius Montón 2021-04-25 19:52:12 +02:00
parent da4ebcbe6c
commit 3b3813bd07
17 changed files with 34 additions and 33 deletions
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2
inc/BusCtrl.h
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@ -72,7 +72,7 @@ public:
* @brief constructor * @brief constructor
* @param name module's name * @param name module's name
*/ */
BusCtrl(sc_core::sc_module_name name); explicit BusCtrl(sc_core::sc_module_name name);
/** /**
* @brief TLM-2 blocking mechanism * @brief TLM-2 blocking mechanism

6
inc/CPU.h
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@ -59,11 +59,11 @@ public:
/** /**
* @brief Destructor * @brief Destructor
*/ */
~CPU(); ~CPU() override;
MemoryInterface *mem_intf; MemoryInterface *mem_intf;
bool CPU_step(void); bool CPU_step();
Registers *getRegisterBank() {return register_bank;} Registers *getRegisterBank() {return register_bank;}
@ -103,7 +103,7 @@ private:
* main thread for CPU simulation * main thread for CPU simulation
* @brief CPU mai thread * @brief CPU mai thread
*/ */
void CPU_thread(void); [[noreturn]] void CPU_thread();
/** /**
* @brief callback for IRQ simple socket * @brief callback for IRQ simple socket

2
inc/C_extension.h
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@ -105,7 +105,7 @@ public:
* @brief Access to opcode field * @brief Access to opcode field
* @return return opcode field * @return return opcode field
*/ */
inline int32_t opcode() const { inline int32_t opcode() const override {
return m_instr.range(1, 0); return m_instr.range(1, 0);
} }

4
inc/Debug.h
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@ -24,10 +24,10 @@ class Debug: sc_core::sc_module {
public: public:
Debug(CPU *cpu, Memory* mem); Debug(CPU *cpu, Memory* mem);
~Debug(); ~Debug() override;
private: private:
std::string compute_checksum_string(const std::string &msg); static std::string compute_checksum_string(const std::string &msg);
void send_packet(int conn, const std::string &msg); void send_packet(int conn, const std::string &msg);
std::string receive_packet(); std::string receive_packet();
void handle_gdb_loop(); void handle_gdb_loop();

2
inc/Log.h
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@ -68,7 +68,7 @@ public:
private: private:
static Log *instance; static Log *instance;
Log(const char *filename); explicit Log(const char *filename);
std::ofstream m_stream; std::ofstream m_stream;
std::ofstream m_sink; std::ofstream m_sink;
}; };

4
inc/M_extension.h
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@ -56,7 +56,7 @@ public:
*/ */
op_M_Codes decode() const; op_M_Codes decode() const;
inline virtual void dump() const override { inline void dump() const override {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl; std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
} }
@ -77,7 +77,7 @@ private:
* @brief Access to opcode field * @brief Access to opcode field
* @return return opcode field * @return return opcode field
*/ */
inline int32_t opcode() const { inline int32_t opcode() const override {
return m_instr.range(14, 12); return m_instr.range(14, 12);
} }

4
inc/Memory.h
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@ -36,9 +36,9 @@ public:
const sc_core::sc_time LATENCY; const sc_core::sc_time LATENCY;
Memory(sc_core::sc_module_name const &name, std::string const &filename); Memory(sc_core::sc_module_name const &name, std::string const &filename);
Memory(const sc_core::sc_module_name& name); explicit Memory(const sc_core::sc_module_name& name);
~Memory(void); ~Memory() override;
/** /**
* @brief Returns Program Counter read from hexfile * @brief Returns Program Counter read from hexfile

2
inc/Performance.h
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@ -83,7 +83,7 @@ public:
*/ */
void dump() const; void dump() const;
inline uint_fast64_t getInstructions() { inline uint_fast64_t getInstructions() const {
return instructions_executed; return instructions_executed;
} }

2
inc/Registers.h
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@ -261,7 +261,7 @@ private:
Performance *perf; Performance *perf;
void initCSR(void); void initCSR();
}; };
#endif #endif

4
inc/Timer.h
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@ -39,7 +39,7 @@ public:
* @brief Constructor * @brief Constructor
* @param name module name * @param name module name
*/ */
Timer(sc_core::sc_module_name const &name); explicit Timer(sc_core::sc_module_name const &name);
/** /**
* @brief Waits for event timer_event and triggers an IRQ * @brief Waits for event timer_event and triggers an IRQ
@ -50,7 +50,7 @@ public:
* line. * line.
* *
*/ */
void run(); [[noreturn]] void run();
/** /**
* *

12
inc/Trace.h
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@ -36,12 +36,12 @@ public:
* @brief Constructor * @brief Constructor
* @param name Module name * @param name Module name
*/ */
Trace(sc_core::sc_module_name const &name); explicit Trace(sc_core::sc_module_name const &name);
/** /**
* @brief Destructor * @brief Destructor
*/ */
~Trace(); ~Trace() override;
private: private:
@ -51,11 +51,11 @@ private:
void xtermLaunch(char *slaveName) const; void xtermLaunch(char *slaveName) const;
void xtermKill(const char *mess); void xtermKill(const char *mess);
void xtermSetup(void); void xtermSetup();
int ptSlave; int ptSlave{};
int ptMaster; int ptMaster{};
int xtermPid; int xtermPid{};
}; };
#endif #endif

2
src/A_extension.cpp
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@ -94,7 +94,7 @@ bool A_extension::Exec_A_SC() {
mem_addr = regs->getValue(rs1); mem_addr = regs->getValue(rs1);
data = regs->getValue(rs2); data = regs->getValue(rs2);
if (TLB_reserved(mem_addr) == true) { if (TLB_reserved(mem_addr)) {
mem_intf->writeDataMem(mem_addr, data, 4); mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite(); perf->dataMemoryWrite();
regs->setValue(rd, 0); // SC writes 0 to rd on success regs->setValue(rd, 0); // SC writes 0 to rd on success

10
src/CPU.cpp
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@ -113,7 +113,7 @@ bool CPU::cpu_process_IRQ() {
return ret_value; return ret_value;
} }
bool CPU::CPU_step(void) { bool CPU::CPU_step() {
bool incPCby2 = false; bool incPCby2 = false;
bool PC_not_affected = false; bool PC_not_affected = false;
@ -186,11 +186,11 @@ bool CPU::CPU_step(void) {
return breakpoint; return breakpoint;
} }
void CPU::CPU_thread(void) { [[noreturn]] void CPU::CPU_thread() {
sc_core::sc_time instr_time = default_time; sc_core::sc_time instr_time = default_time;
while (1) { while (true) {
/* Process one instruction */ /* Process one instruction */
CPU_step(); CPU_step();
@ -212,11 +212,11 @@ void CPU::CPU_thread(void) {
} // while(1) } // while(1)
} // CPU_thread } // CPU_thread
void CPU::call_interrupt(tlm::tlm_generic_payload &trans, void CPU::call_interrupt(tlm::tlm_generic_payload &m_trans,
sc_core::sc_time &delay) { sc_core::sc_time &delay) {
interrupt = true; interrupt = true;
/* Socket caller send a cause (its id) */ /* Socket caller send a cause (its id) */
memcpy(&int_cause, trans.get_data_ptr(), sizeof(uint32_t)); memcpy(&int_cause, m_trans.get_data_ptr(), sizeof(uint32_t));
delay = sc_core::SC_ZERO_TIME; delay = sc_core::SC_ZERO_TIME;
} }

1
src/Memory.cpp
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@ -20,6 +20,7 @@ Memory::Memory(sc_core::sc_module_name const &name, std::string const &filename)
//memset(mem, 0, SIZE*sizeof(uint8_t)); //memset(mem, 0, SIZE*sizeof(uint8_t));
memory_offset = 0; memory_offset = 0;
program_counter = 0;
readHexFile(filename); readHexFile(filename);
log = Log::getInstance(); log = Log::getInstance();

2
src/Registers.cpp
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@ -21,7 +21,7 @@ Registers::Registers() {
register_PC = 0x80000000; // default _start address register_PC = 0x80000000; // default _start address
} }
void Registers::dump(void) { void Registers::dump() {
std::cout << "************************************" << std::endl; std::cout << "************************************" << std::endl;
std::cout << "Registers dump" << std::dec << std::endl; std::cout << "Registers dump" << std::dec << std::endl;
std::cout << "x0 (zero): " << std::right << std::setw(11) std::cout << "x0 (zero): " << std::right << std::setw(11)

6
src/Timer.cpp
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@ -17,16 +17,16 @@ Timer::Timer(sc_core::sc_module_name const &name) :
SC_THREAD(run); SC_THREAD(run);
} }
void Timer::run() { [[noreturn]] void Timer::run() {
tlm::tlm_generic_payload *irq_trans = new tlm::tlm_generic_payload; auto *irq_trans = new tlm::tlm_generic_payload;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME; sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
uint32_t cause = 1 << 31 | 0x07; // Machine timer interrupt uint32_t cause = 1 << 31 | 0x07; // Machine timer interrupt
irq_trans->set_command(tlm::TLM_WRITE_COMMAND); irq_trans->set_command(tlm::TLM_WRITE_COMMAND);
irq_trans->set_data_ptr(reinterpret_cast<unsigned char*>(&cause)); irq_trans->set_data_ptr(reinterpret_cast<unsigned char*>(&cause));
irq_trans->set_data_length(4); irq_trans->set_data_length(4);
irq_trans->set_streaming_width(4); irq_trans->set_streaming_width(4);
irq_trans->set_byte_enable_ptr(0); irq_trans->set_byte_enable_ptr(nullptr);
irq_trans->set_dmi_allowed(false); irq_trans->set_dmi_allowed(false);
irq_trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); irq_trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
irq_trans->set_address(0); irq_trans->set_address(0);

2
src/Trace.cpp
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@ -64,7 +64,7 @@ void Trace::xtermKill(const char *mess) {
} }
void Trace::xtermSetup(void) { void Trace::xtermSetup() {
ptMaster = open("/dev/ptmx", O_RDWR); ptMaster = open("/dev/ptmx", O_RDWR);
if (ptMaster != -1) { if (ptMaster != -1) {