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risc-v-tlm
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added PC control

This commit is contained in:
mariusmonton 2018-09-21 09:24:25 +02:00
parent 981b84a5eb
commit 406d498209
1 changed files with 15 additions and 2 deletions
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15
src/CPU.cpp
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@ -17,7 +17,7 @@ CPU::CPU(sc_module_name name, uint32_t PC): sc_module(name)
CPU::~CPU() { CPU::~CPU() {
cout << "*********************************************" << endl; cout << "*********************************************" << endl;
register_bank->dump(); register_bank->dump();
cout << sc_time_stamp() << endl; cout << "end time: " << sc_time_stamp() << endl;
perf->dump(); perf->dump();
cout << "*********************************************" << endl; cout << "*********************************************" << endl;
} }
@ -31,6 +31,7 @@ void CPU::CPU_thread(void) {
tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
int32_t INSTR; int32_t INSTR;
sc_time delay = SC_ZERO_TIME; sc_time delay = SC_ZERO_TIME;
bool PC_not_affected = true;
trans->set_command( tlm::TLM_READ_COMMAND ); trans->set_command( tlm::TLM_READ_COMMAND );
trans->set_data_ptr( reinterpret_cast<unsigned char*>(&INSTR) ); trans->set_data_ptr( reinterpret_cast<unsigned char*>(&INSTR) );
@ -46,6 +47,7 @@ void CPU::CPU_thread(void) {
/* Get new PC value */ /* Get new PC value */
trans->set_address( register_bank->getPC() ); trans->set_address( register_bank->getPC() );
instr_bus->b_transport( *trans, delay); instr_bus->b_transport( *trans, delay);
perf->codeMemoryRead(); perf->codeMemoryRead();
if ( trans->is_response_error() ) { if ( trans->is_response_error() ) {
@ -55,6 +57,7 @@ void CPU::CPU_thread(void) {
<< dec << endl; << dec << endl;
Instruction inst(INSTR); Instruction inst(INSTR);
PC_not_affected = true;
switch(inst.decode()) { switch(inst.decode()) {
case OP_LUI: case OP_LUI:
exec->LUI(inst); exec->LUI(inst);
@ -64,27 +67,35 @@ void CPU::CPU_thread(void) {
break; break;
case OP_JAL: case OP_JAL:
exec->JAL(inst); exec->JAL(inst);
PC_not_affected = false;
break; break;
case OP_JALR: case OP_JALR:
exec->JALR(inst); exec->JALR(inst);
PC_not_affected = false;
break; break;
case OP_BEQ: case OP_BEQ:
exec->BEQ(inst); exec->BEQ(inst);
PC_not_affected = false;
break; break;
case OP_BNE: case OP_BNE:
exec->BNE(inst); exec->BNE(inst);
PC_not_affected = false;
break; break;
case OP_BLT: case OP_BLT:
exec->BLT(inst); exec->BLT(inst);
PC_not_affected = false;
break; break;
case OP_BGE: case OP_BGE:
exec->BGE(inst); exec->BGE(inst);
PC_not_affected = false;
break; break;
case OP_BLTU: case OP_BLTU:
exec->BLTU(inst); exec->BLTU(inst);
PC_not_affected = false;
break; break;
case OP_BGEU: case OP_BGEU:
exec->BGEU(inst); exec->BGEU(inst);
PC_not_affected = false;
break; break;
case OP_LB: case OP_LB:
exec->LB(inst); exec->LB(inst);
@ -185,7 +196,9 @@ void CPU::CPU_thread(void) {
} }
perf->instructionsInc(); perf->instructionsInc();
if (PC_not_affected == true) {
register_bank->incPC(); register_bank->incPC();
} }
}
} // while(1) } // while(1)
} // CPU_thread } // CPU_thread