diff --git a/.travis.yml b/.travis.yml
index 7ddc7bb..110f4c0 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -13,7 +13,7 @@ before_install:
  
 install:
  - cd ..
- - wget http://www.accellera.org/images/downloads/standards/systemc/systemc-2.3.2.tar.gz
+ - wget --no-check-certificate http://www.accellera.org/images/downloads/standards/systemc/systemc-2.3.2.tar.gz
  - tar xfvz systemc-2.3.2.tar.gz
  - cd systemc-2.3.2
  - mkdir build && cd build
diff --git a/README.md b/README.md
index 8e5a161..17915e5 100644
--- a/README.md
+++ b/README.md
@@ -6,7 +6,7 @@
 This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2.
 It supports RV32IMAC Instruction set by now.
 
-[![travis](https://travis-ci.org/mariusmm/RISC-V-TLM.svg?branch=master)](https://travis-ci.org/mariusmm/RISC-V-TLM)
+[![travis](https://api.travis-ci.com/mariusmm/RISC-V-TLM.svg?branch=master)](https://app.travis-ci.com/github/mariusmm/RISC-V-TLM)
 [![Codacy Badge](https://api.codacy.com/project/badge/Grade/0f7ccc8435f14ce2b241b3bfead772a2)](https://www.codacy.com/app/mariusmm/RISC-V-TLM?utm_source=github.com&utm_medium=referral&utm_content=mariusmm/RISC-V-TLM&utm_campaign=Badge_Grade)
 [![Coverity Scan Build Status](https://img.shields.io/coverity/scan/18772.svg)](https://scan.coverity.com/projects/mariusmm-risc-v-tlm)
 [![license](https://img.shields.io/badge/license-GNU--3.0-green.svg)](https://github.com/mariusmm/RISC-V-TLM/blob/master/LICENSE)