From 492cfd61e955cd00e13a206842be3456fbe260fb Mon Sep 17 00:00:00 2001 From: mariusmonton Date: Tue, 12 Feb 2019 11:39:15 +0100 Subject: [PATCH] better extension enumeration --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index e2b5fe8..d88ac0a 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2. -It supports RV32IMCA Instruction set by now. +It supports RV32IMAC Instruction set by now. [![travis](https://travis-ci.org/mariusmm/RISC-V-TLM.svg?branch=master)](https://travis-ci.org/mariusmm/RISC-V-TLM) [![Codacy Badge](https://api.codacy.com/project/badge/Grade/0f7ccc8435f14ce2b241b3bfead772a2)](https://www.codacy.com/app/mariusmm/RISC-V-TLM?utm_source=github.com&utm_medium=referral&utm_content=mariusmm/RISC-V-TLM&utm_campaign=Badge_Grade)