diff --git a/.gitignore b/.gitignore
index 28a298b..8813ba2 100644
--- a/.gitignore
+++ b/.gitignore
@@ -33,3 +33,5 @@
 
 Log.txt
 helper.ods
+*.swp
+RISCV_TLM
diff --git a/README.md b/README.md
index 500bbad..de15247 100644
--- a/README.md
+++ b/README.md
@@ -11,6 +11,7 @@ Brief description of the modules:
 * Registers: Implements the register file and PC
 * RISC_V_execute: Executes every ISA instruction
 * Instruction: Decodes instruction and acces to any instruction field
+* Simulation: Top-level entity that builds & starts the simulation
 
 Current performance is about 166000 instructions / sec in a Core-i5@2.2Ghz