fixed module name
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@ -16,7 +16,7 @@ Brief description of the modules:
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* CPU: Top entity that includes all other modules.
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* CPU: Top entity that includes all other modules.
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* Memory: Memory highly based on TLM-2 example with read file capability
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* Memory: Memory highly based on TLM-2 example with read file capability
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* Registers: Implements the register file, PC register & CSR registers
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* Registers: Implements the register file, PC register & CSR registers
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* RISC_V_execute: Executes ISA instructions
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* Execute: Executes ISA instructions
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* Instruction: Decodes instruction and acces to any instruction field
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* Instruction: Decodes instruction and acces to any instruction field
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* Simulator: Top-level entity that builds & starts the simulation
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* Simulator: Top-level entity that builds & starts the simulation
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* BusCtrl: Simple bus manager
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* BusCtrl: Simple bus manager
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@ -30,6 +30,7 @@ Current performance is about 284500 instructions / sec in a Core-i5@2.2Ghz
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### Structure
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### Structure
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![Modules' hierarchy](https://github.com/mariusmm/RISC-V-TLM/blob/master/doc/Hierarchy.png)
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@ -37,7 +38,7 @@ Current performance is about 284500 instructions / sec in a Core-i5@2.2Ghz
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This is a preliminar and incomplete version.
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This is a preliminar and incomplete version.
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Task to do:
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Task to do:
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* Implement all missing instructions (RISC_V_execute)
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* Implement all missing instructions (Execute)
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* Implement CSRs (where?)
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* Implement CSRs (where?)
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* Add full support to .elf ~~and .hex~~ filetypes to memory.h
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* Add full support to .elf ~~and .hex~~ filetypes to memory.h
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(only partial .hex support)
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(only partial .hex support)
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@ -69,6 +70,8 @@ $ ./RISCV_TLM asm/BasicLoop.hex
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```
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```
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## Test
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## Test
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See [Test page](Test) for more information.
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In the asm directory there are some basic assembly examples.
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In the asm directory there are some basic assembly examples.
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I "compile" one file with the follwing command:
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I "compile" one file with the follwing command:
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