From 5c905cb5ca0db75bda36d86559ac1ce3919264ea Mon Sep 17 00:00:00 2001
From: mariusmonton <marius.monton@gmail.com>
Date: Wed, 12 Dec 2018 18:15:44 +0100
Subject: [PATCH] better MISA CSR register support

---
 inc/Registers.h   | 16 ++++++++++++----
 src/Registers.cpp | 12 +++++++++---
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/inc/Registers.h b/inc/Registers.h
index 2f07206..65c7b03 100644
--- a/inc/Registers.h
+++ b/inc/Registers.h
@@ -16,10 +16,12 @@
 #include "Performance.h"
 #include "Memory.h"
 
-#define WARL_M_EXTENSION (1 << 12)
-#define WARL_C_EXTENSION (1 << 2)
-#define WARL_I_BASE (1 << 8)
-#define WARL_MXL (1 << 30)
+#define MISA_A_EXTENSION (1 << 0)
+#define MISA_B_EXTENSION (1 << 1)
+#define MISA_C_EXTENSION (1 << 2)
+#define MISA_I_BASE (1 << 8)
+#define MISA_M_EXTENSION (1 << 12)
+#define MISA_MXL (1 << 30)
 
 
 #define CSR_MVENDORID (0xF11)
@@ -41,6 +43,12 @@
 #define CSR_MTVAL (0x343)
 #define CSR_MIP (0x344)
 
+#define CSR_SSCRATCH (0x140)
+#define CSR_SEPC (0x141)
+#define CSR_SCAUSE (0x142)
+#define CSR_STVAL (0x143)
+#define CSR_SIP (0x144)
+
 #define CSR_CYCLE (0xC00)
 #define CSR_TIME (0xC01)
 #define CSR_INSTRET (0xC02)
diff --git a/src/Registers.cpp b/src/Registers.cpp
index a9d5865..112e497 100644
--- a/src/Registers.cpp
+++ b/src/Registers.cpp
@@ -9,7 +9,7 @@ Registers::Registers() {
   initCSR();
   //register_bank[sp] = 1024-1;  // SP points to end of memory
   register_bank[sp] = Memory::SIZE-4;
-  register_PC = 0x10000;       // default _start address
+  register_PC = 0x80000000;       // default _start address
 }
 
 void Registers::dump(void) {
@@ -113,10 +113,16 @@ uint32_t Registers::getCSR(int csr) {
 
 
 void Registers::setCSR(int csr, uint32_t value) {
-  CSR[csr] = value;
+  /* @note rv32mi-p-ma_fetch tests doesn't allow MISA to writable,
+   * but Volume II: Privileged Architectura v1.10 says MISRA is writable (?)
+   */
+  if (csr != CSR_MISA) {
+    CSR[csr] = value;
+  }
 }
 
 void Registers::initCSR() {
-  CSR[CSR_MISA] = WARL_MXL | WARL_M_EXTENSION | WARL_C_EXTENSION | WARL_I_BASE;
+  CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
+        | MISA_A_EXTENSION | MISA_I_BASE;
 
 }