changed pointer by reference
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parent
f7c9f47c3f
commit
61be24e608
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@ -72,14 +72,13 @@ private:
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Registers *register_bank;
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Registers *register_bank;
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Performance *perf;
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Performance *perf;
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Log *log;
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Log *log;
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Instruction *inst;
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C_extension *c_inst;
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C_extension *c_inst;
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M_extension *m_inst;
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M_extension *m_inst;
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A_extension *a_inst;
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A_extension *a_inst;
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BASE_ISA *exec;
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BASE_ISA *exec;
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tlm_utils::tlm_quantumkeeper *m_qk;
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tlm_utils::tlm_quantumkeeper *m_qk;
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Instruction inst;
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bool interrupt;
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bool interrupt;
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std::uint32_t int_cause;
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std::uint32_t int_cause;
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bool irq_already_down;
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bool irq_already_down;
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14
src/CPU.cpp
14
src/CPU.cpp
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@ -9,7 +9,7 @@
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SC_HAS_PROCESS(CPU);
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SC_HAS_PROCESS(CPU);
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CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
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CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
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sc_module(name), instr_bus("instr_bus"), default_time(10,
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sc_module(name), instr_bus("instr_bus"), inst(0), default_time(10,
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sc_core::SC_NS), INSTR(0) {
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sc_core::SC_NS), INSTR(0) {
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register_bank = new Registers();
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register_bank = new Registers();
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mem_intf = new MemoryInterface();
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mem_intf = new MemoryInterface();
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@ -18,7 +18,7 @@ CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
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log = Log::getInstance();
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log = Log::getInstance();
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register_bank->setPC(PC);
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register_bank->setPC(PC);
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register_bank->setValue(Registers::sp, (0x10000000 / 4) - 1);
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register_bank->setValue(Registers::sp, (Memory::SIZE / 4) - 1);
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irq_line_socket.register_b_transport(this, &CPU::call_interrupt);
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irq_line_socket.register_b_transport(this, &CPU::call_interrupt);
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interrupt = false;
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interrupt = false;
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@ -30,7 +30,6 @@ CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
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instr_bus.register_invalidate_direct_mem_ptr(this,
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instr_bus.register_invalidate_direct_mem_ptr(this,
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&CPU::invalidate_direct_mem_ptr);
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&CPU::invalidate_direct_mem_ptr);
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inst = new Instruction(0);
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exec = new BASE_ISA(0, register_bank, mem_intf);
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exec = new BASE_ISA(0, register_bank, mem_intf);
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c_inst = new C_extension(0, register_bank, mem_intf);
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c_inst = new C_extension(0, register_bank, mem_intf);
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m_inst = new M_extension(0, register_bank, mem_intf);
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m_inst = new M_extension(0, register_bank, mem_intf);
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@ -55,7 +54,6 @@ CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
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CPU::~CPU() {
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CPU::~CPU() {
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delete register_bank;
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delete register_bank;
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delete mem_intf;
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delete mem_intf;
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delete inst;
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delete exec;
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delete exec;
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delete c_inst;
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delete c_inst;
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delete m_inst;
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delete m_inst;
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@ -119,7 +117,7 @@ bool CPU::CPU_step() {
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/* Get new PC value */
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/* Get new PC value */
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if (dmi_ptr_valid) {
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if (dmi_ptr_valid) {
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/* if memory_offset at Memory module is set, this won't work */
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/* if memory_offset at Memory module is set, this won't work */
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memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
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std::memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
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} else {
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} else {
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sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
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sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
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tlm::tlm_dmi dmi_data;
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tlm::tlm_dmi dmi_data;
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@ -143,11 +141,11 @@ bool CPU::CPU_step() {
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log->SC_log(Log::INFO) << "PC: 0x" << std::hex << register_bank->getPC()
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log->SC_log(Log::INFO) << "PC: 0x" << std::hex << register_bank->getPC()
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<< ". ";
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<< ". ";
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inst->setInstr(INSTR);
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inst.setInstr(INSTR);
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bool breakpoint = false;
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bool breakpoint = false;
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/* check what type of instruction is and execute it */
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/* check what type of instruction is and execute it */
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switch (inst->check_extension()) {
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switch (inst.check_extension()) {
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[[likely]] case BASE_EXTENSION:
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[[likely]] case BASE_EXTENSION:
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PC_not_affected = exec->process_instruction(inst, &breakpoint);
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PC_not_affected = exec->process_instruction(inst, &breakpoint);
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if (PC_not_affected) {
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if (PC_not_affected) {
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@ -174,7 +172,7 @@ bool CPU::CPU_step() {
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break;
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break;
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[[unlikely]] default:
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[[unlikely]] default:
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std::cout << "Extension not implemented yet" << std::endl;
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std::cout << "Extension not implemented yet" << std::endl;
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inst->dump();
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inst.dump();
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exec->NOP();
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exec->NOP();
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}
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}
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