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risc-v-tlm
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bug on SLLI

This commit is contained in:
mariusmonton 2018-11-22 12:39:16 +01:00
parent 0cd34f9f3b
commit 6726b59c3c
4 changed files with 9 additions and 4 deletions
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4
inc/Instruction.h
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@ -360,6 +360,10 @@ public:
m_instr.range(19,12) = aux.range(19,12);
}
inline int32_t get_shamt() {
return m_instr.range(25, 20);
}
inline int32_t get_csr() {
int32_t aux = 0;

2
inc/Registers.h
View File

@ -19,7 +19,7 @@
#define WARL_M_EXTENSION (1 << 12)
#define WARL_C_EXTENSION (1 << 2)
#define WARL_I_BASE (1 << 8)
#define WARL_MXL (1 << 29)
#define WARL_MXL (1 << 30)
#define CSR_MSTATUS (0x300)

5
src/Execute.cpp
View File

@ -542,10 +542,11 @@ void Execute::SLLI(Instruction &inst) {
rd = inst.get_rd();
rs1 = inst.get_rs1();
rs2 = inst.get_rs2();
rs2 = inst.get_shamt();
if (rs2 >= 0x20) {
// raise an exception, but how?
cout << "ILEGAL INSTRUCTION, shamt[5] != 0" << endl;
}
shift = rs2 & 0x1F;
@ -555,7 +556,7 @@ void Execute::SLLI(Instruction &inst) {
log->SC_log(Log::INFO) << "SLLI: x"
<< rs1 << " << " << shift << " -> x"
<< rd << endl;
<< rd << "(0x" << hex << calc << ")" << endl;
}
void Execute::SRLI(Instruction &inst) {

2
src/Registers.cpp
View File

@ -94,6 +94,6 @@ void Registers::setCSR(int csr, uint32_t value) {
}
void Registers::initCSR() {
CSR[0x301] = WARL_MXL | WARL_M_EXTENSION | WARL_C_EXTENSION | WARL_I_BASE;
CSR[CSR_MISA] = WARL_MXL | WARL_M_EXTENSION | WARL_C_EXTENSION | WARL_I_BASE;
}