colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

new log file, same performance

This commit is contained in:
Màrius Montón 2020-06-09 16:37:29 +02:00
parent 5ee634e4b4
commit 6ff0da0313
15 changed files with 289 additions and 352 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
inc/BusCtrl.h
View File

@ -83,7 +83,7 @@ public:
sc_core::sc_time &delay);
private:
Log *log;
// Log *log;
bool instr_direct_mem_ptr(tlm::tlm_generic_payload&,
tlm::tlm_dmi &dmi_data);

2
inc/CPU.h
View File

@ -65,7 +65,7 @@ public:
private:
Registers *register_bank;
Performance *perf;
Log *log;
// Log *log;
Instruction *inst;
C_extension *c_inst;
M_extension *m_inst;

225
inc/Log.h
View File

@ -1,72 +1,173 @@
/*!
\file Log.h
\brief Class to manage Log
\author Màrius Montón
\date Aug 2018
/**
* https://www.drdobbs.com/cpp/logging-in-c/201804215?pgno=2
*/
// SPDX-License-Identifier: GPL-3.0-or-later
#ifndef LOG_H
#define LOG_H
#ifndef __LOG_H__
#define __LOG_H__
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <string>
#include <fstream>
#include <sstream>
#include "systemc"
#include "tlm.h"
#include <string>
#include <stdio.h>
/**
* @brief Log management class
*
* Singleton class to be shared among all other classes
*/
class Log {
inline std::string NowTime();
enum TLogLevel {logERROR, logWARNING, logINFO, logDEBUG, logDEBUG1, logDEBUG2, logDEBUG3, logDEBUG4};
template <typename T>
class Log
{
public:
enum LogLevel {
ERROR = 0, DEBUG, WARNING, INFO
} currentLogLevel;
/**
* @brief Constructor
* @return pointer to Log class
*/
static Log* getInstance();
/**
* @brief method to log some string
* @param msg mesasge string
* @param level level of the log (LogLevel)
*/
void SC_log(std::string msg, enum LogLevel level);
/**
* @brief method to log some string
* @param level level of the log (LogLevel)
* @return streaming
*
* This function can be used in the following way:
* \code
* my_log->SC_log(Log::WARNING) << "some warning text"
* \endcode
*/
std::ofstream& SC_log(enum LogLevel level);
/**
* @brief Sets log level
* @param newLevel Level of the log
*/
void setLogLevel(enum LogLevel newLevel);
enum LogLevel getLogLevel();
Log();
virtual ~Log();
std::ostringstream& Get(TLogLevel level = logINFO);
public:
static TLogLevel& ReportingLevel();
static std::string ToString(TLogLevel level);
static TLogLevel FromString(const std::string& level);
protected:
std::ostringstream os;
private:
static Log *instance;
Log(const char *filename);
std::ofstream m_stream;
std::ofstream m_sink;
Log(const Log&);
Log& operator =(const Log&);
};
template <typename T>
Log<T>::Log()
{
}
template <typename T>
std::ostringstream& Log<T>::Get(TLogLevel level)
{
os << std::string(level > logDEBUG ? level - logDEBUG : 0, '\t');
return os;
}
template <typename T>
Log<T>::~Log()
{
T::Output(os.str());
}
template <typename T>
TLogLevel& Log<T>::ReportingLevel()
{
static TLogLevel reportingLevel = logDEBUG4;
return reportingLevel;
}
template <typename T>
std::string Log<T>::ToString(TLogLevel level)
{
static const char* const buffer[] = {"ERROR", "WARNING", "INFO", "DEBUG", "DEBUG1", "DEBUG2", "DEBUG3", "DEBUG4"};
return buffer[level];
}
template <typename T>
TLogLevel Log<T>::FromString(const std::string& level)
{
if (level == "DEBUG4")
return logDEBUG4;
if (level == "DEBUG3")
return logDEBUG3;
if (level == "DEBUG2")
return logDEBUG2;
if (level == "DEBUG1")
return logDEBUG1;
if (level == "DEBUG")
return logDEBUG;
if (level == "INFO")
return logINFO;
if (level == "WARNING")
return logWARNING;
if (level == "ERROR")
return logERROR;
Log<T>().Get(logWARNING) << "Unknown logging level '" << level << "'. Using INFO level as default.";
return logINFO;
}
class Output2FILE
{
public:
static FILE*& Stream();
static void Output(const std::string& msg);
};
inline FILE*& Output2FILE::Stream()
{
static FILE* pStream = stderr;
return pStream;
}
inline void Output2FILE::Output(const std::string& msg)
{
FILE* pStream = Stream();
if (!pStream)
return;
fprintf(pStream, "%s", msg.c_str());
fflush(pStream);
}
#if defined(WIN32) || defined(_WIN32) || defined(__WIN32__)
# if defined (BUILDING_FILELOG_DLL)
# define FILELOG_DECLSPEC __declspec (dllexport)
# elif defined (USING_FILELOG_DLL)
# define FILELOG_DECLSPEC __declspec (dllimport)
# else
# define FILELOG_DECLSPEC
# endif // BUILDING_DBSIMPLE_DLL
#else
# define FILELOG_DECLSPEC
#endif // _WIN32
class FILELOG_DECLSPEC FILELog : public Log<Output2FILE> {};
//typedef Log<Output2FILE> FILELog;
#ifndef FILELOG_MAX_LEVEL
#define FILELOG_MAX_LEVEL logDEBUG4
#endif
#define FILE_LOG(level) \
if (level > FILELOG_MAX_LEVEL) ;\
else if (level > FILELog::ReportingLevel() || !Output2FILE::Stream()) ; \
else FILELog().Get(level)
#if defined(WIN32) || defined(_WIN32) || defined(__WIN32__)
#include <windows.h>
inline std::string NowTime()
{
const int MAX_LEN = 200;
char buffer[MAX_LEN];
if (GetTimeFormatA(LOCALE_USER_DEFAULT, 0, 0,
"HH':'mm':'ss", buffer, MAX_LEN) == 0)
return "Error in NowTime()";
char result[100] = {0};
static DWORD first = GetTickCount();
std::sprintf(result, "%s.%03ld", buffer, (long)(GetTickCount() - first) % 1000);
return result;
}
#else
#include <sys/time.h>
inline std::string NowTime()
{
char buffer[11];
time_t t;
time(&t);
tm r = {0};
strftime(buffer, sizeof(buffer), "%X", localtime_r(&t, &r));
struct timeval tv;
gettimeofday(&tv, 0);
char result[100] = {0};
std::sprintf(result, "%s.%03ld", buffer, (long)tv.tv_usec / 1000);
return result;
}
#endif //WIN32
#endif //__LOG_H__

2
inc/Memory.h
View File

@ -71,7 +71,7 @@ private:
/**
* @brief Log class
*/
Log *log;
// Log *log;
/**
* @brief Program counter (PC) read from hex file

2
inc/extension_base.h
View File

@ -51,7 +51,7 @@ protected:
sc_dt::sc_uint<32> m_instr;
Registers *regs;
Performance *perf;
Log *log;
// Log *log;
MemoryInterface *mem_intf;
};

22
src/A_extension.cpp
View File

@ -75,7 +75,7 @@ bool A_extension::Exec_A_LR() {
TLB_reserve(mem_addr);
log->SC_log(Log::INFO) << std::dec << "LR.W: x" << rs1 << " (@0x"
FILE_LOG(logINFO) << std::dec << "LR.W: x" << rs1 << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
return true;
@ -100,7 +100,7 @@ bool A_extension::Exec_A_SC() {
regs->setValue(rd, 1); // SC writes nonzero on failure
}
log->SC_log(Log::INFO) << std::dec << "SC.W: (@0x" << std::hex << mem_addr
FILE_LOG(logINFO) << std::dec << "SC.W: (@0x" << std::hex << mem_addr
<< std::dec << ") <- x" << rs2 << std::hex << "(0x" << data << ")"
<< std::endl;
@ -130,7 +130,7 @@ bool A_extension::Exec_A_AMOSWAP() {
mem_intf->writeDataMem(mem_addr, aux, 4);
log->SC_log(Log::INFO) << std::dec << "AMOSWAP " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOSWAP " << std::endl;
return true;
}
@ -155,7 +155,7 @@ bool A_extension::Exec_A_AMOADD() {
mem_intf->writeDataMem(mem_addr, data, 4);
log->SC_log(Log::INFO) << std::dec << "AMOADD " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOADD " << std::endl;
return true;
}
@ -181,7 +181,7 @@ bool A_extension::Exec_A_AMOXOR() {
mem_intf->writeDataMem(mem_addr, data, 4);
log->SC_log(Log::INFO) << std::dec << "AMOXOR " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOXOR " << std::endl;
return true;
}
@ -206,7 +206,7 @@ bool A_extension::Exec_A_AMOAND() {
mem_intf->writeDataMem(mem_addr, data, 4);
log->SC_log(Log::INFO) << std::dec << "AMOAND " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOAND " << std::endl;
return true;
}
@ -232,7 +232,7 @@ bool A_extension::Exec_A_AMOOR() {
mem_intf->writeDataMem(mem_addr, data, 4);
log->SC_log(Log::INFO) << std::dec << "AMOOR " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOOR " << std::endl;
return true;
}
bool A_extension::Exec_A_AMOMIN() {
@ -260,7 +260,7 @@ bool A_extension::Exec_A_AMOMIN() {
mem_intf->writeDataMem(mem_addr, aux, 4);
log->SC_log(Log::INFO) << std::dec << "AMOMIN " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOMIN " << std::endl;
return true;
}
@ -289,7 +289,7 @@ bool A_extension::Exec_A_AMOMAX() {
mem_intf->writeDataMem(mem_addr, aux, 4);
log->SC_log(Log::INFO) << std::dec << "AMOMAX " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOMAX " << std::endl;
return true;
}
@ -318,7 +318,7 @@ bool A_extension::Exec_A_AMOMINU() {
mem_intf->writeDataMem(mem_addr, aux, 4);
log->SC_log(Log::INFO) << std::dec << "AMOMINU " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOMINU " << std::endl;
return true;
}
@ -347,7 +347,7 @@ bool A_extension::Exec_A_AMOMAXU() {
mem_intf->writeDataMem(mem_addr, aux, 4);
log->SC_log(Log::INFO) << std::dec << "AMOMAXU " << std::endl;
FILE_LOG(logINFO) << std::dec << "AMOMAXU " << std::endl;
return true;
}

180
src/BASE_ISA.cpp
View File

@ -90,10 +90,8 @@ bool BASE_ISA::Exec_LUI() {
imm = get_imm_U() << 12;
regs->setValue(rd, imm);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "LUI x" << std::dec << rd << " <- 0x" << std::hex
FILE_LOG(logINFO) << "LUI x" << std::dec << rd << " <- 0x" << std::hex
<< imm << std::endl;
}
return true;
}
@ -109,10 +107,8 @@ bool BASE_ISA::Exec_AUIPC() {
regs->setValue(rd, new_pc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "AUIPC x" << std::dec << rd << " <- 0x"
FILE_LOG(logINFO) << "AUIPC x" << std::dec << rd << " <- 0x"
<< std::hex << imm << " + PC (0x" << new_pc << ")" << std::endl;
}
return true;
}
@ -132,11 +128,9 @@ bool BASE_ISA::Exec_JAL() {
old_pc = old_pc + 4;
regs->setValue(rd, old_pc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "JAL: x" << std::dec << rd << " <- 0x" << std::hex
FILE_LOG(logINFO) << "JAL: x" << std::dec << rd << " <- 0x" << std::hex
<< old_pc << std::dec << ". PC + 0x" << std::hex << mem_addr
<< " -> PC (0x" << new_pc << ")" << std::endl;
}
return true;
}
@ -156,10 +150,9 @@ bool BASE_ISA::Exec_JALR() {
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
regs->setPC(new_pc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "JALR: x" << std::dec << rd << " <- 0x"
FILE_LOG(logINFO) << "JALR: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc + 4 << " PC <- 0x" << new_pc << std::endl;
}
return true;
}
@ -178,12 +171,11 @@ bool BASE_ISA::Exec_BEQ() {
new_pc = regs->getPC();
}
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "BEQ x" << std::dec << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << "BEQ x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") == x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << std::endl;
}
return true;
}
@ -207,12 +199,10 @@ bool BASE_ISA::Exec_BNE() {
new_pc = regs->getPC();
}
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "BNE: x" << std::dec << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << "BNE: x" << std::dec << rs1 << "(0x" << std::hex
<< val1 << ") == x" << std::dec << rs2 << "(0x" << std::hex << val2
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< std::endl;
}
return true;
}
@ -231,13 +221,11 @@ bool BASE_ISA::Exec_BLT() {
regs->incPC();
}
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "BLT x" << std::dec << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << "BLT x" << std::dec << rs1 << "(0x" << std::hex
<< (int32_t) regs->getValue(rs1) << ") < x" << std::dec << rs2
<< "(0x" << std::hex << (int32_t) regs->getValue(rs2)
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< std::endl;
}
return true;
}
@ -256,13 +244,11 @@ bool BASE_ISA::Exec_BGE() {
regs->incPC();
}
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "BGE x" << std::dec << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << "BGE x" << std::dec << rs1 << "(0x" << std::hex
<< (int32_t) regs->getValue(rs1) << ") > x" << std::dec << rs2
<< "(0x" << std::hex << (int32_t) regs->getValue(rs2)
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< std::endl;
}
return true;
}
@ -282,12 +268,10 @@ bool BASE_ISA::Exec_BLTU() {
new_pc = regs->getPC();
}
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "BLTU x" << std::dec << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << "BLTU x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") < x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << std::endl;
}
return true;
}
@ -306,12 +290,10 @@ bool BASE_ISA::Exec_BGEU() {
regs->incPC();
}
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "BGEU x" << std::dec << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << "BGEU x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") > x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << std::endl;
}
return true;
}
@ -330,10 +312,8 @@ bool BASE_ISA::Exec_LB() {
data = mem_intf->readDataMem(mem_addr, 1);
regs->setValue(rd, data);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "LB: x" << rs1 << " + " << imm << " (@0x"
FILE_LOG(logINFO) << "LB: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
}
return true;
}
@ -352,10 +332,8 @@ bool BASE_ISA::Exec_LH() {
data = mem_intf->readDataMem(mem_addr, 2);
regs->setValue(rd, data);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "LH: x" << rs1 << " + " << imm << " (@0x"
FILE_LOG(logINFO) << "LH: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
}
return true;
}
@ -374,12 +352,10 @@ bool BASE_ISA::Exec_LW() {
data = mem_intf->readDataMem(mem_addr, 4);
regs->setValue(rd, data);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "LW: x" << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << std::dec << "LW: x" << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + " << std::dec << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::hex
<< " (0x" << data << ")" << std::endl;
}
return true;
}
@ -397,10 +373,8 @@ bool BASE_ISA::Exec_LBU() {
data = mem_intf->readDataMem(mem_addr, 1);
regs->setValue(rd, data);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "LBU: x" << rs1 << " + " << imm << " (@0x"
FILE_LOG(logINFO) << "LBU: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
}
return true;
}
@ -418,11 +392,9 @@ bool BASE_ISA::Exec_LHU() {
data = mem_intf->readDataMem(mem_addr, 2);
regs->setValue(rd, data);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "LHU: x" << std::dec << rs1 << " + " << imm
FILE_LOG(logINFO) << "LHU: x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ") -> x" << rd
<< "(0x" << std::hex << data << ")" << std::endl;
}
return true;
}
@ -442,11 +414,9 @@ bool BASE_ISA::Exec_SB() {
mem_intf->writeDataMem(mem_addr, data, 1);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SB: x" << std::dec << rs2 << " -> x" << rs1
FILE_LOG(logINFO) << "SB: x" << std::dec << rs2 << " -> x" << rs1
<< " + 0x" << std::hex << imm << " (@0x" << std::hex << mem_addr
<< std::dec << ")" << std::endl;
}
return true;
}
@ -466,11 +436,9 @@ bool BASE_ISA::Exec_SH() {
mem_intf->writeDataMem(mem_addr, data, 2);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SH: x" << std::dec << rs2 << " -> x" << rs1
FILE_LOG(logINFO) << "SH: x" << std::dec << rs2 << " -> x" << rs1
<< " + 0x" << std::hex << imm << " (@0x" << std::hex << mem_addr
<< std::dec << ")" << std::endl;
}
return true;
}
@ -490,11 +458,9 @@ bool BASE_ISA::Exec_SW() {
mem_intf->writeDataMem(mem_addr, data, 4);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SW: x" << std::dec << rs2 << "(0x" << std::hex
FILE_LOG(logINFO) << "SW: x" << std::dec << rs2 << "(0x" << std::hex
<< data << ") -> x" << std::dec << rs1 << " + 0x" << std::hex << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << std::endl;
}
return true;
}
@ -510,11 +476,9 @@ bool BASE_ISA::Exec_ADDI() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "ADDI: x" << std::dec << rs1 << " + " << imm
FILE_LOG(logINFO) << "ADDI: x" << std::dec << rs1 << " + " << imm
<< " -> x" << std::dec << rd << "(0x" << std::hex << calc << ")"
<< std::endl;
}
return true;
}
@ -529,11 +493,11 @@ bool BASE_ISA::Exec_SLTI() {
if (regs->getValue(rs1) < imm) {
regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTI: x" << rs1 << " < " << imm << " => "
FILE_LOG(logINFO) << "SLTI: x" << rs1 << " < " << imm << " => "
<< "1 -> x" << rd << std::endl;
} else {
regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTI: x" << rs1 << " < " << imm << " => "
FILE_LOG(logINFO) << "SLTI: x" << rs1 << " < " << imm << " => "
<< "0 -> x" << rd << std::endl;
}
@ -550,11 +514,11 @@ bool BASE_ISA::Exec_SLTIU() {
if ((uint32_t) regs->getValue(rs1) < (uint32_t) imm) {
regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTIU: x" << rs1 << " < " << imm << " => "
FILE_LOG(logINFO) << "SLTIU: x" << rs1 << " < " << imm << " => "
<< "1 -> x" << rd << std::endl;
} else {
regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTIU: x" << rs1 << " < " << imm << " => "
FILE_LOG(logINFO) << "SLTIU: x" << rs1 << " < " << imm << " => "
<< "0 -> x" << rd << std::endl;
}
@ -573,10 +537,8 @@ bool BASE_ISA::Exec_XORI() {
calc = regs->getValue(rs1) ^ imm;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "XORI: x" << rs1 << " XOR " << imm << "-> x" << rd
FILE_LOG(logINFO) << "XORI: x" << rs1 << " XOR " << imm << "-> x" << rd
<< std::endl;
}
return true;
}
@ -593,10 +555,8 @@ bool BASE_ISA::Exec_ORI() {
calc = regs->getValue(rs1) | imm;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "ORI: x" << rs1 << " OR " << imm << "-> x" << rd
FILE_LOG(logINFO) << "ORI: x" << rs1 << " OR " << imm << "-> x" << rd
<< std::endl;
}
return true;
}
@ -615,11 +575,9 @@ bool BASE_ISA::Exec_ANDI() {
calc = aux & imm;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "ANDI: x" << rs1 << "(0x" << std::hex << aux
FILE_LOG(logINFO) << "ANDI: x" << rs1 << "(0x" << std::hex << aux
<< ") AND 0x" << imm << " -> x" << std::dec << rd << "(0x"
<< std::hex << calc << ")" << std::endl;
}
return true;
}
@ -645,10 +603,8 @@ bool BASE_ISA::Exec_SLLI() {
calc = ((uint32_t) regs->getValue(rs1)) << shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SLLI: x" << std::dec << rs1 << " << " << shift
FILE_LOG(logINFO) << "SLLI: x" << std::dec << rs1 << " << " << shift
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << std::endl;
}
return true;
}
@ -667,10 +623,8 @@ bool BASE_ISA::Exec_SRLI() {
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SRLI: x" << std::dec << rs1 << " >> " << shift
FILE_LOG(logINFO) << "SRLI: x" << std::dec << rs1 << " >> " << shift
<< " -> x" << rd << std::endl;
}
return true;
}
@ -689,10 +643,8 @@ bool BASE_ISA::Exec_SRAI() {
calc = regs->getValue(rs1) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SRAI: x" << std::dec << rs1 << " >> " << shift
FILE_LOG(logINFO) << "SRAI: x" << std::dec << rs1 << " >> " << shift
<< " -> x" << rd << std::endl;
}
return true;
}
@ -708,10 +660,8 @@ bool BASE_ISA::Exec_ADD() {
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "ADD: x" << std::dec << rs1 << " + x" << rs2
FILE_LOG(logINFO) << "ADD: x" << std::dec << rs1 << " + x" << rs2
<< " -> x" << rd << std::hex << "(0x" << calc << ")" << std::endl;
}
return true;
}
@ -726,10 +676,8 @@ bool BASE_ISA::Exec_SUB() {
calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SUB: x" << rs1 << " - x" << rs2 << " -> x" << rd
FILE_LOG(logINFO) << "SUB: x" << rs1 << " - x" << rs2 << " -> x" << rd
<< "(" << calc << ")" << std::endl;
}
return true;
}
@ -748,10 +696,8 @@ bool BASE_ISA::Exec_SLL() {
calc = ((uint32_t) regs->getValue(rs1)) << shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SLL: x" << rs1 << " << " << shift << " -> x"
FILE_LOG(logINFO) << "SLL: x" << rs1 << " << " << shift << " -> x"
<< rd << std::endl;
}
return true;
}
@ -765,11 +711,11 @@ bool BASE_ISA::Exec_SLT() {
if (regs->getValue(rs1) < regs->getValue(rs2)) {
regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLT: x" << rs1 << " < x" << rs2 << " => "
FILE_LOG(logINFO) << "SLT: x" << rs1 << " < x" << rs2 << " => "
<< "1 -> x" << rd << std::endl;
} else {
regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLT: x" << rs1 << " < x" << rs2 << " => "
FILE_LOG(logINFO) << "SLT: x" << rs1 << " < x" << rs2 << " => "
<< "0 -> x" << rd << std::endl;
}
@ -785,11 +731,11 @@ bool BASE_ISA::Exec_SLTU() {
if ((uint32_t) regs->getValue(rs1) < (uint32_t) regs->getValue(rs2)) {
regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTU: x" << rs1 << " < x" << rs2 << " => "
FILE_LOG(logINFO) << "SLTU: x" << rs1 << " < x" << rs2 << " => "
<< "1 -> x" << rd << std::endl;
} else {
regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTU: x" << rs1 << " < x" << rs2 << " => "
FILE_LOG(logINFO) << "SLTU: x" << rs1 << " < x" << rs2 << " => "
<< "0 -> x" << rd << std::endl;
}
@ -807,10 +753,8 @@ bool BASE_ISA::Exec_XOR() {
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "XOR: x" << rs1 << " XOR x" << rs2 << "-> x" << rd
FILE_LOG(logINFO) << "XOR: x" << rs1 << " XOR x" << rs2 << "-> x" << rd
<< std::endl;
}
return true;
}
@ -829,10 +773,8 @@ bool BASE_ISA::Exec_SRL() {
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SRL: x" << rs1 << " >> " << shift << " -> x"
FILE_LOG(logINFO) << "SRL: x" << rs1 << " >> " << shift << " -> x"
<< rd << std::endl;
}
return true;
}
@ -851,10 +793,8 @@ bool BASE_ISA::Exec_SRA() {
calc = regs->getValue(rs1) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "SRA: x" << rs1 << " >> " << shift << " -> x"
FILE_LOG(logINFO) << "SRA: x" << rs1 << " >> " << shift << " -> x"
<< rd << std::endl;
}
return true;
}
@ -870,10 +810,8 @@ bool BASE_ISA::Exec_OR() {
calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "OR: x" << rs1 << " OR x" << rs2 << "-> x" << rd
FILE_LOG(logINFO) << "OR: x" << rs1 << " OR x" << rs2 << "-> x" << rd
<< std::endl;
}
return true;
}
@ -889,23 +827,21 @@ bool BASE_ISA::Exec_AND() {
calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "AND: x" << rs1 << " AND x" << rs2 << "-> x" << rd
FILE_LOG(logINFO) << "AND: x" << rs1 << " AND x" << rs2 << "-> x" << rd
<< std::endl;
}
return true;
}
bool BASE_ISA::Exec_FENCE() {
log->SC_log(Log::INFO) << "FENCE" << std::endl;
FILE_LOG(logINFO) << "FENCE" << std::endl;
return true;
}
bool BASE_ISA::Exec_ECALL() {
log->SC_log(Log::INFO) << "ECALL" << std::endl;
FILE_LOG(logINFO) << "ECALL" << std::endl;
std::cout << std::endl << "ECALL Instruction called, stopping simulation"
<< std::endl;
regs->dump();
@ -925,7 +861,7 @@ bool BASE_ISA::Exec_ECALL() {
bool BASE_ISA::Exec_EBREAK() {
log->SC_log(Log::INFO) << "EBREAK" << std::endl;
FILE_LOG(logINFO) << "EBREAK" << std::endl;
std::cout << std::endl << "EBRAK Instruction called, dumping information"
<< std::endl;
regs->dump();
@ -955,7 +891,7 @@ bool BASE_ISA::Exec_CSRRW() {
aux = regs->getValue(rs1);
regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << std::hex << "CSRRW: CSR #" << csr << " -> x"
FILE_LOG(logINFO) << std::hex << "CSRRW: CSR #" << csr << " -> x"
<< std::dec << rd << ". x" << rs1 << "-> CSR #" << std::hex << csr
<< " (0x" << aux << ")" << std::endl;
@ -972,7 +908,7 @@ bool BASE_ISA::Exec_CSRRS() {
csr = get_csr();
if (rd == 0) {
log->SC_log(Log::INFO) << "CSRRS with rd1 == 0, doing nothing."
FILE_LOG(logINFO) << "CSRRS with rd1 == 0, doing nothing."
<< std::endl;
return false;
}
@ -986,7 +922,7 @@ bool BASE_ISA::Exec_CSRRS() {
aux2 = aux | bitmask;
regs->setCSR(csr, aux2);
log->SC_log(Log::INFO) << "CSRRS: CSR #" << csr << "(0x" << std::hex << aux
FILE_LOG(logINFO) << "CSRRS: CSR #" << csr << "(0x" << std::hex << aux
<< ") -> x" << std::dec << rd << ". x" << rs1 << " & CSR #" << csr
<< " <- 0x" << std::hex << aux2 << std::endl;
@ -1003,7 +939,7 @@ bool BASE_ISA::Exec_CSRRC() {
csr = get_csr();
if (rd == 0) {
log->SC_log(Log::INFO) << "CSRRC with rd1 == 0, doing nothing."
FILE_LOG(logINFO) << "CSRRC with rd1 == 0, doing nothing."
<< std::endl;
return true;
}
@ -1017,7 +953,7 @@ bool BASE_ISA::Exec_CSRRC() {
aux2 = aux & ~bitmask;
regs->setCSR(csr, aux2);
log->SC_log(Log::INFO) << "CSRRC: CSR #" << csr << "(0x" << std::hex << aux
FILE_LOG(logINFO) << "CSRRC: CSR #" << csr << "(0x" << std::hex << aux
<< ") -> x" << std::dec << rd << ". x" << rs1 << " & CSR #" << csr
<< " <- 0x" << std::hex << aux2 << std::endl;
@ -1041,7 +977,7 @@ bool BASE_ISA::Exec_CSRRWI() {
aux = rs1;
regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRWI: CSR #" << csr << " -> x" << rd << ". x"
FILE_LOG(logINFO) << "CSRRWI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << "-> CSR #" << csr << std::endl;
return true;
@ -1068,7 +1004,7 @@ bool BASE_ISA::Exec_CSRRSI() {
aux = aux | bitmask;
regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRSI: CSR #" << csr << " -> x" << rd << ". x"
FILE_LOG(logINFO) << "CSRRSI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << " & CSR #" << csr << "(0x" << std::hex << aux << ")"
<< std::endl;
@ -1096,7 +1032,7 @@ bool BASE_ISA::Exec_CSRRCI() {
aux = aux & ~bitmask;
regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRCI: CSR #" << csr << " -> x" << rd << ". x"
FILE_LOG(logINFO) << "CSRRCI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << " & CSR #" << csr << "(0x" << std::hex << aux << ")"
<< std::endl;
@ -1111,7 +1047,7 @@ bool BASE_ISA::Exec_MRET() {
new_pc = regs->getCSR(CSR_MEPC);
regs->setPC(new_pc);
log->SC_log(Log::INFO) << "MRET: PC <- 0x" << std::hex << new_pc
FILE_LOG(logINFO) << "MRET: PC <- 0x" << std::hex << new_pc
<< std::endl;
// update mstatus
@ -1132,20 +1068,20 @@ bool BASE_ISA::Exec_SRET() {
new_pc = regs->getCSR(CSR_SEPC);
regs->setPC(new_pc);
log->SC_log(Log::INFO) << "SRET: PC <- 0x" << std::hex << new_pc
FILE_LOG(logINFO) << "SRET: PC <- 0x" << std::hex << new_pc
<< std::endl;
return true;
}
bool BASE_ISA::Exec_WFI() {
log->SC_log(Log::INFO) << "WFI" << std::endl;
FILE_LOG(logINFO) << "WFI" << std::endl;
return true;
}
bool BASE_ISA::Exec_SFENCE() {
log->SC_log(Log::INFO) << "SFENCE" << std::endl;
FILE_LOG(logINFO) << "SFENCE" << std::endl;
return true;
}

2
src/BusCtrl.cpp
View File

@ -15,7 +15,7 @@ BusCtrl::BusCtrl(sc_core::sc_module_name name) :
"trace_socket") {
cpu_instr_socket.register_b_transport(this, &BusCtrl::b_transport);
cpu_data_socket.register_b_transport(this, &BusCtrl::b_transport);
log = Log::getInstance();
cpu_instr_socket.register_get_direct_mem_ptr(this,
&BusCtrl::instr_direct_mem_ptr);
memory_socket.register_invalidate_direct_mem_ptr(this,

11
src/CPU.cpp
View File

@ -16,7 +16,6 @@ CPU::CPU(sc_core::sc_module_name name, uint32_t PC) :
mem_intf = new MemoryInterface();
perf = Performance::getInstance();
log = Log::getInstance();
register_bank->setPC(PC);
@ -68,7 +67,7 @@ bool CPU::cpu_process_IRQ() {
if (interrupt == true) {
csr_temp = register_bank->getCSR(CSR_MSTATUS);
if ((csr_temp & MSTATUS_MIE) == 0) {
log->SC_log(Log::DEBUG) << "interrupt delayed" << std::endl;
FILE_LOG(logDEBUG) << "interrupt delayed" << std::endl;
return ret_value;
}
@ -77,12 +76,12 @@ bool CPU::cpu_process_IRQ() {
if ((csr_temp & MIP_MEIP) == 0) {
csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
register_bank->setCSR(CSR_MIP, csr_temp);
log->SC_log(Log::DEBUG) << "Interrupt!" << std::endl;
FILE_LOG(logDEBUG) << "Interrupt!" << std::endl;
/* updated MEPC register */
old_pc = register_bank->getPC();
register_bank->setCSR(CSR_MEPC, old_pc);
log->SC_log(Log::INFO) << "Old PC Value 0x" << std::hex << old_pc
FILE_LOG(logINFO) << "Old PC Value 0x" << std::hex << old_pc
<< std::endl;
/* update MCAUSE register */
@ -91,7 +90,7 @@ bool CPU::cpu_process_IRQ() {
/* set new PC address */
new_pc = register_bank->getCSR(CSR_MTVEC);
//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
log->SC_log(Log::DEBUG) << "NEW PC Value 0x" << std::hex << new_pc
FILE_LOG(logDEBUG) << "NEW PC Value 0x" << std::hex << new_pc
<< std::endl;
register_bank->setPC(new_pc);
@ -155,7 +154,7 @@ void CPU::CPU_thread(void) {
perf->codeMemoryRead();
log->SC_log(Log::INFO) << "PC: 0x" << std::hex << register_bank->getPC()
FILE_LOG(logINFO) << "PC: 0x" << std::hex << register_bank->getPC()
<< ". ";
inst->setInstr(INSTR);

94
src/C_extension.cpp
View File

@ -157,9 +157,7 @@ bool C_extension::Exec_C_JR() {
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
regs->setPC(new_pc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "JR: PC <- 0x" << std::hex << new_pc << std::endl;
}
FILE_LOG(logINFO) << "JR: PC <- 0x" << std::hex << new_pc << std::endl;
return true;
}
@ -175,12 +173,10 @@ bool C_extension::Exec_C_MV() {
calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.MV: x" << std::dec << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << "C.MV: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ") -> x" << std::dec << rd
<< "(0x" << std::hex << calc << ")" << std::endl;
}
return true;
}
@ -196,10 +192,8 @@ bool C_extension::Exec_C_ADD() {
calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.ADD: x" << std::dec << rs1 << " + x" << rs2
FILE_LOG(logINFO) << "C.ADD: x" << std::dec << rs1 << " + x" << rs2
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << std::endl;
}
return true;
}
@ -221,11 +215,9 @@ bool C_extension::Exec_C_LWSP() {
regs->setValue(rd, data);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.LWSP: x" << std::dec << rs1 << " + " << imm
FILE_LOG(logINFO) << "C.LWSP: x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ") -> x" << rd
<< "(" << std::hex << data << ")" << std::dec << std::endl;
}
return true;
}
@ -247,11 +239,9 @@ bool C_extension::Exec_C_ADDI4SPN() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "C.ADDI4SPN: x" << rs1 << "(0x"
FILE_LOG(logINFO) << std::dec << "C.ADDI4SPN: x" << rs1 << "(0x"
<< std::hex << regs->getValue(rs1) << ") + " << std::dec << imm
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << std::endl;
}
return true;
}
@ -270,7 +260,7 @@ bool C_extension::Exec_C_ADDI16SP() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
log->SC_log(Log::INFO) << std::dec << "C.ADDI16SP: x" << rs1 << " + "
FILE_LOG(logINFO) << std::dec << "C.ADDI16SP: x" << rs1 << " + "
<< std::dec << imm << " -> x" << rd << "(0x" << std::hex << calc
<< ")" << std::endl;
} else {
@ -278,7 +268,7 @@ bool C_extension::Exec_C_ADDI16SP() {
rd = get_rd();
imm = get_imm_LUI();
regs->setValue(rd, imm);
log->SC_log(Log::INFO) << std::dec << "C.LUI x" << rd << " <- 0x"
FILE_LOG(logINFO) << std::dec << "C.LUI x" << rd << " <- 0x"
<< std::hex << imm << std::endl;
}
@ -301,11 +291,9 @@ bool C_extension::Exec_C_SWSP() {
mem_intf->writeDataMem(mem_addr, data, 4);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "C.SWSP: x" << rs2 << "(0x"
FILE_LOG(logINFO) << std::dec << "C.SWSP: x" << rs2 << "(0x"
<< std::hex << data << ") -> x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << std::endl;
}
return true;
}
@ -326,11 +314,9 @@ bool C_extension::Exec_C_BEQZ() {
new_pc = regs->getPC();
}
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.BEQZ: x" << std::dec << rs1 << "(" << val1
FILE_LOG(logINFO) << "C.BEQZ: x" << std::dec << rs1 << "(" << val1
<< ") == 0? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< std::endl;
}
return true;
}
@ -351,11 +337,10 @@ bool C_extension::Exec_C_BNEZ() {
new_pc = regs->getPC();
}
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.BNEZ: x" << std::dec << rs1 << "(0x"
FILE_LOG(logINFO) << "C.BNEZ: x" << std::dec << rs1 << "(0x"
<< std::hex << val1 << ") != 0? -> PC (0x" << std::hex << new_pc
<< ")" << std::dec << std::endl;
}
return true;
}
@ -372,11 +357,9 @@ bool C_extension::Exec_C_LI() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "C.LI: x" << rs1 << "("
FILE_LOG(logINFO) << std::dec << "C.LI: x" << rs1 << "("
<< regs->getValue(rs1) << ") + " << imm << " -> x" << rd << "("
<< calc << ")" << std::endl;
}
return true;
}
@ -395,10 +378,8 @@ bool C_extension::Exec_C_SRLI() {
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.SRLI: x" << rs1 << " >> " << shift << " -> x"
FILE_LOG(logINFO) << "C.SRLI: x" << rs1 << " >> " << shift << " -> x"
<< rd << std::endl;
}
return true;
}
@ -417,10 +398,9 @@ bool C_extension::Exec_C_SRAI() {
calc = (int32_t) regs->getValue(rs1) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.SRAI: x" << rs1 << " >> " << std::dec << shift
FILE_LOG(logINFO) << "C.SRAI: x" << rs1 << " >> " << std::dec << shift
<< " -> x" << rd << "(" << calc << ")" << std::endl;
}
return true;
}
@ -439,10 +419,8 @@ bool C_extension::Exec_C_SLLI() {
calc = ((uint32_t) regs->getValue(rs1)) << shift;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.SLLI: x" << std::dec << rs1 << " << " << shift
FILE_LOG(logINFO) << "C.SLLI: x" << std::dec << rs1 << " << " << shift
<< " -> x" << rd << "(0x" << calc << ")" << std::endl;
}
return true;
}
@ -461,10 +439,8 @@ bool C_extension::Exec_C_ANDI() {
calc = aux & imm;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.ANDI: x" << rs1 << "(" << aux << ") AND "
FILE_LOG(logINFO) << "C.ANDI: x" << rs1 << "(" << aux << ") AND "
<< imm << " -> x" << rd << std::endl;
}
return true;
}
@ -480,10 +456,8 @@ bool C_extension::Exec_C_SUB() {
calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.SUB: x" << std::dec << rs1 << " - x" << rs2
FILE_LOG(logINFO) << "C.SUB: x" << std::dec << rs1 << " - x" << rs2
<< " -> x" << rd << std::endl;
}
return true;
}
@ -499,10 +473,8 @@ bool C_extension::Exec_C_XOR() {
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.XOR: x" << std::dec << rs1 << " XOR x" << rs2
FILE_LOG(logINFO) << "C.XOR: x" << std::dec << rs1 << " XOR x" << rs2
<< "-> x" << rd << std::endl;
}
return true;
}
@ -518,10 +490,8 @@ bool C_extension::Exec_C_OR() {
calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C_OR: x" << std::dec << rs1 << " OR x" << rs2
FILE_LOG(logINFO) << "C_OR: x" << std::dec << rs1 << " OR x" << rs2
<< "-> x" << rd << std::endl;
}
return true;
}
@ -537,10 +507,8 @@ bool C_extension::Exec_C_AND() {
calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.AND: x" << std::dec << rs1 << " AND x" << rs2
FILE_LOG(logINFO) << "C.AND: x" << std::dec << rs1 << " AND x" << rs2
<< "-> x" << rd << std::endl;
}
return true;
}
@ -557,11 +525,9 @@ bool C_extension::Exec_C_ADDI() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.ADDI: x" << std::dec << rs1 << " + " << imm
FILE_LOG(logINFO) << "C.ADDI: x" << std::dec << rs1 << " + " << imm
<< " -> x" << std::dec << rd << "(0x" << std::hex << calc << ")"
<< std::endl;
}
return true;
}
@ -580,11 +546,9 @@ bool C_extension::Exec_C_JALR() {
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
regs->setPC(new_pc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.JALR: x" << std::dec << rd << " <- 0x"
FILE_LOG(logINFO) << "C.JALR: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc + 4 << " PC <- 0x" << std::hex << new_pc
<< std::endl;
}
return true;
}
@ -603,12 +567,10 @@ bool C_extension::Exec_C_LW() {
data = mem_intf->readDataMem(mem_addr, 4);
regs->setValue(rd, data);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "C.LW: x" << rs1 << "(0x" << std::hex
FILE_LOG(logINFO) << std::dec << "C.LW: x" << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + " << std::dec << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::hex
<< " (0x" << data << ")" << std::endl;
}
return true;
}
@ -628,11 +590,9 @@ bool C_extension::Exec_C_SW() {
mem_intf->writeDataMem(mem_addr, data, 4);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.SW: x" << std::dec << rs2 << "(0x" << std::hex
FILE_LOG(logINFO) << "C.SW: x" << std::dec << rs2 << "(0x" << std::hex
<< data << ") -> x" << std::dec << rs1 << " + 0x" << std::hex << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << std::endl;
}
return true;
}
@ -652,11 +612,9 @@ bool C_extension::Exec_C_JAL(int m_rd) {
old_pc = old_pc + 2;
regs->setValue(rd, old_pc);
if (log->getLogLevel() > Log::INFO) {
log->SC_log(Log::INFO) << "C.JAL: x" << std::dec << rd << " <- 0x"
FILE_LOG(logINFO) << "C.JAL: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc << std::dec << ". PC + 0x" << std::hex
<< mem_addr << " -> PC (0x" << new_pc << ")" << std::endl;
}
return true;
}

52
src/Log.cpp
View File

@ -1,52 +0,0 @@
/*!
\file Log.cpp
\brief Class to manage Log
\author Màrius Montón
\date Aug 2018
*/
// SPDX-License-Identifier: GPL-3.0-or-later
#include "Log.h"
Log* Log::getInstance() {
if (instance == 0) {
instance = new Log("Log.txt");
}
return instance;
}
Log::Log(const char *filename) {
m_stream.open(filename);
currentLogLevel = Log::INFO;
}
void Log::SC_log(std::string msg, enum LogLevel level) {
if (level <= currentLogLevel) {
m_stream << "time " << sc_core::sc_time_stamp() << ": " << msg
<< std::endl;
}
}
std::ofstream& Log::SC_log(enum LogLevel level) {
if (level <= currentLogLevel) {
m_stream << "time " << sc_core::sc_time_stamp() << ": ";
return m_stream;
} else {
return m_sink;
}
}
void Log::setLogLevel(enum LogLevel newLevel) {
std::cout << "LogLevel set to " << newLevel << std::endl;
currentLogLevel = newLevel;
}
enum Log::LogLevel Log::getLogLevel() {
return currentLogLevel;
}
Log *Log::instance = 0;

16
src/M_extension.cpp
View File

@ -59,7 +59,7 @@ bool M_extension::Exec_M_MUL() {
result = result & 0x00000000FFFFFFFF;
regs->setValue(rd, result);
log->SC_log(Log::INFO) << std::dec << "MUL: x" << rs1 << " * x" << rs2
FILE_LOG(logDEBUG) << std::dec << "MUL: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
return true;
@ -83,7 +83,7 @@ bool M_extension::Exec_M_MULH() {
ret_value = (int32_t) ((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value);
log->SC_log(Log::INFO) << std::dec << "MULH: x" << rs1 << " * x" << rs2
FILE_LOG(logDEBUG) << std::dec << "MULH: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
return true;
@ -106,7 +106,7 @@ bool M_extension::Exec_M_MULHSU() {
result = (result >> 32) & 0x00000000FFFFFFFF;
regs->setValue(rd, result);
log->SC_log(Log::INFO) << std::dec << "MULHSU: x" << rs1 << " * x" << rs2
FILE_LOG(logDEBUG) << std::dec << "MULHSU: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
return true;
@ -129,7 +129,7 @@ bool M_extension::Exec_M_MULHU() {
ret_value = (uint32_t) (result >> 32) & 0x00000000FFFFFFFF;
regs->setValue(rd, ret_value);
log->SC_log(Log::INFO) << std::dec << "MULHU: x" << rs1 << " * x" << rs2
FILE_LOG(logDEBUG) << std::dec << "MULHU: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << ret_value << ")" << std::endl;
return true;
@ -158,7 +158,7 @@ bool M_extension::Exec_M_DIV() {
regs->setValue(rd, result);
log->SC_log(Log::INFO) << std::dec << "DIV: x" << rs1 << " / x" << rs2
FILE_LOG(logDEBUG) << std::dec << "DIV: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
return true;
@ -185,7 +185,7 @@ bool M_extension::Exec_M_DIVU() {
regs->setValue(rd, result);
log->SC_log(Log::INFO) << std::dec << "DIVU: x" << rs1 << " / x" << rs2
FILE_LOG(logDEBUG) << std::dec << "DIVU: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
return true;
@ -213,7 +213,7 @@ bool M_extension::Exec_M_REM() {
regs->setValue(rd, result);
log->SC_log(Log::INFO) << std::dec << "REM: x" << rs1 << " / x" << rs2
FILE_LOG(logDEBUG) << std::dec << "REM: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
return true;
@ -239,7 +239,7 @@ bool M_extension::Exec_M_REMU() {
regs->setValue(rd, result);
log->SC_log(Log::INFO) << std::dec << "REMU: x" << rs1 << " / x" << rs2
FILE_LOG(logDEBUG) << std::dec << "REMU: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
return true;

6
src/Memory.cpp
View File

@ -22,8 +22,7 @@ Memory::Memory(sc_core::sc_module_name name, std::string filename) :
memory_offset = 0;
readHexFile(filename);
log = Log::getInstance();
log->SC_log(Log::INFO) << "Using file: " << filename << std::endl;
FILE_LOG(logINFO) << "Using file: " << filename << std::endl;
}
Memory::Memory(sc_core::sc_module_name name, bool use_file) :
@ -36,8 +35,7 @@ Memory::Memory(sc_core::sc_module_name name, bool use_file) :
mem = new uint8_t[SIZE];
log = Log::getInstance();
log->SC_log(Log::INFO) << "Memory instantiated wihtout file" << std::endl;
FILE_LOG(logINFO) << "Memory instantiated wihtout file" << std::endl;
}
Memory::~Memory() {

14
src/Simulator.cpp
View File

@ -82,10 +82,8 @@ void process_arguments(int argc, char *argv[]) {
int c;
int debug_level;
Log *log;
log = Log::getInstance();
log->setLogLevel(Log::ERROR);
//log->setLogLevel(Log::ERROR);
while ((c = getopt(argc, argv, "D:f:?")) != -1) {
switch (c) {
case 'D':
@ -93,19 +91,19 @@ void process_arguments(int argc, char *argv[]) {
switch (debug_level) {
case 3:
log->setLogLevel(Log::INFO);
// log->setLogLevel(Log::INFO);
break;
case 2:
log->setLogLevel(Log::WARNING);
// log->setLogLevel(Log::WARNING);
break;
case 1:
log->setLogLevel(Log::DEBUG);
// log->setLogLevel(Log::DEBUG);
break;
case 0:
log->setLogLevel(Log::ERROR);
// log->setLogLevel(Log::ERROR);
break;
default:
log->setLogLevel(Log::INFO);
// log->setLogLevel(Log::INFO);
break;
}
break;

3
src/extension_base.cpp
View File

@ -13,7 +13,6 @@ extension_base::extension_base(sc_dt::sc_uint<32> instr,
m_instr(instr), regs(register_bank), mem_intf(mem_interface) {
perf = Performance::getInstance();
log = Log::getInstance();
}
extension_base::~extension_base() {
@ -49,7 +48,7 @@ void extension_base::RaiseException(uint32_t cause, uint32_t inst) {
regs->setPC(new_pc);
log->SC_log(Log::ERROR) << "Exception! new PC 0x" << std::hex << new_pc
FILE_LOG(logERROR) << "Exception! new PC 0x" << std::hex << new_pc
<< std::endl;
regs->dump();