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merge with log branch. New log mechanism

This commit is contained in:
Màrius Montón 2021-11-25 13:01:23 +01:00
parent 2c4de6a427 e6bf4e30a4
commit 724cf258ce
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GPG Key ID: FA199E7A752699F0
20 changed files with 249 additions and 527 deletions
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1
inc/A_extension.h
View File

@ -13,7 +13,6 @@
#include <unordered_set>
#include "Log.h"
#include "Registers.h"
#include "MemoryInterface.h"
#include "extension_base.h"

2
inc/BASE_ISA.h
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@ -22,8 +22,6 @@
#include "M_extension.h"
#include "A_extension.h"
#include "Registers.h"
#include "Log.h"
typedef enum {
OP_LUI,

5
inc/BusCtrl.h
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@ -20,8 +20,6 @@
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "Log.h"
/**
* Memory mapped Trace peripheral address
*/
@ -85,12 +83,9 @@ public:
sc_core::sc_time &delay);
private:
bool instr_direct_mem_ptr(tlm::tlm_generic_payload&,
tlm::tlm_dmi &dmi_data);
void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
Log *log;
};
#endif

3
inc/CPU.h
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@ -21,7 +21,6 @@
#include "MemoryInterface.h"
#include "BASE_ISA.h"
#include "Registers.h"
#include "Log.h"
#include "Instruction.h"
#include "C_extension.h"
#include "M_extension.h"
@ -71,7 +70,7 @@ public:
private:
Registers *register_bank;
Performance *perf;
Log *log;
std::shared_ptr<spdlog::logger> logger;
C_extension *c_inst;
M_extension *m_inst;
A_extension *a_inst;

76
inc/Log.h
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@ -1,76 +0,0 @@
/*!
\file Log.h
\brief Class to manage Log
\author Màrius Montón
\date Aug 2018
*/
// SPDX-License-Identifier: GPL-3.0-or-later
#ifndef LOG_H
#define LOG_H
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <string>
#include <fstream>
#include <sstream>
#include "systemc"
#include "tlm.h"
/**
* @brief Log management class
*
* Singleton class to be shared among all other classes
*/
class Log {
public:
enum LogLevel {
ERROR = 0, DEBUG, WARNING, INFO
} currentLogLevel;
/**
* @brief Constructor
* @return pointer to Log class
*/
static Log* getInstance();
/**
* @brief method to log some string
* @param msg mesasge string
* @param level level of the log (LogLevel)
*/
void SC_log(const std::string& msg, enum LogLevel level);
/**
* @brief method to log some string
* @param level level of the log (LogLevel)
* @return streaming
*
* This function can be used in the following way:
* \code
* my_log->SC_log(Log::WARNING) << "some warning text"
* \endcode
*/
std::ofstream& SC_log(enum LogLevel level);
/**
* @brief Sets log level
* @param newLevel Level of the log
*/
void setLogLevel(enum LogLevel newLevel);
/**
* @brief Returns log level
* @return Current log level
*/
enum LogLevel getLogLevel() const;
private:
static Log *instance;
explicit Log(const char *filename);
std::ofstream m_stream;
std::ofstream m_sink;
};
#endif

1
inc/M_extension.h
View File

@ -12,7 +12,6 @@
#include "systemc"
#include "extension_base.h"
#include "Log.h"
#include "Registers.h"
typedef enum {

6
inc/Memory.h
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@ -19,8 +19,8 @@
#include "tlm.h"
#include "tlm_utils/simple_target_socket.h"
#include "Log.h"
#include "spdlog/spdlog.h"
#include "spdlog/sinks/basic_file_sink.h"
/**
* @brief Basic TLM-2 memory
*/
@ -71,7 +71,7 @@ private:
/**
* @brief Log class
*/
Log *log;
std::shared_ptr<spdlog::logger> logger;
/**
* @brief Program counter (PC) read from hex file

1
inc/MemoryInterface.h
View File

@ -16,7 +16,6 @@
#include "tlm_utils/tlm_quantumkeeper.h"
#include "memory.h"
#include "Log.h"
/**
* @brief Memory Interface

6
inc/extension_base.h
View File

@ -13,9 +13,11 @@
#include "Instruction.h"
#include "Registers.h"
#include "Log.h"
#include "MemoryInterface.h"
#include "spdlog/spdlog.h"
#include "spdlog/sinks/basic_file_sink.h"
#define EXCEPTION_CAUSE_INSTRUCTION_MISALIGN 0
#define EXCEPTION_CAUSE_INSTRUCTION_ACCESS 1
#define EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION 2
@ -76,8 +78,8 @@ protected:
sc_dt::sc_uint<32> m_instr;
Registers *regs;
Performance *perf;
Log *log;
MemoryInterface *mem_intf;
std::shared_ptr<spdlog::logger> logger;
};
#endif /* INC_EXTENSION_BASE_H_ */

29
src/A_extension.cpp
View File

@ -76,8 +76,8 @@ bool A_extension::Exec_A_LR() {
TLB_reserve(mem_addr);
log->SC_log(Log::INFO) << std::dec << "LR.W: x" << rs1 << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.LR.W: x{:d}(0x{:x}) -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, mem_addr, rd, data);
return true;
}
@ -102,9 +102,8 @@ bool A_extension::Exec_A_SC() {
regs->setValue(rd, 1); // SC writes nonzero on failure
}
log->SC_log(Log::INFO) << std::dec << "SC.W: (@0x" << std::hex << mem_addr
<< std::dec << ") <- x" << rs2 << std::hex << "(0x" << data << ")"
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.SC.W: (0x{:x}) <- x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(),
mem_addr, rs2, data);
return true;
}
@ -133,7 +132,8 @@ bool A_extension::Exec_A_AMOSWAP() const {
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOSWAP " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOSWAP");
return true;
}
@ -160,7 +160,7 @@ bool A_extension::Exec_A_AMOADD() const {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOADD " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOADD");
return true;
}
@ -188,7 +188,7 @@ bool A_extension::Exec_A_AMOXOR() const {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOXOR " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOXOR");
return true;
}
@ -215,7 +215,7 @@ bool A_extension::Exec_A_AMOAND() const {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOAND " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOAND");
return true;
}
@ -243,7 +243,8 @@ bool A_extension::Exec_A_AMOOR() const {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOOR " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOOR");
return true;
}
@ -274,7 +275,7 @@ bool A_extension::Exec_A_AMOMIN() const {
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOMIN " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOMIN");
return true;
}
@ -305,7 +306,7 @@ bool A_extension::Exec_A_AMOMAX() const {
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOMAX " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOMAX");
return true;
}
@ -336,7 +337,7 @@ bool A_extension::Exec_A_AMOMINU() const {
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOMINU " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOMINU");
return true;
}
@ -367,7 +368,7 @@ bool A_extension::Exec_A_AMOMAXU() const {
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
log->SC_log(Log::INFO) << std::dec << "AMOMAXU " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOMAXU");
return true;
}

333
src/BASE_ISA.cpp
View File

@ -6,6 +6,9 @@
*/
// SPDX-License-Identifier: GPL-3.0-or-later
#include "spdlog/spdlog.h"
#include "BASE_ISA.h"
enum Codes {
@ -90,10 +93,8 @@ bool BASE_ISA::Exec_LUI() const {
imm = get_imm_U() << 12;
regs->setValue(rd, static_cast<std::int32_t>(imm));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "LUI: x" << std::dec << rd << " <- 0x" << std::hex
<< imm << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. LUI: x{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, imm);
return true;
}
@ -109,10 +110,8 @@ bool BASE_ISA::Exec_AUIPC() const {
regs->setValue(rd, new_pc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "AUIPC: x" << std::dec << rd << " <- 0x"
<< std::hex << imm << " + PC (0x" << new_pc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. AUIPC: x{:d} <- 0x{:x} + PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, imm, new_pc);
return true;
}
@ -132,11 +131,8 @@ bool BASE_ISA::Exec_JAL() const {
old_pc = old_pc + 4;
regs->setValue(rd, old_pc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "JAL: x" << std::dec << rd << " <- 0x" << std::hex
<< old_pc << std::dec << ". PC + 0x" << std::hex << mem_addr
<< " -> PC (0x" << new_pc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. JAL: x{:d} <- 0x{:x}. PC + 0x{:x} -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc, mem_addr, new_pc);
return true;
}
@ -157,18 +153,18 @@ bool BASE_ISA::Exec_JALR() {
if( (new_pc & 0x00000003) != 0) {
// not aligned
log->SC_log(Log::ERROR) << "JALR: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc + 4 << " PC <- 0x" << new_pc << "\n";
log->SC_log(Log::ERROR) << "JALR : Exception\n";
logger->debug("{} ns. PC: 0x{:x}. JALR: x{:d} <- 0x{:x} PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc + 4, new_pc);
logger->debug("{} ns. PC: 0x{:x}. JALR : Exception");
RaiseException(EXCEPTION_CAUSE_LOAD_ADDR_MISALIGN, m_instr);
} else {
regs->setPC(new_pc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "JALR: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc + 4 << " PC <- 0x" << new_pc << "\n";
}
}
logger->debug("{} ns. PC: 0x{:x}. JALR: x{:d} <- 0x{:x}. PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc + 4, new_pc);
return true;
}
@ -187,12 +183,8 @@ bool BASE_ISA::Exec_BEQ() const {
new_pc = static_cast<std::int32_t>(regs->getPC());
}
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BEQ: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") == x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. BEQ: x{:d}(0x{:x}) == x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -216,12 +208,8 @@ bool BASE_ISA::Exec_BNE() const {
new_pc = static_cast<std::int32_t>(regs->getPC());
}
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BNE: x" << std::dec << rs1 << "(0x" << std::hex
<< val1 << ") == x" << std::dec << rs2 << "(0x" << std::hex << val2
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. BNE: x{:d}(0x{:x}) != x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, rs2, val2, new_pc);
return true;
}
@ -240,13 +228,8 @@ bool BASE_ISA::Exec_BLT() const {
regs->incPC();
}
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BLT: x" << std::dec << rs1 << "(0x" << std::hex
<< static_cast<std::int32_t>(regs->getValue(rs1)) << ") < x" << std::dec << rs2
<< "(0x" << std::hex << static_cast<std::int32_t>(regs->getValue(rs2))
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. BLT: x{:d}(0x{:x}) < x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -265,13 +248,8 @@ bool BASE_ISA::Exec_BGE() const {
regs->incPC();
}
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BGE: x" << std::dec << rs1 << "(0x" << std::hex
<< static_cast<std::int32_t>(regs->getValue(rs1)) << ") > x" << std::dec << rs2
<< "(0x" << std::hex << static_cast<std::int32_t>(regs->getValue(rs2))
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. BGE: x{:d}(0x{:x}) > x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -291,12 +269,8 @@ bool BASE_ISA::Exec_BLTU() const {
new_pc = static_cast<std::int32_t>(regs->getPC());
}
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BLTU: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") < x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. BLTU: x{:d}(0x{:x}) < x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -315,12 +289,8 @@ bool BASE_ISA::Exec_BGEU() const {
regs->incPC();
}
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BGEU: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") > x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. BGEU: x{:d}(0x{:x}) > x{:d}(0x{:x}) -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -340,10 +310,8 @@ bool BASE_ISA::Exec_LB() const {
perf->dataMemoryRead();
regs->setValue(rd, data);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "LB: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. LB: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -363,10 +331,8 @@ bool BASE_ISA::Exec_LH() const {
perf->dataMemoryRead();
regs->setValue(rd, data);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "LH: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. LH: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -386,12 +352,9 @@ bool BASE_ISA::Exec_LW() const {
perf->dataMemoryRead();
regs->setValue(rd, static_cast<std::int32_t>(data));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "LW: x" << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + " << std::dec << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::hex
<< " (0x" << data << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. LW: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -410,10 +373,9 @@ bool BASE_ISA::Exec_LBU() const {
perf->dataMemoryRead();
regs->setValue(rd, static_cast<std::int32_t>(data));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "LBU: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. LBU: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -433,11 +395,8 @@ bool BASE_ISA::Exec_LHU() const {
regs->setValue(rd, data);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "LHU: x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ") -> x" << rd
<< "(0x" << std::hex << data << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. LHU: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -458,11 +417,8 @@ bool BASE_ISA::Exec_SB() const {
mem_intf->writeDataMem(mem_addr, data, 1);
perf->dataMemoryWrite();
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SB: x" << std::dec << rs2 << " -> x" << rs1
<< " + 0x" << std::hex << imm << " (@0x" << std::hex << mem_addr
<< std::dec << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SB: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, rs1, imm, mem_addr);
return true;
}
@ -483,11 +439,8 @@ bool BASE_ISA::Exec_SH() const {
mem_intf->writeDataMem(mem_addr, data, 2);
perf->dataMemoryWrite();
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SH: x" << std::dec << rs2 << " -> x" << rs1
<< " + 0x" << std::hex << imm << " (@0x" << std::hex << mem_addr
<< std::dec << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SH: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, rs1, imm, mem_addr);
return true;
}
@ -508,11 +461,9 @@ bool BASE_ISA::Exec_SW() const {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SW: x" << std::dec << rs2 << "(0x" << std::hex
<< data << ") -> x" << std::dec << rs1 << " + 0x" << std::hex << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SW: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, rs1, imm, mem_addr);
return true;
}
@ -528,11 +479,8 @@ bool BASE_ISA::Exec_ADDI() const {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "ADDI: x" << std::dec << rs1 << " + " << imm
<< " -> x" << std::dec << rd << "(0x" << std::hex << calc << ")"
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. ADDI: x{:d} + x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd, calc);
return true;
}
@ -547,12 +495,13 @@ bool BASE_ISA::Exec_SLTI() const {
if (static_cast<std::int32_t>(regs->getValue(rs1)) < imm) {
regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTI: x" << rs1 << " < " << imm << " => "
<< "1 -> x" << rd << "\n";
logger->debug("{} ns. PC: 0x{:x}. SLTI: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
} else {
regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTI: x" << rs1 << " < " << imm << " => "
<< "0 -> x" << rd << "\n";
logger->debug("{} ns. PC: 0x{:x}. SLTI: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
}
return true;
@ -568,12 +517,12 @@ bool BASE_ISA::Exec_SLTIU() const {
if (static_cast<std::uint32_t>(regs->getValue(rs1)) < static_cast<std::uint32_t>(imm)) {
regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTIU: x" << rs1 << " < " << imm << " => "
<< "1 -> x" << rd << "\n";
logger->debug("{} ns. PC: 0x{:x}. SLTIU: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
} else {
regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTIU: x" << rs1 << " < " << imm << " => "
<< "0 -> x" << rd << "\n";
logger->debug("{} ns. PC: 0x{:x}. SLTIU: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
}
return true;
@ -591,10 +540,8 @@ bool BASE_ISA::Exec_XORI() const {
calc = regs->getValue(rs1) ^ imm;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "XORI: x" << rs1 << " XOR " << imm << "-> x" << rd
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. XORI: x{:d} XOR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
return true;
}
@ -611,10 +558,8 @@ bool BASE_ISA::Exec_ORI() const {
calc = regs->getValue(rs1) | imm;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "ORI: x" << rs1 << " OR " << imm << "-> x" << rd
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. ORI: x{:d} OR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
return true;
}
@ -633,11 +578,8 @@ bool BASE_ISA::Exec_ANDI() const {
calc = aux & imm;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "ANDI: x" << rs1 << "(0x" << std::hex << aux
<< ") AND 0x" << imm << " -> x" << std::dec << rd << "(0x"
<< std::hex << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. ANDI: x{:d} AND x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
return true;
}
@ -663,10 +605,8 @@ bool BASE_ISA::Exec_SLLI() {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SLLI: x" << std::dec << rs1 << " << " << shift
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SLLI: x{:d} << {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -685,10 +625,8 @@ bool BASE_ISA::Exec_SRLI() const {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SRLI: x" << std::dec << rs1 << " >> " << shift
<< " -> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SRLI: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -707,10 +645,8 @@ bool BASE_ISA::Exec_SRAI() const {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SRAI: x" << std::dec << rs1 << " >> " << shift
<< " -> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SRAI: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -726,10 +662,8 @@ bool BASE_ISA::Exec_ADD() const {
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "ADD: x" << std::dec << rs1 << " + x" << rs2
<< " -> x" << rd << std::hex << "(0x" << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. ADD: x{:d} + x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -744,10 +678,8 @@ bool BASE_ISA::Exec_SUB() const {
calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SUB: x" << rs1 << " - x" << rs2 << " -> x" << rd
<< "(" << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SUB: x{:d} - x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -766,10 +698,8 @@ bool BASE_ISA::Exec_SLL() const {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SLL: x" << rs1 << " << " << shift << " -> x"
<< rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SLL: x{:d} << x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -783,12 +713,12 @@ bool BASE_ISA::Exec_SLT() const {
if (regs->getValue(rs1) < regs->getValue(rs2)) {
regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLT: x" << rs1 << " < x" << rs2 << " => "
<< "1 -> x" << rd << "\n";
logger->debug("{} ns. PC: 0x{:x}. SLT: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
} else {
regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLT: x" << rs1 << " < x" << rs2 << " => "
<< "0 -> x" << rd << "\n";
logger->debug("{} ns. PC: 0x{:x}. SLT: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
}
return true;
@ -803,12 +733,12 @@ bool BASE_ISA::Exec_SLTU() const {
if ( static_cast<std::uint32_t>(regs->getValue(rs1)) < static_cast<std::uint32_t>(regs->getValue(rs2)) ) {
regs->setValue(rd, 1);
log->SC_log(Log::INFO) << "SLTU: x" << rs1 << " < x" << rs2 << " => "
<< "1 -> x" << rd << "\n";
logger->debug("{} ns. PC: 0x{:x}. SLTU: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
} else {
regs->setValue(rd, 0);
log->SC_log(Log::INFO) << "SLTU: x" << rs1 << " < x" << rs2 << " => "
<< "0 -> x" << rd << "\n";
logger->debug("{} ns. PC: 0x{:x}. SLTU: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
}
return true;
@ -825,10 +755,8 @@ bool BASE_ISA::Exec_XOR() const {
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "XOR: x" << rs1 << " XOR x" << rs2 << "-> x" << rd
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. XOR: x{:d} XOR x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -847,10 +775,8 @@ bool BASE_ISA::Exec_SRL() const {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SRL: x" << rs1 << " >> " << shift << " -> x"
<< rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SRL: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -869,10 +795,8 @@ bool BASE_ISA::Exec_SRA() const {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "SRA: x" << rs1 << " >> " << shift << " -> x"
<< rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. SRA: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -888,10 +812,8 @@ bool BASE_ISA::Exec_OR() const {
calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "OR: x" << rs1 << " OR x" << rs2 << "-> x" << rd
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. OR: x{:d} OR x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -907,25 +829,24 @@ bool BASE_ISA::Exec_AND() const {
calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "AND: x" << rs1 << " AND x" << rs2 << "-> x" << rd
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. AND: x{:d} AND x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
bool BASE_ISA::Exec_FENCE() const {
log->SC_log(Log::INFO) << "FENCE" << "\n";
logger->debug("{} ns. PC: 0x{:x}. FENCE");
return true;
}
bool BASE_ISA::Exec_ECALL() {
log->SC_log(Log::INFO) << "ECALL" << "\n" << std::flush ;
std::cout << "\n" << "ECALL Instruction called, stopping simulation"
<< "\n";
logger->debug("{} ns. PC: 0x{:x}. ECALL");
std::cout << std::endl << "ECALL Instruction called, stopping simulation"
<< std::endl;
regs->dump();
std::cout << "Simulation time " << sc_core::sc_time_stamp() << "\n";
perf->dump();
@ -947,9 +868,9 @@ bool BASE_ISA::Exec_ECALL() {
bool BASE_ISA::Exec_EBREAK() {
log->SC_log(Log::INFO) << "EBREAK" << "\n" << std::flush;
std::cout << "\n" << "EBREAK Instruction called, dumping information"
<< "\n";
logger->debug("{} ns. PC: 0x{:x}. EBREAK");
std::cout << std::endl << "EBRAK Instruction called, dumping information"
<< std::endl;
regs->dump();
std::cout << "Simulation time " << sc_core::sc_time_stamp() << "\n";
perf->dump();
@ -977,9 +898,8 @@ bool BASE_ISA::Exec_CSRRW() const {
aux = regs->getValue(rs1);
regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << std::hex << "CSRRW: CSR #" << csr << " -> x"
<< std::dec << rd << ". x" << rs1 << "-> CSR #" << std::hex << csr
<< " (0x" << aux << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. CSRRW: CSR #{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, aux);
return true;
}
@ -994,8 +914,7 @@ bool BASE_ISA::Exec_CSRRS() const {
csr = get_csr();
if (rd == 0) {
log->SC_log(Log::INFO) << "CSRRS with rd1 == 0, doing nothing."
<< "\n";
logger->debug("{} ns. PC: 0x{:x}. CSRRS with rd1 == 0, doing nothing.");
return false;
}
@ -1008,9 +927,8 @@ bool BASE_ISA::Exec_CSRRS() const {
aux2 = aux | bitmask;
regs->setCSR(csr, aux2);
log->SC_log(Log::INFO) << "CSRRS: CSR #" << csr << "(0x" << std::hex << aux
<< ") -> x" << std::dec << rd << ". x" << rs1 << " & CSR #" << csr
<< " <- 0x" << std::hex << aux2 << "\n";
logger->debug("{} ns. PC: 0x{:x}. CSRRS: CSR #{:d}(0x{:x}) -> x{:d}(0x{:x}) & CSR #{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, aux, rd, rs1, csr, aux2);
return true;
}
@ -1025,8 +943,7 @@ bool BASE_ISA::Exec_CSRRC() const {
csr = get_csr();
if (rd == 0) {
log->SC_log(Log::INFO) << "CSRRC with rd1 == 0, doing nothing."
<< "\n";
logger->debug("{} ns. PC: 0x{:x}. CSRRC with rd1 == 0, doing nothing.");
return true;
}
@ -1039,9 +956,8 @@ bool BASE_ISA::Exec_CSRRC() const {
aux2 = aux & ~bitmask;
regs->setCSR(csr, aux2);
log->SC_log(Log::INFO) << "CSRRC: CSR #" << csr << "(0x" << std::hex << aux
<< ") -> x" << std::dec << rd << ". x" << rs1 << " & CSR #" << csr
<< " <- 0x" << std::hex << aux2 << "\n";
logger->debug("{} ns. PC: 0x{:x}. CSRRC: CSR #{:d}(0x{:x}) -> x{:d}(0x{:x}) & CSR #{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, aux, rd, rs1, csr, aux2);
return true;
}
@ -1063,8 +979,8 @@ bool BASE_ISA::Exec_CSRRWI() const {
aux = rs1;
regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRWI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << "-> CSR #" << csr << "\n";
logger->debug("{} ns. PC: 0x{:x}. CSRRWI: CSR #{:d} -> x{:d}. x{:d} -> CSR #{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr);
return true;
}
@ -1090,9 +1006,8 @@ bool BASE_ISA::Exec_CSRRSI() const {
aux = aux | bitmask;
regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRSI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << " & CSR #" << csr << "(0x" << std::hex << aux << ")"
<< "\n";
logger->debug("{} ns. PC: 0x{:x}. CSRRSI: CSR #{:d} -> x{:d}. x{:d} & CSR #{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr, aux);
return true;
}
@ -1118,9 +1033,8 @@ bool BASE_ISA::Exec_CSRRCI() const {
aux = aux & ~bitmask;
regs->setCSR(csr, aux);
log->SC_log(Log::INFO) << "CSRRCI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << " & CSR #" << csr << "(0x" << std::hex << aux << ")"
<< "\n";
logger->debug("{} ns. PC: 0x{:x}. CSRRCI: CSR #{:d} -> x{:d}. x{:d} & CSR #{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr, aux);
return true;
}
@ -1133,8 +1047,7 @@ bool BASE_ISA::Exec_MRET() const {
new_pc = regs->getCSR(CSR_MEPC);
regs->setPC(new_pc);
log->SC_log(Log::INFO) << "MRET: PC <- 0x" << std::hex << new_pc
<< "\n";
logger->debug("{} ns. PC: 0x{:x}. MRET: PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), new_pc);
// update mstatus
std::uint32_t csr_temp;
@ -1154,21 +1067,17 @@ bool BASE_ISA::Exec_SRET() const {
new_pc = regs->getCSR(CSR_SEPC);
regs->setPC(new_pc);
log->SC_log(Log::INFO) << "SRET: PC <- 0x" << std::hex << new_pc
<< "\n";
logger->debug("{} ns. PC: 0x{:x}. SRET: PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC());
return true;
}
bool BASE_ISA::Exec_WFI() const {
log->SC_log(Log::INFO) << "WFI" << "\n";
logger->debug("{} ns. PC: 0x{:x}. WFI");
return true;
}
bool BASE_ISA::Exec_SFENCE() const {
log->SC_log(Log::INFO) << "SFENCE" << "\n";
logger->debug("{} ns. PC: 0x{:x}. SFENCE");
return true;
}

3
src/BusCtrl.cpp
View File

@ -15,11 +15,11 @@ BusCtrl::BusCtrl(sc_core::sc_module_name const &name) :
"trace_socket") {
cpu_instr_socket.register_b_transport(this, &BusCtrl::b_transport);
cpu_data_socket.register_b_transport(this, &BusCtrl::b_transport);
cpu_instr_socket.register_get_direct_mem_ptr(this,
&BusCtrl::instr_direct_mem_ptr);
memory_socket.register_invalidate_direct_mem_ptr(this,
&BusCtrl::invalidate_direct_mem_ptr);
log = Log::getInstance();
}
void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
@ -29,7 +29,6 @@ void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
if (adr >= TO_HOST_ADDRESS / 4) {
std::cout << "To host\n" << std::flush;
log->SC_log(Log::ERROR) << std::flush;
sc_core::sc_stop();
return;
}

28
src/CPU.cpp
View File

@ -15,7 +15,6 @@ CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
mem_intf = new MemoryInterface();
perf = Performance::getInstance();
log = Log::getInstance();
register_bank->setPC(PC);
register_bank->setValue(Registers::sp, (Memory::SIZE / 4) - 1);
@ -49,6 +48,8 @@ CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
if (!debug) {
SC_THREAD(CPU_thread);
}
logger = spdlog::get("my_logger");
}
CPU::~CPU() {
@ -68,7 +69,8 @@ bool CPU::cpu_process_IRQ() {
if (interrupt) {
csr_temp = register_bank->getCSR(CSR_MSTATUS);
if ((csr_temp & MSTATUS_MIE) == 0) {
log->SC_log(Log::DEBUG) << "interrupt delayed" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(), register_bank->getPC());
return ret_value;
}
@ -77,13 +79,16 @@ bool CPU::cpu_process_IRQ() {
if ((csr_temp & MIP_MEIP) == 0) {
csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
register_bank->setCSR(CSR_MIP, csr_temp);
log->SC_log(Log::DEBUG) << "Interrupt!" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(), register_bank->getPC());
/* updated MEPC register */
std::uint32_t old_pc = register_bank->getPC();
register_bank->setCSR(CSR_MEPC, old_pc);
log->SC_log(Log::INFO) << "Old PC Value 0x" << std::hex << old_pc
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(), register_bank->getPC(),
old_pc);
/* update MCAUSE register */
register_bank->setCSR(CSR_MCAUSE, 0x80000000);
@ -91,8 +96,8 @@ bool CPU::cpu_process_IRQ() {
/* set new PC address */
std::uint32_t new_pc = register_bank->getCSR(CSR_MTVEC);
//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
log->SC_log(Log::DEBUG) << "NEW PC Value 0x" << std::hex << new_pc
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(), register_bank->getPC(),
new_pc);
register_bank->setPC(new_pc);
ret_value = true;
@ -137,12 +142,9 @@ bool CPU::CPU_step() {
}
}
perf->codeMemoryRead();
log->SC_log(Log::INFO) << "PC: 0x" << std::hex << register_bank->getPC()
<< ". ";
inst.setInstr(INSTR);
bool breakpoint = false;
perf->codeMemoryRead();
inst.setInstr(INSTR);
bool breakpoint = false;
/* check what type of instruction is and execute it */
switch (inst.check_extension()) {

158
src/C_extension.cpp
View File

@ -141,7 +141,6 @@ op_C_Codes C_extension::decode() const {
return OP_C_ERROR;
break;
}
return OP_C_ERROR;
}
@ -157,9 +156,7 @@ bool C_extension::Exec_C_JR() {
new_pc = static_cast<std::int32_t>(static_cast<std::int32_t>((regs->getValue(rs1)) + static_cast<std::int32_t>(mem_addr)) & 0xFFFFFFFE);
regs->setPC(new_pc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "JR: PC <- 0x" << std::hex << new_pc << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.JR: PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), new_pc);
return true;
}
@ -175,12 +172,8 @@ bool C_extension::Exec_C_MV() {
calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.MV: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ") -> x" << std::dec << rd
<< "(0x" << std::hex << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.MV: x{:d}(0x{:x}) + x{:d}(0x{:x}) -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), rd, calc);
return true;
}
@ -196,10 +189,8 @@ bool C_extension::Exec_C_ADD() {
calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.ADD: x" << std::dec << rs1 << " + x" << rs2
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.ADD: x{:d} + x{} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -221,11 +212,10 @@ bool C_extension::Exec_C_LWSP() {
perf->dataMemoryRead();
regs->setValue(rd, static_cast<std::int32_t>(data));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.LWSP: x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ") -> x" << rd
<< "(" << std::hex << data << ")" << std::dec << "\n";
}
regs->setValue(rd, data);
logger->debug("{} ns. PC: 0x{:x}. C.LWSP: x{:d} + {:d}(@0x{:x}) -> x{:d}({:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd, data);
return true;
}
@ -247,11 +237,8 @@ bool C_extension::Exec_C_ADDI4SPN() {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "C.ADDI4SPN: x" << rs1 << "(0x"
<< std::hex << regs->getValue(rs1) << ") + " << std::dec << imm
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.ADDI4SN: x{:d} + (0x{:x}) + {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, rd, calc);
return true;
}
@ -272,16 +259,16 @@ bool C_extension::Exec_C_ADDI16SP() {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc);
log->SC_log(Log::INFO) << std::dec << "C.ADDI16SP: x" << rs1 << " + "
<< std::dec << imm << " -> x" << rd << "(0x" << std::hex << calc
<< ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. C.ADDI16SP: x{:d} + {:d} -> x{:d} (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd, calc);
} else {
/* C.LUI OPCODE */
rd = get_rd();
imm = get_imm_LUI();
regs->setValue(rd, imm);
log->SC_log(Log::INFO) << std::dec << "C.LUI: x" << rd << " <- 0x"
<< std::hex << imm << "\n";
logger->debug("{} ns. PC: 0x{:x}. C.LUI: x{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, imm);
}
return true;
@ -304,11 +291,8 @@ bool C_extension::Exec_C_SWSP() {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "C.SWSP: x" << rs2 << "(0x"
<< std::hex << data << ") -> x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.SWSP: x{:d}(0x{:x}) -> x{:d} + {} (@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, data, rs1, imm, mem_addr);
return true;
}
@ -329,11 +313,8 @@ bool C_extension::Exec_C_BEQZ() {
new_pc = static_cast<std::int32_t>(regs->getPC());
}
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.BEQZ: x" << std::dec << rs1 << "(" << val1
<< ") == 0? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.BEQZ: x{:d}(0x{:x}) == 0? -> PC (0xx{:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, new_pc);
return true;
}
@ -354,11 +335,8 @@ bool C_extension::Exec_C_BNEZ() {
new_pc = static_cast<std::int32_t>(regs->getPC());
}
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.BNEZ: x" << std::dec << rs1 << "(0x"
<< std::hex << val1 << ") != 0? -> PC (0x" << std::hex << new_pc
<< ")" << std::dec << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.BNEZ: x{:d}(0x{:x}) != 0? -> PC (0xx{:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, new_pc);
return true;
}
@ -375,11 +353,8 @@ bool C_extension::Exec_C_LI() {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "C.LI: x" << rs1 << "("
<< regs->getValue(rs1) << ") + " << imm << " -> x" << rd << "("
<< calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.LI: x{:d} ({:d}) + {:d} -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, rd, calc);
return true;
}
@ -398,10 +373,8 @@ bool C_extension::Exec_C_SRLI() {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.SRLI: x" << rs1 << " >> " << shift << " -> x"
<< rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.SRLI: x{:d} >> {} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd);
return true;
}
@ -420,10 +393,8 @@ bool C_extension::Exec_C_SRAI() {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.SRAI: x" << rs1 << " >> " << std::dec << shift
<< " -> x" << rd << "(" << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.SRAI: x{:d} >> {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -442,10 +413,8 @@ bool C_extension::Exec_C_SLLI() {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.SLLI: x" << std::dec << rs1 << " << " << shift
<< " -> x" << rd << "(0x" << calc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.SLLI: x{:d} << {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -464,10 +433,8 @@ bool C_extension::Exec_C_ANDI() {
calc = aux & imm;
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.ANDI: x" << rs1 << "(" << aux << ") AND "
<< imm << " -> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.ANDI: x{:d}({:d}) AND {:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, aux, imm, rd);
return true;
}
@ -483,10 +450,8 @@ bool C_extension::Exec_C_SUB() {
calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.SUB: x" << std::dec << rs1 << " - x" << rs2
<< " -> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.SUB: x{:d} - x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
return true;
}
@ -502,10 +467,8 @@ bool C_extension::Exec_C_XOR() {
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.XOR: x" << std::dec << rs1 << " XOR x" << rs2
<< "-> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.XOR: x{:d} XOR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
return true;
}
@ -521,10 +484,8 @@ bool C_extension::Exec_C_OR() {
calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C_OR: x" << std::dec << rs1 << " OR x" << rs2
<< "-> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.OR: x{:d} OR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
return true;
}
@ -540,10 +501,8 @@ bool C_extension::Exec_C_AND() {
calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.AND: x" << std::dec << rs1 << " AND x" << rs2
<< "-> x" << rd << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.AND: x{:d} AND x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
return true;
}
@ -560,11 +519,7 @@ bool C_extension::Exec_C_ADDI() const {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.ADDI: x" << std::dec << rs1 << " + " << imm
<< " -> x" << std::dec << rd << "(0x" << std::hex << calc << ")"
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.ADDI: x{:d} + {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), rs1, imm, rd, calc);
return true;
}
@ -583,11 +538,8 @@ bool C_extension::Exec_C_JALR() {
new_pc = static_cast<std::int32_t>((regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE);
regs->setPC(new_pc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.JALR: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc + 4 << " PC <- 0x" << std::hex << new_pc
<< "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.JALR: x{:d} <- 0x{:x} PC <- 0xx{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc + 4, new_pc);
return true;
}
@ -607,12 +559,8 @@ bool C_extension::Exec_C_LW() {
perf->dataMemoryRead();
regs->setValue(rd, static_cast<std::int32_t>(data));
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << std::dec << "C.LW: x" << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + " << std::dec << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::hex
<< " (0x" << data << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.LW: x{:d}(0x{:x}) + {:d} (@0x{:x}) -> {:d} (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, mem_addr, rd, data);
return true;
}
@ -633,11 +581,8 @@ bool C_extension::Exec_C_SW() {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.SW: x" << std::dec << rs2 << "(0x" << std::hex
<< data << ") -> x" << std::dec << rs1 << " + 0x" << std::hex << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.SW: x{:d}(0x{:x}) -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, data, rs1, imm, mem_addr);
return true;
}
@ -657,18 +602,15 @@ bool C_extension::Exec_C_JAL(int m_rd) {
old_pc = old_pc + 2;
regs->setValue(rd, old_pc);
if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "C.JAL: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc << std::dec << ". PC + 0x" << std::hex
<< mem_addr << " -> PC (0x" << new_pc << ")" << "\n";
}
logger->debug("{} ns. PC: 0x{:x}. C.JAL: x{:d} <- 0x{:x}. PC + 0x{:x} -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc, mem_addr, new_pc);
return true;
}
bool C_extension::Exec_C_EBREAK() {
log->SC_log(Log::INFO) << "C.EBREAK" << "\n" << std::flush;
logger->debug("C.EBREAK");
std::cout << "\n" << "C.EBRAK Instruction called, dumping information"
<< "\n";
regs->dump();

1
src/Debug.cpp
View File

@ -10,6 +10,7 @@
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <sstream>
#include <iomanip>
#include <sys/socket.h>
#include <netinet/in.h>

52
src/Log.cpp
View File

@ -1,52 +0,0 @@
/*!
\file Log.cpp
\brief Class to manage Log
\author Màrius Montón
\date Aug 2018
*/
// SPDX-License-Identifier: GPL-3.0-or-later
#include "Log.h"
Log* Log::getInstance() {
if (instance == nullptr) {
instance = new Log("Log.txt");
}
return instance;
}
Log::Log(const char *filename) {
m_stream.open(filename);
currentLogLevel = Log::INFO;
}
void Log::SC_log(std::string const& msg, enum LogLevel level) {
if (level <= currentLogLevel) {
m_stream << "time " << sc_core::sc_time_stamp() << ": " << msg
<< "\n";
}
}
std::ofstream& Log::SC_log(enum LogLevel level) {
if (level <= currentLogLevel) {
m_stream << "time " << sc_core::sc_time_stamp() << ": ";
return m_stream;
} else {
return m_sink;
}
}
void Log::setLogLevel(enum LogLevel newLevel) {
std::cout << "LogLevel set to " << newLevel << "\n";
currentLogLevel = newLevel;
}
enum Log::LogLevel Log::getLogLevel() const {
return currentLogLevel;
}
Log *Log::instance = nullptr;

32
src/M_extension.cpp
View File

@ -59,8 +59,8 @@ bool M_extension::Exec_M_MUL() const {
result = result & 0x00000000FFFFFFFF;
regs->setValue(rd, static_cast<std::int32_t>(result));
log->SC_log(Log::INFO) << std::dec << "MUL: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. M.MUL: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -83,8 +83,8 @@ bool M_extension::Exec_M_MULH() const {
ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value);
log->SC_log(Log::INFO) << std::dec << "MULH: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. M.MULH: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -106,8 +106,8 @@ bool M_extension::Exec_M_MULHSU() const {
result = (result >> 32) & 0x00000000FFFFFFFF;
regs->setValue(rd, static_cast<std::int32_t>(result));
log->SC_log(Log::INFO) << std::dec << "MULHSU: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. M.MULHSU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -129,8 +129,8 @@ bool M_extension::Exec_M_MULHU() const {
ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value);
log->SC_log(Log::INFO) << std::dec << "MULHU: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << ret_value << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. M.MULHU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -158,8 +158,8 @@ bool M_extension::Exec_M_DIV() const {
regs->setValue(rd, static_cast<std::int32_t>(result));
log->SC_log(Log::INFO) << std::dec << "DIV: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. M.DIV: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -185,8 +185,8 @@ bool M_extension::Exec_M_DIVU() const {
regs->setValue(rd, static_cast<std::int32_t>(result));
log->SC_log(Log::INFO) << std::dec << "DIVU: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. M.DIVU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -213,8 +213,8 @@ bool M_extension::Exec_M_REM() const {
regs->setValue(rd, result);
log->SC_log(Log::INFO) << std::dec << "REM: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. M.REM: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -239,8 +239,8 @@ bool M_extension::Exec_M_REMU() const {
regs->setValue(rd, static_cast<std::int32_t>(result));
log->SC_log(Log::INFO) << std::dec << "REMU: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << "\n";
logger->debug("{} ns. PC: 0x{:x}. M.REMU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}

8
src/Memory.cpp
View File

@ -20,8 +20,8 @@ Memory::Memory(sc_core::sc_module_name const &name, std::string const &filename)
program_counter = 0;
readHexFile(filename);
log = Log::getInstance();
log->SC_log(Log::INFO) << "Using file: " << filename << std::endl;
logger = spdlog::get("my_logger");
logger->debug("Using file {}", filename);
}
Memory::Memory(sc_core::sc_module_name const& name) :
@ -32,8 +32,8 @@ Memory::Memory(sc_core::sc_module_name const& name) :
program_counter = 0;
log = Log::getInstance();
log->SC_log(Log::INFO) << "Memory instantiated without file" << std::endl;
logger = spdlog::get("my_logger");
logger->debug("Memory instantiated wihtout file");
}
Memory::~Memory() = default;

23
src/Simulator.cpp
View File

@ -21,6 +21,9 @@
#include "Timer.h"
#include "Debug.h"
#include "spdlog/spdlog.h"
#include "spdlog/sinks/basic_file_sink.h"
std::string filename;
bool debug_session = false;
bool mem_dump = false;
@ -116,6 +119,7 @@ private:
};
Simulator *top;
std::shared_ptr<spdlog::logger> logger;
void intHandler(int dummy) {
delete top;
@ -128,10 +132,6 @@ void process_arguments(int argc, char *argv[]) {
int c;
int debug_level;
Log *log;
log = Log::getInstance();
log->setLogLevel(Log::ERROR);
debug_session = false;
@ -154,19 +154,19 @@ void process_arguments(int argc, char *argv[]) {
switch (debug_level) {
case 3:
log->setLogLevel(Log::INFO);
logger->set_level(spdlog::level::info);
break;
case 2:
log->setLogLevel(Log::WARNING);
logger->set_level(spdlog::level::warn);
break;
case 1:
log->setLogLevel(Log::DEBUG);
logger->set_level(spdlog::level::debug);
break;
case 0:
log->setLogLevel(Log::ERROR);
logger->set_level(spdlog::level::err);
break;
default:
log->setLogLevel(Log::INFO);
logger->set_level(spdlog::level::info);
break;
}
break;
@ -199,6 +199,11 @@ int sc_main(int argc, char *argv[]) {
/* SystemC time resolution set to 1 ns*/
sc_core::sc_set_time_resolution(1, sc_core::SC_NS);
spdlog::filename_t filename = SPDLOG_FILENAME_T("newlog.txt");
logger = spdlog::create<spdlog::sinks::basic_file_sink_mt>("my_logger", filename);
logger->set_pattern("%v");
logger->set_level(spdlog::level::info);
/* Parse and process program arguments. -f is mandatory */
process_arguments(argc, argv);

8
src/extension_base.cpp
View File

@ -13,7 +13,7 @@ extension_base::extension_base(const sc_dt::sc_uint<32> & instr,
m_instr(instr), regs(register_bank), mem_intf(mem_interface) {
perf = Performance::getInstance();
log = Log::getInstance();
logger = spdlog::get("my_logger");
}
extension_base::~extension_base() =default;
@ -48,13 +48,13 @@ void extension_base::RaiseException(std::uint32_t cause, std::uint32_t inst) {
regs->setPC(new_pc);
log->SC_log(Log::ERROR) << "Exception! new PC 0x" << std::hex << new_pc
<< std::endl << std::flush;
logger->debug("{} ns. PC: 0x{:x}. Exception! new PC 0x{:x} ", sc_core::sc_time_stamp().value(), regs->getPC(),
new_pc);
}
bool extension_base::NOP() {
log->SC_log(Log::INFO) << "NOP" << "\n";
logger->debug("{} ns. PC: 0x{:x}. NOP! new PC 0x{:x} ", sc_core::sc_time_stamp().value(), regs->getPC());
sc_core::sc_stop();
return true;
}