colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

typo

This commit is contained in:
mariusmonton 2018-10-08 12:35:07 +02:00
parent 557e3c1ba4
commit 744a2010a5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -37,7 +37,7 @@ Current performance is about 284500 instructions / sec in a Core-i5@2.2Ghz
This is a preliminar and incomplete version. This is a preliminar and incomplete version.
Task to do: Task to do:
* Implement all missing instructions (RISC_V_execute) * Implement all missing instructions (Execute)
* Implement CSRs (where?) * Implement CSRs (where?)
* Add full support to .elf ~~and .hex~~ filetypes to memory.h * Add full support to .elf ~~and .hex~~ filetypes to memory.h
(only partial .hex support) (only partial .hex support)