colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

updated

This commit is contained in:
mariusmonton 2018-09-17 12:35:52 +02:00
parent d0806a5759
commit 79cff335e3
1 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
README.md
View File

@ -3,13 +3,14 @@
**This code is suitable to hard refactor at any time** **This code is suitable to hard refactor at any time**
This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2. This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2.
It partially supports RV32I Instruction set by now.
Brief description of the modules: Brief description of the modules:
* CPU: Top entity that includes all other modules. * CPU: Top entity that includes all other modules.
* Memory: Memory highly based on TLM-2 example with read file capability * Memory: Memory highly based on TLM-2 example with read file capability
* Registers: Implements the register file and PC * Registers: Implements the register file, PC register & CSR registers
* RISC_V_execute: Executes every ISA instruction * RISC_V_execute: Executes ISA instructions
* Instruction: Decodes instruction and acces to any instruction field * Instruction: Decodes instruction and acces to any instruction field
* Simulation: Top-level entity that builds & starts the simulation * Simulation: Top-level entity that builds & starts the simulation
@ -30,13 +31,16 @@ This is a preliminar and incomplete version.
Task to do: Task to do:
* implement all missing instructions (RISC_V_execute) * implement all missing instructions (RISC_V_execute)
* still unresolved data memory access (need to implement hierarchical socket * Implement CSRs (where?)
from CPU to RISC_V_execute)
* Implement CSRs
* Add full support to .elf and .hex filetypes to memory.h * Add full support to .elf and .hex filetypes to memory.h
(only partial .hex support) (only partial .hex support)
* Connect some TLM peripherals * Connect some TLM peripherals
* Debug module similiar to ARM's ITM
* Some standard UART model
* ...
* Test, test, test & test. I'm sure there are a lot of bugs in the code * Test, test, test & test. I'm sure there are a lot of bugs in the code
* Improve structure and modules hierarchy
* Add 64 & 128 bits architecture (RV64I, RV128I)
## compile ## compile
In order to compile the project you need SystemC-2.3.2 installed in your system. In order to compile the project you need SystemC-2.3.2 installed in your system.