From 912ee3a44eb3b49b2908a9596005a2b7023c1b7c Mon Sep 17 00:00:00 2001
From: mariusmonton <marius.monton@gmail.com>
Date: Thu, 27 Sep 2018 16:15:59 +0200
Subject: [PATCH] added twitter address

---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index eb6a7cf..e825a50 100644
--- a/README.md
+++ b/README.md
@@ -7,6 +7,8 @@ This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2.
 It partially supports RV32I Instruction set by now.
 
 [![travis](https://travis-ci.org/mariusmm/RISC-V-TLM.svg?branch=master)](https://travis-ci.org/mariusmm/RISC-V-TLM)
+[![Twitter URL](https://img.shields.io/twitter/url/http/shields.io.svg?style=social)](https://twitter.com/mariusmonton)
+
 
 Brief description of the modules:
 * CPU: Top entity that includes all other modules.