IRQ implemented
This commit is contained in:
mariusmonton
parent
6c3b4347a8
commit
a4a1be7386
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@ -29,6 +29,12 @@ using namespace std;
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* Memory mapped Trace peripheral address
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*/
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#define TRACE_MEMORY_ADDRESS 0x40000000
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#define TIMER_MEMORY_ADDRESS_LO 0x40004000
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#define TIMER_MEMORY_ADDRESS_HI 0x40004004
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#define TIMERCMP_MEMORY_ADDRESS_LO 0x40004008
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#define TIMERCMP_MEMORY_ADDRESS_HI 0x4000400C
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/**
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* @brief Simple bus controller
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*
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@ -60,12 +66,15 @@ public:
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*/
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tlm_utils::simple_initiator_socket<BusCtrl> trace_socket;
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/**
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* @brief TLM initiator socket Trace module
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*/
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tlm_utils::simple_initiator_socket<BusCtrl> timer_socket;
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/**
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* @brief constructor
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* @param name module's name
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*/
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BusCtrl(sc_module_name name);
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/**
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@ -38,7 +38,7 @@ public:
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//tlm_utils::simple_initiator_socket<cpu_base> data_bus;
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//sc_in<sc_signal<bool> > interrupt;
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sc_in<bool> interrupt;
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CPU(sc_module_name name, uint32_t PC);
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~CPU();
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@ -50,6 +50,12 @@ private:
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Performance *perf;
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Log *log;
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/**
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*
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* @brief Process and triggers IRQ if all conditions memory_socket
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* @return true if IRQ is triggered, false otherwise
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*/
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bool cpu_process_IRQ();
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/**
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* @brief Executes default ISA instruction
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* @param inst instruction to execute
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@ -57,6 +57,8 @@
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#define CSR_TIMEH (0xC81)
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#define CSR_INSTRETH (0xC02)
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#define CSR_STVEC (0x105)
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/* 1 ns tick in CYCLE & TIME counters */
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#define TICKS_PER_SECOND (1000000)
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@ -0,0 +1,54 @@
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/*!
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\file Timer.h
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\brief Basic TLM-2 Timer module
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\author Màrius Montón
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\date January 2019
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*/
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#ifndef __TIMER_H__
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#define __TIMER_H__
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#include <iostream>
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#include <fstream>
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include "systemc"
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#include "tlm.h"
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#include "tlm_utils/simple_target_socket.h"
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#include "BusCtrl.h"
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using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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/**
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* @brief Simple timer peripheral
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*
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* It runs a 1 ns (nanoseconds) pace
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*
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*/
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class Timer: sc_module {
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public:
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// TLM-2 socket, defaults to 32-bits wide, base protocol
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tlm_utils::simple_target_socket<Timer> socket;
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sc_out<bool> timer_irq;
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// Constructor
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Timer(sc_module_name name);
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void run();
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// TLM-2 blocking transport method
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virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay );
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private:
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sc_uint<64> m_mtime;
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sc_uint<64> m_mtimecmp;
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sc_event timer_event;
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bool irq_value;
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};
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#endif
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@ -17,10 +17,19 @@ void BusCtrl::b_transport( tlm::tlm_generic_payload& trans, sc_time& delay ) {
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//tlm::tlm_command cmd = trans.get_command();
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sc_dt::uint64 adr = trans.get_address() / 4;
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if (adr == TRACE_MEMORY_ADDRESS / 4) {
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trace_socket->b_transport(trans, delay);
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} else {
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memory_socket->b_transport(trans, delay);
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switch (adr) {
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case TIMER_MEMORY_ADDRESS_HI / 4:
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case TIMER_MEMORY_ADDRESS_LO / 4:
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case TIMERCMP_MEMORY_ADDRESS_HI / 4:
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case TIMERCMP_MEMORY_ADDRESS_LO / 4:
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timer_socket->b_transport(trans, delay);
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break;
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case TRACE_MEMORY_ADDRESS / 4:
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trace_socket->b_transport(trans, delay);
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break;
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default:
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memory_socket->b_transport(trans, delay);
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break;
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}
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#if 0
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49
src/CPU.cpp
49
src/CPU.cpp
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@ -21,6 +21,45 @@ CPU::~CPU() {
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cout << "*********************************************" << endl;
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}
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bool CPU::cpu_process_IRQ() {
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uint32_t csr_temp;
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uint32_t new_pc, old_pc;
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bool ret_value = false;
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if (interrupt == true){
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csr_temp = register_bank->getCSR(CSR_MIP);
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if ( (csr_temp & (1 << 11) ) == 0 ) {
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csr_temp |= (1 << 11); // MEIP bit in MIP register (11th bit)
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register_bank->setCSR(CSR_MIP, csr_temp);
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// cout << "time: " << sc_time_stamp() << ". CPU: interrupt" << endl;
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log->SC_log(Log::INFO) << "Interrupt!" << endl;
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/* updated MEPC register */
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old_pc = register_bank->getPC();
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register_bank->setCSR(CSR_MEPC, old_pc);
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// log->SC_log(Log::INFO) << "Old PC Value 0x" << hex << old_pc << endl;
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/* update MCAUSE register */
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register_bank->setCSR(CSR_MCAUSE, 0x8000000);
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/* set new PC address */
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new_pc = register_bank->getCSR(CSR_MTVEC);
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new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
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// log->SC_log(Log::DEBUG) << "NEW PC Value 0x" << hex << new_pc << endl;
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register_bank->setPC(new_pc);
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ret_value = true;
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}
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} else {
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csr_temp = register_bank->getCSR(CSR_MIP);
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csr_temp &= ~(1 << 11);
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register_bank->setCSR(CSR_MIP, csr_temp);
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}
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return ret_value;
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}
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bool CPU::process_c_instruction(Instruction &inst) {
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bool PC_not_affected = true;
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@ -444,8 +483,6 @@ void CPU::CPU_thread(void) {
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inst.dump();
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exec->NOP(inst);
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} // switch (inst.check_extension())
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/* Fixed instruction time to 10 ns (i.e. 100 MHz)*/
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sc_core::wait(10, SC_NS);
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}
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perf->instructionsInc();
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@ -453,5 +490,13 @@ void CPU::CPU_thread(void) {
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if (PC_not_affected == true) {
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register_bank->incPC(incPCby2);
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}
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/* Process IRQ (if any) */
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cpu_process_IRQ();
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/* Fixed instruction time to 10 ns (i.e. 100 MHz)*/
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sc_core::wait(10, SC_NS);
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} // while(1)
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} // CPU_thread
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@ -18,6 +18,7 @@
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#include "Memory.h"
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#include "BusCtrl.h"
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#include "Trace.h"
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#include "Timer.h"
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using namespace sc_core;
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using namespace sc_dt;
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@ -38,6 +39,7 @@ SC_MODULE(Simulator)
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Memory *MainMemory;
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BusCtrl* Bus;
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Trace *trace;
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Timer *timer;
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uint32_t start_PC;
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sc_signal<bool> IRQ;
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@ -51,13 +53,16 @@ SC_MODULE(Simulator)
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Bus = new BusCtrl("BusCtrl");
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trace = new Trace("Trace");
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timer = new Timer("Timer");
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cpu->instr_bus.bind(Bus->cpu_instr_socket);
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cpu->exec->data_bus.bind(Bus->cpu_data_socket);
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Bus->memory_socket.bind(MainMemory->socket);
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Bus->trace_socket.bind(trace->socket);
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//cpu->interrupt.bind(IRQ);
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Bus->timer_socket.bind(timer->socket);
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timer->timer_irq.bind(IRQ);
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cpu->interrupt.bind(IRQ);
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}
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~Simulator() {
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@ -66,6 +71,7 @@ SC_MODULE(Simulator)
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delete MainMemory;
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delete Bus;
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delete trace;
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delete timer;
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}
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};
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@ -80,6 +86,7 @@ void intHandler(int dummy) {
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int sc_main(int argc, char* argv[])
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{
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/* Capture Ctrl+C and finish the simulation */
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signal(SIGINT, intHandler);
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/* SystemC time resolution set to 1 ns*/
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@ -0,0 +1,95 @@
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#include "Timer.h"
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SC_HAS_PROCESS(Timer);
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Timer::Timer(sc_module_name name): sc_module(name)
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,socket("timer_socket"), m_mtime(0), m_mtimecmp(0), irq_value(false) {
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socket.register_b_transport(this, &Timer::b_transport);
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SC_THREAD(run);
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}
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/**
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* @brief Waits for event timer_event and triggers an IRQ
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*
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*/
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void Timer::run() {
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while(true) {
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// timer_event.notify( sc_time(10000, SC_NS) );
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wait(timer_event);
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if (timer_irq.read() == true) {
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timer_irq.write(false);
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// cout << "time: " << sc_time_stamp() <<". bla bla " << endl;
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} else {
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timer_irq.write(true);
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cout << "time: " << sc_time_stamp() << ". Timer interrupt!" << endl;
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// notify in 20 ns to low irq signal
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timer_event.notify( sc_time(20, SC_NS));
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}
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}
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}
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/**
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*
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* @brief TLM-2.0 socket implementaiton
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* @param trans TLM-2.0 transaction
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* @param delay transactino delay time
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*/
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void Timer::b_transport( tlm::tlm_generic_payload& trans, sc_time& delay ) {
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tlm::tlm_command cmd = trans.get_command();
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sc_dt::uint64 addr = trans.get_address();
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unsigned char* ptr = trans.get_data_ptr();
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uint32_t aux_value = 0;
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uint64_t notify_time = 0;
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unsigned int len = trans.get_data_length();
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//unsigned char* byt = trans.get_byte_enable_ptr();
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//unsigned int wid = trans.get_streaming_width();
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// cout << "accessing TIMER 0x" << hex << addr << endl;
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if (cmd == tlm::TLM_WRITE_COMMAND) {
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memcpy(&aux_value, ptr, len);
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switch (addr) {
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case TIMER_MEMORY_ADDRESS_LO:
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m_mtime.range(31,0) = aux_value;
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break;
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case TIMER_MEMORY_ADDRESS_HI:
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m_mtime.range(63,32) = aux_value;
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break;
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case TIMERCMP_MEMORY_ADDRESS_LO:
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m_mtimecmp.range(31,0) = aux_value;
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// timer_event.notify(SC_ZERO_TIME);
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break;
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case TIMERCMP_MEMORY_ADDRESS_HI:
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m_mtimecmp.range(63,32) = aux_value;
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// notify needs relative time, mtimecmp works in absolute time
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notify_time = m_mtimecmp - m_mtime;
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// cout << "time: " << sc_core::sc_time_stamp()
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// << ": interrupt will be in " << dec << notify_time
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// << " ns" << endl;
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timer_event.notify( sc_time(notify_time, SC_NS) );
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break;
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}
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} else { // TLM_READ_COMMAND
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switch (addr) {
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case TIMER_MEMORY_ADDRESS_LO:
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m_mtime = sc_time_stamp().value();
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aux_value = m_mtime.range(31,0);
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break;
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case TIMER_MEMORY_ADDRESS_HI:
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aux_value = m_mtime.range(63,32);
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break;
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case TIMERCMP_MEMORY_ADDRESS_LO:
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aux_value = m_mtimecmp.range(31,0);
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break;
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case TIMERCMP_MEMORY_ADDRESS_HI:
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aux_value = m_mtimecmp.range(63,32);
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break;
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}
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memcpy(ptr, &aux_value, len);
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}
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trans.set_response_status( tlm::TLM_OK_RESPONSE );
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}
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@ -0,0 +1,56 @@
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TARGET = timer
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TARGET_ARCH=riscv32
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CC = riscv32-unknown-elf-gcc
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# compiling flags here
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CFLAGS = -Wall -I. -O0 -static --specs=nosys.specs
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LINKER = riscv32-unknown-linux-gnu-gcc
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# linking flags here
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LDFLAGS = -I. --entry main -L/opt/riscv/riscv32-unknown-elf/lib/ -T ld_script.ld
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LIBS = $(EXTRA_LIBS)
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# change these to proper directories where each file should be
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SRCDIR = ./
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OBJDIR = .
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BINDIR = ./
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INCDIR = -I.
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LIBDIR = -L.
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SOURCES := $(wildcard $(SRCDIR)/*.c)
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INCLUDES := $(wildcard $(INCDIR)/*.h)
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OBJECTS := $(SOURCES:$(SRCDIR)/%.c=$(OBJDIR)/%.o)
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rm = rm -f
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$(BINDIR)/$(TARGET): $(OBJECTS)
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# $(LINKER) $(OBJECTS) $(LDFLAGS) $(LIBS) $(LIBDIR) -o $@
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riscv32-unknown-linux-gnu-objdump -d $< > dump
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objcopy -Oihex $< $(TARGET).hex
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# @echo "Linking complete!"
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$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
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@echo "Compiling "$<" ..."
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# $(CC) $(CFLAGS) $(INCDIR) -c $< -o $@
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$(CC) $(CFLAGS) $(INCDIR) $< -o $@
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@echo "Done!"
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#$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.S
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# @echo "Assembling "$<" ..."
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# $(CC) $(CFLAGS) $(INCDIR) -c $< -o $@
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# $(CC) $(CFLAGS) $(INCDIR) $< -o $@
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# @echo "Done!"
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.PHONY: clean
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clean:
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@$(rm) $(OBJECTS) *.hex dump
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@echo "Cleanup complete!"
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.PHONY: remove
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remove: clean
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@$(rm) $(BINDIR)/$(TARGET)
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@echo "Executable removed!"
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@ -0,0 +1,58 @@
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TARGET = timer
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TARGET_ARCH=riscv32
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CC = riscv32-unknown-elf-gcc
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# compiling flags here
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CFLAGS = -Wall -I. -O0 -static -march=rv32imac -mabi=ilp32 --specs=nosys.specs
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LINKER = riscv32-unknown-linux-gnu-gcc
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# linking flags here
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LDFLAGS = -I. --entry main -L/opt/riscv/riscv32-unknown-elf/lib/ -T ld_script.ld
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LIBS = $(EXTRA_LIBS)
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# change these to proper directories where each file should be
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SRCDIR = ./
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OBJDIR = .
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BINDIR = ./
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INCDIR = -I.
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LIBDIR = -L.
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SOURCES := $(wildcard $(SRCDIR)/*.c)
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INCLUDES := $(wildcard $(INCDIR)/*.h)
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OBJECTS := $(SOURCES:$(SRCDIR)/%.c=$(OBJDIR)/%.o)
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#OBJECTS := main.o timerasm.o
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rm = rm -f
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$(BINDIR)/$(TARGET): $(OBJECTS)
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# $(LINKER) $(OBJECTS) $(LDFLAGS) $(LIBS) $(LIBDIR) -o $@
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riscv32-unknown-linux-gnu-objdump -d $< > dump
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objcopy -Oihex $< $(TARGET).hex
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# @echo "Linking complete!"
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$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.c
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@echo "Compiling "$<" ..."
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# $(CC) $(CFLAGS) $(INCDIR) -c $< -o $@
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$(CC) $(CFLAGS) $(INCDIR) $< -o $@
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@echo "Done!"
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|
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$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.S
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@echo "Assembling "$<" ..."
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$(CC) $(CFLAGS) $(INCDIR) $< -o $@
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echo "Done!"
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.PHONY: clean
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clean:
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@$(rm) $(OBJECTS) *.hex dump
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@echo "Cleanup complete!"
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.PHONY: remove
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remove: clean
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@$(rm) $(BINDIR)/$(TARGET)
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@echo "Executable removed!"
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,58 @@
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#include <stdio.h>
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#define TIMER (*(uint32_t *)0x40004000)
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#define TIMER_CMP (*(uint32_t *)0x40004008)
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#define TRACE (*(unsigned char *)0x40000000)
|
||||
|
||||
volatile int ticks = 0;
|
||||
|
||||
int _write(int file, const char *ptr, int len) {
|
||||
int x;
|
||||
|
||||
for (x = 0; x < len; x++) {
|
||||
TRACE = *ptr++;
|
||||
}
|
||||
|
||||
return (len);
|
||||
}
|
||||
|
||||
void timer_ISR() {
|
||||
ticks++;
|
||||
}
|
||||
|
||||
void register_timer_isr() {
|
||||
asm volatile("la t0, timer_ISR\n csrw mtvec, t0");
|
||||
asm volatile("li t1, 0x888\ncsrw mie, t1");
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
|
||||
uint32_t timer_value;
|
||||
uint32_t start_time;
|
||||
|
||||
register_timer_isr();
|
||||
|
||||
timer_value = TIMER;
|
||||
printf("Time: %ld ns\n", timer_value);
|
||||
|
||||
timer_value = TIMER;
|
||||
printf("Time: %ld ns\n", timer_value);
|
||||
|
||||
timer_value = TIMER;
|
||||
printf("Time: %ld ns\n", timer_value);
|
||||
|
||||
timer_value = TIMER;
|
||||
printf("Time: %ld ns\n", timer_value);
|
||||
|
||||
start_time = TIMER;
|
||||
TIMER_CMP = start_time + 1000;
|
||||
do {
|
||||
timer_value = TIMER;
|
||||
} while (timer_value < start_time + 50000);
|
||||
asm volatile ("ecall");
|
||||
|
||||
printf("Timer: %ld ns\n", timer_value);
|
||||
asm volatile ("ecall");
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
#include <stdio.h>
|
||||
|
||||
#define TIMER (*(uint64_t *)0x40004000)
|
||||
#define TIMER_CMP (*(uint64_t *)0x40004008)
|
||||
#define TRACE (*(unsigned char *)0x40000000)
|
||||
|
||||
volatile int ticks = 0;
|
||||
|
||||
int _write(int file, const char *ptr, int len) {
|
||||
int x;
|
||||
|
||||
for (x = 0; x < len; x++) {
|
||||
TRACE = *ptr++;
|
||||
}
|
||||
|
||||
return (len);
|
||||
}
|
||||
|
||||
void timer_ISR() {
|
||||
uint32_t timer_value;
|
||||
|
||||
ticks++;
|
||||
if (ticks < 10) {
|
||||
timer_value = TIMER;
|
||||
TIMER_CMP = timer_value + 590; // timer is in nanoseconds, set to 1 ms.
|
||||
}
|
||||
}
|
||||
|
||||
void register_timer_isr() {
|
||||
asm volatile("la t0, TIMER_CMP_INT \n csrw mtvec, t0");
|
||||
asm volatile("li t1, 0x888 \n csrw mie, t1");
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
|
||||
uint32_t timer_value;
|
||||
uint32_t start_time;
|
||||
|
||||
register_timer_isr();
|
||||
|
||||
start_time = TIMER;
|
||||
TIMER_CMP = start_time + 10000;
|
||||
printf("set timer to %ld ns\n", start_time + 10000);
|
||||
|
||||
do {
|
||||
timer_value = TIMER;
|
||||
} while (timer_value < start_time + 200000);
|
||||
|
||||
printf("Timer: %ld ns\n", timer_value);
|
||||
printf("ticks: %ld\n", ticks);
|
||||
asm volatile ("ecall");
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
#include <stdio.h>
|
||||
|
||||
#define TIMER (*(uint64_t *)0x40004000)
|
||||
#define TIMER_CMP (*(uint64_t *)0x40004008)
|
||||
#define TRACE (*(unsigned char *)0x40000000)
|
||||
|
||||
volatile int ticks = 0;
|
||||
|
||||
int _write(int file, const char *ptr, int len) {
|
||||
int x;
|
||||
|
||||
for (x = 0; x < len; x++) {
|
||||
TRACE = *ptr++;
|
||||
}
|
||||
|
||||
return (len);
|
||||
}
|
||||
|
||||
void timer_ISR() {
|
||||
uint32_t timer_value;
|
||||
|
||||
ticks++;
|
||||
// timer_value = TIMER;
|
||||
// TIMER_CMP = timer_value + 1000;
|
||||
}
|
||||
|
||||
void register_timer_isr() {
|
||||
asm volatile("la t0, TIMER_CMP_INT \n csrw mtvec, t0");
|
||||
asm volatile("li t1, 0x888 \n csrw mie, t1");
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
|
||||
uint32_t timer_value;
|
||||
uint32_t start_time;
|
||||
|
||||
register_timer_isr();
|
||||
|
||||
start_time = TIMER;
|
||||
TIMER_CMP = start_time + 10000;
|
||||
printf("set timer to %ld ns\n", start_time + 10000);
|
||||
|
||||
do {
|
||||
timer_value = TIMER;
|
||||
} while (timer_value < start_time + 200000);
|
||||
|
||||
start_time = TIMER;
|
||||
TIMER_CMP = start_time + 10000;
|
||||
printf("set timer to %ld ns\n", start_time + 10000);
|
||||
|
||||
do {
|
||||
timer_value = TIMER;
|
||||
} while (timer_value < start_time + 200000);
|
||||
|
||||
|
||||
printf("Timer: %ld ns\n", timer_value);
|
||||
printf("ticks: %ld\n", ticks);
|
||||
asm volatile ("ecall");
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
.global TIMER_CMP_INT
|
||||
.global portSAVE_CONTEXT
|
||||
.global portRESTORE_CONTEXT
|
||||
.globl timer_ISR
|
||||
|
||||
|
||||
#define STORE sw
|
||||
#define LOAD lw
|
||||
#define REGBYTES 4
|
||||
|
||||
|
||||
TIMER_CMP_INT:
|
||||
/* store execution context on the stack (register content) */
|
||||
addi sp, sp, -REGBYTES * 32
|
||||
STORE x1, 0x0(sp)
|
||||
STORE x4, 3 * REGBYTES(sp)
|
||||
STORE x5, 4 * REGBYTES(sp)
|
||||
STORE x6, 5 * REGBYTES(sp)
|
||||
STORE x7, 6 * REGBYTES(sp)
|
||||
STORE x10, 9 * REGBYTES(sp)
|
||||
STORE x11, 10 * REGBYTES(sp)
|
||||
STORE x12, 11 * REGBYTES(sp)
|
||||
STORE x13, 12 * REGBYTES(sp)
|
||||
STORE x14, 13 * REGBYTES(sp)
|
||||
STORE x15, 14 * REGBYTES(sp)
|
||||
STORE x16, 15 * REGBYTES(sp)
|
||||
STORE x17, 16 * REGBYTES(sp)
|
||||
STORE x28, 27 * REGBYTES(sp)
|
||||
STORE x29, 28 * REGBYTES(sp)
|
||||
STORE x30, 29 * REGBYTES(sp)
|
||||
STORE x31, 30 * REGBYTES(sp)
|
||||
|
||||
/* load interrupt/trap reason and call external C function to handle it */
|
||||
csrr a0, mcause
|
||||
jal timer_ISR
|
||||
|
||||
/* re-store the saved context */
|
||||
LOAD x1, 0x0(sp)
|
||||
LOAD x4, 3 * REGBYTES(sp)
|
||||
LOAD x5, 4 * REGBYTES(sp)
|
||||
LOAD x6, 5 * REGBYTES(sp)
|
||||
LOAD x7, 6 * REGBYTES(sp)
|
||||
LOAD x10, 9 * REGBYTES(sp)
|
||||
LOAD x11, 10 * REGBYTES(sp)
|
||||
LOAD x12, 11 * REGBYTES(sp)
|
||||
LOAD x13, 12 * REGBYTES(sp)
|
||||
LOAD x14, 13 * REGBYTES(sp)
|
||||
LOAD x15, 14 * REGBYTES(sp)
|
||||
LOAD x16, 15 * REGBYTES(sp)
|
||||
LOAD x17, 16 * REGBYTES(sp)
|
||||
LOAD x28, 27 * REGBYTES(sp)
|
||||
LOAD x29, 28 * REGBYTES(sp)
|
||||
LOAD x30, 29 * REGBYTES(sp)
|
||||
LOAD x31, 30 * REGBYTES(sp)
|
||||
addi sp, sp, REGBYTES * 32
|
||||
mret
|
||||
|
||||
Loading…
Reference in New Issue