renamed RISC_V_execute to Execute
This commit is contained in:
mariusmonton
parent
2920415d93
commit
a5773202e1
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@ -16,7 +16,7 @@
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#include "memory.h"
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#include "Instruction.h"
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#include "RISC_V_execute.h"
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#include "Execute.h"
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#include "Registers.h"
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#include "Log.h"
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@ -40,7 +40,7 @@ public:
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CPU(sc_module_name name, uint32_t PC);
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~CPU();
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RISC_V_execute *exec;
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Execute *exec;
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private:
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Registers *register_bank;
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@ -1,11 +1,11 @@
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/*!
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\file RISC_V_execute.h
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\file Execute.h
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\brief RISC-V ISA implementation
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\author Màrius Montón
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\date August 2018
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*/
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#ifndef RISC_V_EXECUTE_H
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#define RISC_V_EXECUTE_H
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#ifndef Execute_H
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#define Execute_H
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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@ -26,7 +26,7 @@ using namespace std;
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/**
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* @brief Risc_V execute module
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*/
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class RISC_V_execute : sc_module {
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class Execute : sc_module {
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public:
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/**
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@ -34,11 +34,11 @@ public:
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* @param name module name
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* @param register_bank pointer to register bank to use
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*/
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RISC_V_execute(sc_module_name name,
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Execute(sc_module_name name,
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Registers *register_bank);
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/* Quick & dirty way to publish a socket though modules */
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tlm_utils::simple_initiator_socket<RISC_V_execute> data_bus;
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tlm_utils::simple_initiator_socket<Execute> data_bus;
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void LUI(Instruction &inst);
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void AUIPC(Instruction &inst);
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@ -6,7 +6,7 @@ CPU::CPU(sc_module_name name, uint32_t PC): sc_module(name)
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, instr_bus("instr_bus")
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{
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register_bank = new Registers();
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exec = new RISC_V_execute("RISC_V_execute", register_bank);
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exec = new Execute("Execute", register_bank);
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perf = Performance::getInstance();
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log = Log::getInstance();
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@ -1,7 +1,7 @@
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#include "RISC_V_execute.h"
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#include "Execute.h"
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SC_HAS_PROCESS(RISC_V_execute);
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RISC_V_execute::RISC_V_execute(sc_module_name name
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SC_HAS_PROCESS(Execute);
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Execute::Execute(sc_module_name name
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, Registers *register_bank)
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: sc_module(name)
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, data_bus("data_bus")
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@ -10,7 +10,7 @@ RISC_V_execute::RISC_V_execute(sc_module_name name
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log = Log::getInstance();
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}
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void RISC_V_execute::LUI(Instruction &inst) {
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void Execute::LUI(Instruction &inst) {
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int rd;
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uint32_t imm = 0;
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@ -21,7 +21,7 @@ void RISC_V_execute::LUI(Instruction &inst) {
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}
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void RISC_V_execute::AUIPC(Instruction &inst) {
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void Execute::AUIPC(Instruction &inst) {
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int rd;
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uint32_t imm = 0;
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int new_pc;
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@ -36,7 +36,7 @@ void RISC_V_execute::AUIPC(Instruction &inst) {
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log->SC_log(Log::INFO) << "AUIPC R" << rd << " + PC -> PC (" << new_pc << ")" << endl;
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}
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void RISC_V_execute::JAL(Instruction &inst) {
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void Execute::JAL(Instruction &inst) {
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int32_t mem_addr = 0;
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int rd;
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int new_pc, old_pc;
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@ -58,7 +58,7 @@ void RISC_V_execute::JAL(Instruction &inst) {
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<< hex << new_pc << ")" << endl;
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}
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void RISC_V_execute::JALR(Instruction &inst) {
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void Execute::JALR(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rd, rs1;
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int new_pc, old_pc;
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@ -78,7 +78,7 @@ void RISC_V_execute::JALR(Instruction &inst) {
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<< " PC <- 0x" << hex << new_pc << endl;
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}
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void RISC_V_execute::BEQ(Instruction &inst) {
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void Execute::BEQ(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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@ -96,7 +96,7 @@ void RISC_V_execute::BEQ(Instruction &inst) {
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}
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void RISC_V_execute::BNE(Instruction &inst) {
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void Execute::BNE(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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uint32_t val1, val2;
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@ -119,7 +119,7 @@ void RISC_V_execute::BNE(Instruction &inst) {
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<< new_pc << ")" << endl;
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}
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void RISC_V_execute::BLT(Instruction &inst) {
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void Execute::BLT(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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@ -136,7 +136,7 @@ void RISC_V_execute::BLT(Instruction &inst) {
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log->SC_log(Log::INFO) << "BLT R" << rs1 << " < R" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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}
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void RISC_V_execute::BGE(Instruction &inst) {
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void Execute::BGE(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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@ -156,7 +156,7 @@ void RISC_V_execute::BGE(Instruction &inst) {
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<< ")? -> PC (" << new_pc << ")" << endl;
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}
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void RISC_V_execute::BLTU(Instruction &inst) {
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void Execute::BLTU(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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@ -173,7 +173,7 @@ void RISC_V_execute::BLTU(Instruction &inst) {
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log->SC_log(Log::INFO) << "BLTU R" << rs1 << " < R" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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}
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void RISC_V_execute::BGEU(Instruction &inst) {
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void Execute::BGEU(Instruction &inst) {
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int rs1, rs2;
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int new_pc = 0;
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@ -190,7 +190,7 @@ void RISC_V_execute::BGEU(Instruction &inst) {
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log->SC_log(Log::INFO) << "BGEU R" << rs1 << " > R" << rs2 << "? -> PC (" << new_pc << ")" << endl;
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}
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void RISC_V_execute::LB(Instruction &inst) {
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void Execute::LB(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rd, rs1;
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int32_t imm = 0;
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@ -208,7 +208,7 @@ void RISC_V_execute::LB(Instruction &inst) {
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<< hex <<mem_addr << dec << ") -> R" << rd << endl;
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}
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void RISC_V_execute::LH(Instruction &inst) {
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void Execute::LH(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rd, rs1;
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int32_t imm = 0;
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@ -226,7 +226,7 @@ void RISC_V_execute::LH(Instruction &inst) {
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<< hex <<mem_addr << dec << ") -> R" << rd << endl;
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}
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void RISC_V_execute::LW(Instruction &inst) {
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void Execute::LW(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rd, rs1;
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int32_t imm = 0;
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@ -244,7 +244,7 @@ void RISC_V_execute::LW(Instruction &inst) {
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<< hex <<mem_addr << dec << ") -> R" << rd << endl;
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}
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void RISC_V_execute::LBU(Instruction &inst) {
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void Execute::LBU(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rd, rs1;
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int32_t imm = 0;
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@ -262,7 +262,7 @@ void RISC_V_execute::LBU(Instruction &inst) {
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<< hex <<mem_addr << dec << ") -> R" << rd << endl;
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}
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void RISC_V_execute::LHU(Instruction &inst) {
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void Execute::LHU(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rd, rs1;
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int32_t imm = 0;
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@ -280,7 +280,7 @@ void RISC_V_execute::LHU(Instruction &inst) {
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<< hex <<mem_addr << dec << ") -> R" << rd << endl;
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}
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void RISC_V_execute::SB(Instruction &inst) {
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void Execute::SB(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rs1, rs2;
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int32_t imm = 0;
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@ -299,7 +299,7 @@ void RISC_V_execute::SB(Instruction &inst) {
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<< imm << " (@0x" << hex <<mem_addr << dec << ")" << endl;
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}
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void RISC_V_execute::SH(Instruction &inst) {
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void Execute::SH(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rs1, rs2;
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int32_t imm = 0;
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@ -318,7 +318,7 @@ void RISC_V_execute::SH(Instruction &inst) {
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<< imm << " (@0x" << hex <<mem_addr << dec << ")" << endl;
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}
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void RISC_V_execute::SW(Instruction &inst) {
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void Execute::SW(Instruction &inst) {
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uint32_t mem_addr = 0;
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int rs1, rs2;
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int32_t imm = 0;
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@ -338,7 +338,7 @@ void RISC_V_execute::SW(Instruction &inst) {
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<< " (@0x" << hex << mem_addr << dec << ")" << endl;
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}
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void RISC_V_execute::ADDI(Instruction &inst) {
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void Execute::ADDI(Instruction &inst) {
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int rd, rs1;
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int32_t imm = 0;
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int32_t calc;
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@ -353,7 +353,7 @@ void RISC_V_execute::ADDI(Instruction &inst) {
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log->SC_log(Log::INFO) << dec << "ADDI: R" << rs1 << " + " << imm << " -> R" << rd << endl;
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}
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void RISC_V_execute::SLTI(Instruction &inst) {
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void Execute::SLTI(Instruction &inst) {
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int rd, rs1;
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int32_t imm;
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@ -372,7 +372,7 @@ void RISC_V_execute::SLTI(Instruction &inst) {
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}
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}
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void RISC_V_execute::SLTIU(Instruction &inst) {
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void Execute::SLTIU(Instruction &inst) {
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int rd, rs1;
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int32_t imm;
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@ -391,7 +391,7 @@ void RISC_V_execute::SLTIU(Instruction &inst) {
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}
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}
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void RISC_V_execute::XORI(Instruction &inst) {
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void Execute::XORI(Instruction &inst) {
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int rd, rs1;
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int32_t imm;
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uint32_t calc;
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@ -407,7 +407,7 @@ void RISC_V_execute::XORI(Instruction &inst) {
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<< "-> R" << rd << endl;
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}
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void RISC_V_execute::ORI(Instruction &inst) {
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void Execute::ORI(Instruction &inst) {
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int rd, rs1;
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int32_t imm;
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uint32_t calc;
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@ -423,7 +423,7 @@ void RISC_V_execute::ORI(Instruction &inst) {
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<< "-> R" << rd << endl;
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}
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void RISC_V_execute::ANDI(Instruction &inst) {
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void Execute::ANDI(Instruction &inst) {
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int rd, rs1;
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int32_t imm;
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uint32_t calc;
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@ -439,7 +439,7 @@ void RISC_V_execute::ANDI(Instruction &inst) {
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<< " -> R" << rd << endl;
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}
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void RISC_V_execute::SLLI(Instruction &inst) {
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void Execute::SLLI(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t shift;
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uint32_t calc;
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@ -456,7 +456,7 @@ void RISC_V_execute::SLLI(Instruction &inst) {
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log->SC_log(Log::INFO) << "SLLI: R" << rs1 << " << " << shift << " -> R" << rd << endl;
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}
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void RISC_V_execute::SRLI(Instruction &inst) {
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void Execute::SRLI(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t shift;
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uint32_t calc;
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@ -473,7 +473,7 @@ void RISC_V_execute::SRLI(Instruction &inst) {
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log->SC_log(Log::INFO) << "SRLI: R" << rs1 << " >> " << shift << " -> R" << rd << endl;
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}
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void RISC_V_execute::SRAI(Instruction &inst) {
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void Execute::SRAI(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t shift;
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int32_t calc;
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@ -490,7 +490,7 @@ void RISC_V_execute::SRAI(Instruction &inst) {
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log->SC_log(Log::INFO) << "SRAI: R" << rs1 << " >> " << shift << " -> R" << rd << endl;
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}
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void RISC_V_execute::ADD(Instruction &inst) {
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void Execute::ADD(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t calc;
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rd = inst.rd();
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@ -503,7 +503,7 @@ void RISC_V_execute::ADD(Instruction &inst) {
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log->SC_log(Log::INFO) << "ADD: R" << rs1 << " + R" << rs2 << " -> R" << rd << endl;
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}
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void RISC_V_execute::SUB(Instruction &inst) {
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void Execute::SUB(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t calc;
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rd = inst.rd();
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@ -518,7 +518,7 @@ void RISC_V_execute::SUB(Instruction &inst) {
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log->SC_log(Log::INFO) << "SUB: R" << rs1 << " - R" << rs2 << " -> R" << rd << endl;
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}
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void RISC_V_execute::SLL(Instruction &inst) {
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void Execute::SLL(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t shift;
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uint32_t calc;
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@ -537,7 +537,7 @@ void RISC_V_execute::SLL(Instruction &inst) {
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/** */
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void RISC_V_execute::SLT(Instruction &inst) {
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void Execute::SLT(Instruction &inst) {
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int rd, rs1, rs2;
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rd = inst.rd();
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@ -556,7 +556,7 @@ void RISC_V_execute::SLT(Instruction &inst) {
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}
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void RISC_V_execute::SLTU(Instruction &inst) {
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void Execute::SLTU(Instruction &inst) {
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int rd, rs1, rs2;
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rd = inst.rd();
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@ -575,7 +575,7 @@ void RISC_V_execute::SLTU(Instruction &inst) {
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}
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void RISC_V_execute::XOR(Instruction &inst) {
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void Execute::XOR(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t calc;
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@ -592,7 +592,7 @@ void RISC_V_execute::XOR(Instruction &inst) {
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void RISC_V_execute::SRL(Instruction &inst) {
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void Execute::SRL(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t shift;
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uint32_t calc;
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@ -609,7 +609,7 @@ void RISC_V_execute::SRL(Instruction &inst) {
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log->SC_log(Log::INFO) << "SRL: R" << rs1 << " >> " << shift << " -> R" << rd << endl;
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}
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void RISC_V_execute::SRA(Instruction &inst) {
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void Execute::SRA(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t shift;
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int32_t calc;
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@ -627,7 +627,7 @@ void RISC_V_execute::SRA(Instruction &inst) {
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}
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void RISC_V_execute::OR(Instruction &inst) {
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void Execute::OR(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t calc;
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@ -643,7 +643,7 @@ void RISC_V_execute::OR(Instruction &inst) {
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}
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void RISC_V_execute::AND(Instruction &inst) {
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void Execute::AND(Instruction &inst) {
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int rd, rs1, rs2;
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uint32_t calc;
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@ -658,7 +658,7 @@ void RISC_V_execute::AND(Instruction &inst) {
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<< "-> R" << rd << endl;
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}
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void RISC_V_execute::CSRRW(Instruction &inst) {
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void Execute::CSRRW(Instruction &inst) {
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int rd, rs1;
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int csr;
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uint32_t aux;
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@ -681,7 +681,7 @@ void RISC_V_execute::CSRRW(Instruction &inst) {
|
|||
<< ". R" << rs1 << "-> CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void RISC_V_execute::CSRRS(Instruction &inst) {
|
||||
void Execute::CSRRS(Instruction &inst) {
|
||||
int rd, rs1;
|
||||
int csr;
|
||||
uint32_t bitmask, aux;
|
||||
|
|
@ -706,7 +706,7 @@ void RISC_V_execute::CSRRS(Instruction &inst) {
|
|||
<< ". R" << rs1 << " & CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void RISC_V_execute::CSRRC(Instruction &inst) {
|
||||
void Execute::CSRRC(Instruction &inst) {
|
||||
int rd, rs1;
|
||||
int csr;
|
||||
uint32_t bitmask, aux;
|
||||
|
|
@ -731,13 +731,13 @@ void RISC_V_execute::CSRRC(Instruction &inst) {
|
|||
<< ". R" << rs1 << " & CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void RISC_V_execute::NOP(Instruction &inst) {
|
||||
void Execute::NOP(Instruction &inst) {
|
||||
cout << endl;
|
||||
regs->dump();
|
||||
cout << "Simulation time " << sc_time_stamp() << endl;
|
||||
perf->dump();
|
||||
|
||||
SC_REPORT_ERROR("RISC_V_execute", "NOP");
|
||||
SC_REPORT_ERROR("Execute", "NOP");
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -746,7 +746,7 @@ void RISC_V_execute::NOP(Instruction &inst) {
|
|||
* @param size size of the data to read in bytes
|
||||
* @return data value read
|
||||
*/
|
||||
uint32_t RISC_V_execute::readDataMem(uint32_t addr, int size) {
|
||||
uint32_t Execute::readDataMem(uint32_t addr, int size) {
|
||||
uint32_t data;
|
||||
tlm::tlm_generic_payload trans;
|
||||
sc_time delay = SC_ZERO_TIME;
|
||||
|
|
@ -772,7 +772,7 @@ uint32_t RISC_V_execute::readDataMem(uint32_t addr, int size) {
|
|||
* @param data data to write
|
||||
* @param size size of the data to write in bytes
|
||||
*/
|
||||
void RISC_V_execute::writeDataMem(uint32_t addr, uint32_t data, int size) {
|
||||
void Execute::writeDataMem(uint32_t addr, uint32_t data, int size) {
|
||||
tlm::tlm_generic_payload trans;
|
||||
sc_time delay = SC_ZERO_TIME;
|
||||
|
||||
Loading…
Reference in New Issue