minor changes
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2c93492ab1
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@ -7,14 +7,11 @@ Registers::Registers() {
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perf = Performance::getInstance();
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perf = Performance::getInstance();
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initCSR();
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initCSR();
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//register_bank[sp] = 1024-1; // SP points to end of memory
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//register_bank[sp] = 0x70000000;
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//register_bank[sp] = (0x10000000 / 4) - 1;
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//cout << "Memory size: 0x" << hex << Memory::SIZE << endl;
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//cout << "Memory size: 0x" << hex << Memory::SIZE << endl;
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//cout << "SP address: 0x" << hex << (0x10000000 / 4) - 1 << endl;
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//cout << "SP address: 0x" << hex << (0x10000000 / 4) - 1 << endl;
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//register_bank[sp] = Memory::SIZE-4;
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register_bank[sp] = Memory::SIZE-4; // default stack at the end of the memory
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register_PC = 0x80000000; // default _start address
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register_PC = 0x80000000; // default _start address
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}
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}
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@ -119,7 +116,7 @@ uint32_t Registers::getCSR(int csr) {
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void Registers::setCSR(int csr, uint32_t value) {
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void Registers::setCSR(int csr, uint32_t value) {
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/* @note rv32mi-p-ma_fetch tests doesn't allow MISA to writable,
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/* @FIXME: rv32mi-p-ma_fetch tests doesn't allow MISA to writable,
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* but Volume II: Privileged Architectura v1.10 says MISRA is writable (?)
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* but Volume II: Privileged Architectura v1.10 says MISRA is writable (?)
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*/
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*/
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if (csr != CSR_MISA) {
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if (csr != CSR_MISA) {
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@ -130,5 +127,6 @@ void Registers::setCSR(int csr, uint32_t value) {
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void Registers::initCSR() {
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void Registers::initCSR() {
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CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
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CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
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| MISA_A_EXTENSION | MISA_I_BASE;
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| MISA_A_EXTENSION | MISA_I_BASE;
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CSR[CSR_MSTATUS] = MISA_MXL ;
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}
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}
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@ -47,7 +47,7 @@ SC_MODULE(Simulator)
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SC_CTOR(Simulator)
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SC_CTOR(Simulator)
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{
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{
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log = Log::getInstance();
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log = Log::getInstance();
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log->setLogLevel(Log::ERROR);
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log->setLogLevel(Log::INFO);
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MainMemory = new Memory("Main_Memory", filename);
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MainMemory = new Memory("Main_Memory", filename);
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start_PC = MainMemory->getPCfromHEX();
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start_PC = MainMemory->getPCfromHEX();
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