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risc-v-tlm
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minor changes

This commit is contained in:
mariusmonton 2019-02-11 15:54:13 +01:00
parent 2c93492ab1
commit a87743b92d
2 changed files with 4 additions and 6 deletions
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8
src/Registers.cpp
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@ -7,14 +7,11 @@ Registers::Registers() {
perf = Performance::getInstance();
initCSR();
//register_bank[sp] = 1024-1; // SP points to end of memory
//register_bank[sp] = 0x70000000;
//register_bank[sp] = (0x10000000 / 4) - 1;
//cout << "Memory size: 0x" << hex << Memory::SIZE << endl;
//cout << "SP address: 0x" << hex << (0x10000000 / 4) - 1 << endl;
//register_bank[sp] = Memory::SIZE-4;
register_bank[sp] = Memory::SIZE-4; // default stack at the end of the memory
register_PC = 0x80000000; // default _start address
}
@ -119,7 +116,7 @@ uint32_t Registers::getCSR(int csr) {
void Registers::setCSR(int csr, uint32_t value) {
/* @note rv32mi-p-ma_fetch tests doesn't allow MISA to writable,
/* @FIXME: rv32mi-p-ma_fetch tests doesn't allow MISA to writable,
* but Volume II: Privileged Architectura v1.10 says MISRA is writable (?)
*/
if (csr != CSR_MISA) {
@ -130,5 +127,6 @@ void Registers::setCSR(int csr, uint32_t value) {
void Registers::initCSR() {
CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
| MISA_A_EXTENSION | MISA_I_BASE;
CSR[CSR_MSTATUS] = MISA_MXL ;
}

2
src/Simulator.cpp
View File

@ -47,7 +47,7 @@ SC_MODULE(Simulator)
SC_CTOR(Simulator)
{
log = Log::getInstance();
log->setLogLevel(Log::ERROR);
log->setLogLevel(Log::INFO);
MainMemory = new Memory("Main_Memory", filename);
start_PC = MainMemory->getPCfromHEX();