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risc-v-tlm
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enable interrupts writing to mstatus

This commit is contained in:
mariusmonton 2019-01-22 19:31:13 +01:00
parent fa3b178f79
commit a8943a111f
1 changed files with 3 additions and 0 deletions
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3
tests/C/timer/timer.c
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@ -33,6 +33,9 @@ void register_timer_isr() {
asm volatile("csrw mtvec, t0"); asm volatile("csrw mtvec, t0");
asm volatile("li t1, 0x888"); asm volatile("li t1, 0x888");
asm volatile("csrw mie, t1"); asm volatile("csrw mie, t1");
// enable interrupts
asm volatile( "csrs mstatus,1" );
} }
int main(void) { int main(void) {