Added instructions to pass riscv-tests
This commit is contained in:
mariusmonton
parent
f17b3b75d5
commit
aa526943b9
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@ -15,10 +15,11 @@
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#include "tlm_utils/simple_initiator_socket.h"
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#include "memory.h"
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#include "Instruction.h"
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#include "Execute.h"
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#include "Registers.h"
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#include "Log.h"
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#include "Instruction.h"
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#include "C_Instruction.h"
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using namespace sc_core;
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using namespace sc_dt;
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@ -52,8 +53,9 @@ private:
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* @param inst instruction to execute
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* @return true if PC is affected by instruction
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*/
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bool process_default_instruction(Instruction &inst);
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bool process_base_instruction(Instruction &inst);
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bool process_c_instruction(Instruction &inst);
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void CPU_thread(void);
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@ -16,6 +16,7 @@
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#include "memory.h"
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#include "Instruction.h"
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#include "C_Instruction.h"
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#include "Registers.h"
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#include "Log.h"
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@ -43,7 +44,7 @@ public:
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void LUI(Instruction &inst);
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void AUIPC(Instruction &inst);
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void JAL(Instruction &inst);
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void JAL(Instruction &inst, bool c_extension = false, int m_rd = 1);
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void JALR(Instruction &inst);
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void BEQ(Instruction &inst);
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@ -55,7 +56,7 @@ public:
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void LB(Instruction &inst);
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void LH(Instruction &inst);
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void LW(Instruction &inst);
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void LW(Instruction &inst, bool c_extension = false);
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void LBU(Instruction &inst);
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void LHU(Instruction &inst);
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@ -65,7 +66,7 @@ public:
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void SBU(Instruction &inst);
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void SHU(Instruction &inst);
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void ADDI(Instruction &inst);
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void ADDI(Instruction &inst, bool c_extension = false);
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void SLTI(Instruction &inst);
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void SLTIU(Instruction &inst);
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void XORI(Instruction &inst);
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@ -87,6 +88,9 @@ public:
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void OR(Instruction &inst);
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void AND(Instruction &inst);
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void FENCE(Instruction &inst);
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void ECALL(Instruction &inst);
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void CSRRW(Instruction &inst);
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void CSRRS(Instruction &inst);
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void CSRRC(Instruction &inst);
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@ -94,6 +98,19 @@ public:
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void CSRRSI(Instruction &inst);
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void CSRRCI(Instruction &inst);
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void MRET(Instruction &inst);
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/* C Extensions */
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void C_JR(Instruction &inst);
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void C_MV(Instruction &inst);
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void C_LWSP(Instruction &inst);
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void C_ADDI4SPN(Instruction &inst);
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void C_ADDI16SP(Instruction &inst);
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void C_SWSP(Instruction &inst);
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void C_BEQZ(Instruction &inst);
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void C_BNEZ(Instruction &inst);
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void C_LI(Instruction &inst);
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void NOP(Instruction &inst);
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private:
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@ -14,6 +14,23 @@ using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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typedef enum {
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BASE_EXTENSION,
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M_EXTENSION,
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A_EXTENSION,
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F_EXTENSION,
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D_EXTENSION,
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Q_EXTENSION,
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L_EXTENSION,
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C_EXTENSION,
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R_EXTENSION,
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J_EXTENSION,
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P_EXTENSION,
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V_EXTENSION,
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N_EXTENSION,
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UNKNOWN_EXTENSION
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} extension_t;
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typedef enum {
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OP_LUI,
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OP_AUIPC,
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@ -58,6 +75,21 @@ OP_SRA,
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OP_OR,
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OP_AND,
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OP_FENCE,
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OP_ECALL,
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OP_EBREAK,
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OP_CSRRW,
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OP_CSRRS,
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OP_CSRRC,
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OP_CSRRWI,
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OP_CSRRSI,
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OP_CSRRCI,
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OP_URET,
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OP_SRET,
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OP_MRET,
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OP_ERROR
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} opCodes;
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@ -116,6 +148,21 @@ typedef enum {
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SRA_F7 = 0b0100000,
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OR_F = 0b110,
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AND_F = 0b111,
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FENCE = 0b0001111,
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ECALL = 0b1110011,
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ECALL_F = 0b000000000000,
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EBREAK_F= 0b000000000001,
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URET_F = 0b000000000010,
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SRET_F = 0b000100000010,
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MRET_F = 0b001100000010,
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ECALL_F3= 0b000,
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CSRRW = 0b001,
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CSRRS = 0b010,
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CSRRC = 0b011,
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CSRRWI = 0b101,
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CSRRSI = 0b110,
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CSRRCI = 0b111,
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} Codes;
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/**
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@ -311,7 +358,11 @@ public:
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}
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inline int32_t get_csr() {
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return get_imm_I();
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int32_t aux = 0;
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aux = m_instr.range(31, 20);
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return aux;
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}
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/**
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@ -320,6 +371,18 @@ public:
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*/
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opCodes decode();
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/**
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* @brief returns what instruction extension
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* @return extension
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*/
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extension_t check_extension();
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uint32_t getInstr() {
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return m_instr;
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}
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inline void dump() {
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cout << hex << "0x" << m_instr << dec << endl;
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}
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@ -48,14 +48,12 @@ public:
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// *********************************************
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// TLM-2 forward DMI method
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// *********************************************
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virtual bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
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tlm::tlm_dmi& dmi_data);
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// *********************************************
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// TLM-2 debug transport method
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// *********************************************
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virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
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private:
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117
src/CPU.cpp
117
src/CPU.cpp
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@ -1,4 +1,3 @@
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#include "CPU.h"
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SC_HAS_PROCESS(CPU);
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@ -22,7 +21,69 @@ CPU::~CPU() {
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cout << "*********************************************" << endl;
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}
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bool CPU::process_default_instruction(Instruction &inst) {
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bool CPU::process_c_instruction(Instruction &inst) {
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bool PC_not_affected = true;
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C_Instruction c_inst(inst.getInstr());
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switch(c_inst.decode()) {
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case OP_C_ADDI4SPN:
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exec->C_ADDI4SPN(inst);
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break;
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case OP_C_LW:
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exec->LW(inst, true);
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break;
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case OP_C_ADDI:
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exec->ADDI(inst, true);
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break;
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case OP_C_JAL:
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exec->JAL(inst, true, 1);
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PC_not_affected = false;
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break;
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case OP_C_J:
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exec->JAL(inst, true, 0);
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PC_not_affected = false;
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break;
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case OP_C_LI:
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exec->C_LI(inst);
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break;
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case OP_C_LWSP:
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exec->C_LWSP(inst);
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break;
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case OP_C_JR:
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exec->C_JR(inst);
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PC_not_affected = false;
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break;
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case OP_C_MV:
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exec->C_MV(inst);
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break;
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case OP_C_SWSP:
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exec->C_SWSP(inst);
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break;
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case OP_C_ADDI16SP:
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exec->C_ADDI16SP(inst);
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break;
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case OP_C_BEQZ:
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exec->C_BEQZ(inst);
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PC_not_affected = false;
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break;
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case OP_C_BNEZ:
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exec->C_BNEZ(inst);
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PC_not_affected = false;
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break;
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default:
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std::cout << "C instruction not implemented yet" << endl;
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inst.dump();
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exec->NOP(inst);
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//sc_stop();
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break;
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}
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return PC_not_affected;
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}
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bool CPU::process_base_instruction(Instruction &inst) {
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bool PC_not_affected = true;
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switch(inst.decode()) {
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@ -156,7 +217,40 @@ bool CPU::process_default_instruction(Instruction &inst) {
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exec->CSRRC(inst);
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break;
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#endif
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case OP_FENCE:
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exec->FENCE(inst);
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break;
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case OP_ECALL:
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exec->ECALL(inst);
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break;
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case OP_CSRRW:
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exec->CSRRW(inst);
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break;
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case OP_CSRRS:
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exec->CSRRS(inst);
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break;
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case OP_CSRRC:
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exec->CSRRC(inst);
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break;
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case OP_CSRRWI:
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exec->CSRRWI(inst);
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break;
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case OP_CSRRSI:
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exec->CSRRSI(inst);
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break;
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case OP_CSRRCI:
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exec->CSRRCI(inst);
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break;
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case OP_MRET:
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exec->MRET(inst);
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PC_not_affected = false;
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break;
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default:
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std::cout << "Wrong instruction" << endl;
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inst.dump();
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exec->NOP(inst);
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//sc_stop();
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break;
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}
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@ -173,6 +267,7 @@ void CPU::CPU_thread(void) {
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uint32_t INSTR;
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sc_time delay = SC_ZERO_TIME;
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bool PC_not_affected;
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bool incPCby2 = false;
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trans->set_command( tlm::TLM_READ_COMMAND );
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trans->set_data_ptr( reinterpret_cast<unsigned char*>(&INSTR) );
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@ -197,14 +292,26 @@ void CPU::CPU_thread(void) {
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log->SC_log(Log::INFO) << "PC: " << hex << register_bank->getPC()
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<< dec << endl;
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Instruction inst(INSTR);
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/* check what type of instruction is and execute it */
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switch(inst.check_extension()) {
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case BASE_EXTENSION:
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PC_not_affected = process_base_instruction(inst);
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incPCby2 = false;
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break;
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case C_EXTENSION:
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PC_not_affected = process_c_instruction(inst);
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incPCby2 = true;
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break;
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default:
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std::cout << "Extension not implemented yet" << std::endl;
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inst.dump();
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exec->NOP(inst);
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}
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PC_not_affected = process_default_instruction(inst);
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// default:
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@ -215,7 +322,7 @@ void CPU::CPU_thread(void) {
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perf->instructionsInc();
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if (PC_not_affected == true) {
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register_bank->incPC();
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register_bank->incPC(incPCby2);
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}
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} // while(1)
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} // CPU_thread
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324
src/Execute.cpp
324
src/Execute.cpp
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@ -30,28 +30,39 @@ void Execute::AUIPC(Instruction &inst) {
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imm = inst.get_imm_U() << 12;
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new_pc = regs->getPC() + imm;
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regs->setPC(new_pc);
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regs->setValue(rd, new_pc);
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log->SC_log(Log::INFO) << "AUIPC x" << rd << " + PC -> PC (" << new_pc << ")" << endl;
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}
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void Execute::JAL(Instruction &inst) {
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void Execute::JAL(Instruction &inst, bool c_extension, int m_rd) {
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int32_t mem_addr = 0;
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int rd;
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int new_pc, old_pc;
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if (c_extension == false) {
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rd = inst.get_rd();
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mem_addr = inst.get_imm_J();
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old_pc = regs->getPC();
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new_pc = old_pc + mem_addr;
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regs->setPC(new_pc);
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old_pc = old_pc + 4;
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regs->setValue(rd, old_pc);
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} else {
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C_Instruction c_inst(inst.getInstr());
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rd = m_rd;
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mem_addr = c_inst.get_imm_J();
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old_pc = regs->getPC();
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new_pc = old_pc + mem_addr;
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regs->setPC(new_pc);
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old_pc = old_pc + 2;
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regs->setValue(rd, old_pc);
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}
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log->SC_log(Log::INFO) << dec << "JAL: x" << rd << " <- 0x" << hex << old_pc
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<< dec << " PC + " << mem_addr << " -> PC (0x"
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@ -226,21 +237,29 @@ void Execute::LH(Instruction &inst) {
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<< hex <<mem_addr << dec << ") -> x" << rd << endl;
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}
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void Execute::LW(Instruction &inst) {
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void Execute::LW(Instruction &inst, bool c_extension) {
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uint32_t mem_addr = 0;
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int rd, rs1;
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int32_t imm = 0;
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uint32_t data;
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if (c_extension == false) {
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rd = inst.get_rd();
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rs1 = inst.get_rs1();
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imm = inst.get_imm_I();
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} else {
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C_Instruction c_inst(inst.getInstr());
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rd = c_inst.get_rdp();
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rs1 = c_inst.get_rs1p();
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imm = c_inst.get_imm_L();
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}
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mem_addr = imm + regs->getValue(rs1);
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data = readDataMem(mem_addr, 4);
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regs->setValue(rd, data);
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log->SC_log(Log::INFO) << "LW: x" << rs1 << " + " << imm << " (@0x"
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log->SC_log(Log::INFO) << "C.LW: x" << rs1 << " + " << imm << " (@0x"
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<< hex <<mem_addr << dec << ") -> x" << rd << endl;
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}
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@ -338,14 +357,22 @@ void Execute::SW(Instruction &inst) {
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<< " (@0x" << hex << mem_addr << dec << ")" << endl;
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}
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void Execute::ADDI(Instruction &inst) {
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void Execute::ADDI(Instruction &inst, bool c_extension) {
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int rd, rs1;
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int32_t imm = 0;
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int32_t calc;
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if (c_extension == false) {
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rd = inst.get_rd();
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rs1 = inst.get_rs1();
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imm = inst.get_imm_I();
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} else {
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C_Instruction c_inst(inst.getInstr());
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rd = c_inst.get_rd();
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rs1 = rd;
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imm = c_inst.get_imm_I();
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}
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calc = regs->getValue(rs1) + imm;
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regs->setValue(rd, calc);
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@ -658,6 +685,20 @@ void Execute::AND(Instruction &inst) {
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<< "-> x" << rd << endl;
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}
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void Execute::FENCE(Instruction &inst) {
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log->SC_log(Log::INFO) << "FENCE" << endl;
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}
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void Execute::ECALL(Instruction &inst) {
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log->SC_log(Log::INFO) << "ECALL" << endl;
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std::cout << "ECALL Instruction called, stopping simulation" << endl;
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regs->dump();
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cout << "Simulation time " << sc_time_stamp() << endl;
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perf->dump();
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SC_REPORT_ERROR("Execute", "ECALL");
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}
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void Execute::CSRRW(Instruction &inst) {
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int rd, rs1;
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int csr;
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@ -667,13 +708,11 @@ void Execute::CSRRW(Instruction &inst) {
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rs1 = inst.get_rs1();
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csr = inst.get_csr();
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if (rd == 0) {
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return;
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}
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/* These operations must be atomical */
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if (rd != 0) {
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aux = regs->getCSR(csr);
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regs->setValue(rd, aux);
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}
|
||||
aux = regs->getValue(rs1);
|
||||
regs->setCSR(csr, aux);
|
||||
|
||||
|
|
@ -731,6 +770,267 @@ void Execute::CSRRC(Instruction &inst) {
|
|||
<< ". x" << rs1 << " & CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void Execute::CSRRWI(Instruction &inst) {
|
||||
int rd, rs1;
|
||||
int csr;
|
||||
uint32_t aux;
|
||||
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
csr = inst.get_csr();
|
||||
|
||||
|
||||
/* These operations must be atomical */
|
||||
if (rd != 0) {
|
||||
aux = regs->getCSR(csr);
|
||||
regs->setValue(rd, aux);
|
||||
}
|
||||
aux = rs1;
|
||||
regs->setCSR(csr, aux);
|
||||
|
||||
log->SC_log(Log::INFO) << "CSRRWI: CSR #" << csr << " -> x" << rd
|
||||
<< ". x" << rs1 << "-> CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void Execute::CSRRSI(Instruction &inst) {
|
||||
int rd, rs1;
|
||||
int csr;
|
||||
uint32_t bitmask, aux;
|
||||
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
csr = inst.get_csr();
|
||||
|
||||
if (rs1 == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* These operations must be atomical */
|
||||
aux = regs->getCSR(csr);
|
||||
regs->setValue(rd, aux);
|
||||
|
||||
bitmask = rs1;
|
||||
aux = aux | bitmask;
|
||||
regs->setCSR(csr, aux);
|
||||
|
||||
log->SC_log(Log::INFO) << "CSRRSI: CSR #" << csr << " -> x" << rd
|
||||
<< ". x" << rs1 << " & CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void Execute::CSRRCI(Instruction &inst) {
|
||||
int rd, rs1;
|
||||
int csr;
|
||||
uint32_t bitmask, aux;
|
||||
|
||||
rd = inst.get_rd();
|
||||
rs1 = inst.get_rs1();
|
||||
csr = inst.get_csr();
|
||||
|
||||
if (rs1 == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* These operations must be atomical */
|
||||
aux = regs->getCSR(csr);
|
||||
regs->setValue(rd, aux);
|
||||
|
||||
bitmask = rs1;
|
||||
aux = aux & ~bitmask;
|
||||
regs->setCSR(csr, aux);
|
||||
|
||||
log->SC_log(Log::INFO) << "CSRRCI: CSR #" << csr << " -> x" << rd
|
||||
<< ". x" << rs1 << " & CSR #" << csr << endl;
|
||||
}
|
||||
|
||||
void Execute::MRET(Instruction &inst) {
|
||||
uint32_t new_pc = 0;
|
||||
|
||||
new_pc = regs->getCSR(0x341);
|
||||
regs->setPC(new_pc);
|
||||
|
||||
log->SC_log(Log::INFO) << "MRET: PC <- 0x" << hex << new_pc << endl;
|
||||
}
|
||||
|
||||
void Execute::C_JR(Instruction &inst) {
|
||||
uint32_t mem_addr = 0;
|
||||
int rd, rs1;
|
||||
int new_pc, old_pc;
|
||||
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rd = 0;
|
||||
rs1 = c_inst.get_rs1();
|
||||
mem_addr = 0;
|
||||
|
||||
std::cout << "rs1 :" << rs1 << std::endl;
|
||||
old_pc = regs->getPC();
|
||||
regs->setValue(rd, old_pc + 4);
|
||||
|
||||
|
||||
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
|
||||
regs->setPC(new_pc);
|
||||
|
||||
log->SC_log(Log::INFO) << "JR: x" << dec << rd << " <- 0x" << hex << old_pc + 4
|
||||
<< " PC <- 0x" << hex << new_pc << endl;
|
||||
}
|
||||
|
||||
void Execute::C_MV(Instruction &inst) {
|
||||
int rd, rs1, rs2;
|
||||
uint32_t calc;
|
||||
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rd = c_inst.get_rd();
|
||||
rs1 = 0;
|
||||
rs2 = c_inst.get_rs2();
|
||||
|
||||
calc = regs->getValue(rs1) + regs->getValue(rs2);
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << "MV: x" << rs1 << " + x" << rs2 << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::C_LWSP(Instruction &inst) {
|
||||
uint32_t mem_addr = 0;
|
||||
int rd, rs1;
|
||||
int32_t imm = 0;
|
||||
uint32_t data;
|
||||
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rd = c_inst.get_rd();
|
||||
rs1 = c_inst.get_rs1();
|
||||
imm = c_inst.get_imm_LWSP();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = readDataMem(mem_addr, 4);
|
||||
regs->setValue(rd, data);
|
||||
|
||||
log->SC_log(Log::INFO) << "C.LWSP: x" << rs1 << " + " << imm << " (@0x"
|
||||
<< hex <<mem_addr << dec << ") -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::C_ADDI4SPN(Instruction &inst) {
|
||||
int rd, rs1;
|
||||
int32_t imm = 0;
|
||||
int32_t calc;
|
||||
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rd = c_inst.get_rdp();
|
||||
rs1 = 2;
|
||||
imm = c_inst.get_imm_ADDI4SPN();
|
||||
|
||||
calc = regs->getValue(rs1) + imm;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << dec << "ADDI4SPN: x" << rs1 << " + " << imm << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::C_ADDI16SP(Instruction &inst) {
|
||||
// addi x2, x2, nzimm[9:4]
|
||||
int rd, rs1;
|
||||
int32_t imm = 0;
|
||||
int32_t calc;
|
||||
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rd = 2;
|
||||
rs1 = 2;
|
||||
imm = c_inst.get_imm_ADDI16SP();
|
||||
|
||||
|
||||
calc = regs->getValue(rs1) + imm;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << dec << "ADDI16SP: x" << rs1 << " + " << imm << " -> x" << rd << endl;
|
||||
}
|
||||
|
||||
void Execute::C_SWSP(Instruction &inst) {
|
||||
// sw rs2, offset(x2)
|
||||
uint32_t mem_addr = 0;
|
||||
int rs1, rs2;
|
||||
int32_t imm = 0;
|
||||
uint32_t data;
|
||||
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rs1 = 2;
|
||||
rs2 = 2;
|
||||
imm = c_inst.get_imm_CSS();
|
||||
|
||||
mem_addr = imm + regs->getValue(rs1);
|
||||
data = regs->getValue(rs2);
|
||||
|
||||
writeDataMem(mem_addr, data, 4);
|
||||
|
||||
log->SC_log(Log::INFO) << "SWSP: x" << dec << rs2 << "(0x" << hex << data
|
||||
<< ") -> x" << dec << rs1 << " + " << imm
|
||||
<< " (@0x" << hex << mem_addr << dec << ")" << endl;
|
||||
|
||||
}
|
||||
|
||||
void Execute::C_BEQZ(Instruction &inst) {
|
||||
int rs1;
|
||||
int new_pc = 0;
|
||||
uint32_t val1;
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rs1 = c_inst.get_rs1p();
|
||||
val1 = regs->getValue(rs1);
|
||||
|
||||
if (val1 == 0) {
|
||||
new_pc = regs->getPC() + c_inst.get_imm_CB();
|
||||
regs->setPC(new_pc);
|
||||
} else {
|
||||
regs->incPC(true); //PC <- PC +2
|
||||
}
|
||||
|
||||
log->SC_log(Log::INFO) << "C.BEQZ: x" << rs1 << "(" << val1
|
||||
<< ") == 0? -> PC (" << new_pc << ")" << endl;
|
||||
}
|
||||
|
||||
void Execute::C_BNEZ(Instruction &inst) {
|
||||
int rs1;
|
||||
int new_pc = 0;
|
||||
uint32_t val1;
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rs1 = c_inst.get_rs1p();
|
||||
val1 = regs->getValue(rs1);
|
||||
|
||||
if (val1 != 0) {
|
||||
new_pc = regs->getPC() + c_inst.get_imm_CB();
|
||||
regs->setPC(new_pc);
|
||||
} else {
|
||||
regs->incPC(true); //PC <- PC +2
|
||||
}
|
||||
|
||||
log->SC_log(Log::INFO) << "C.BNEZ: x" << rs1 << "(" << val1
|
||||
<< ") == 0? -> PC (" << new_pc << ")" << endl;
|
||||
}
|
||||
|
||||
void Execute::C_LI(Instruction &inst) {
|
||||
|
||||
int rd, rs1;
|
||||
int32_t imm = 0;
|
||||
int32_t calc;
|
||||
|
||||
C_Instruction c_inst(inst.getInstr());
|
||||
|
||||
rd = c_inst.get_rd();
|
||||
rs1 = 0;
|
||||
imm = c_inst.get_imm_ADDI();
|
||||
|
||||
calc = regs->getValue(rs1) + imm;
|
||||
regs->setValue(rd, calc);
|
||||
|
||||
log->SC_log(Log::INFO) << dec << "LI: x" << rs1 << " + " << imm << " -> x" << rd << endl;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void Execute::NOP(Instruction &inst) {
|
||||
cout << endl;
|
||||
regs->dump();
|
||||
|
|
|
|||
|
|
@ -112,8 +112,64 @@ opCodes Instruction::decode() {
|
|||
return OP_AND;
|
||||
}
|
||||
} /* ADD */
|
||||
return OP_ERROR;
|
||||
case FENCE:
|
||||
return OP_FENCE;
|
||||
case ECALL: {
|
||||
switch (get_funct3()) {
|
||||
case ECALL_F3:
|
||||
switch(get_csr()) {
|
||||
case ECALL_F:
|
||||
return OP_ECALL;
|
||||
case EBREAK_F:
|
||||
return OP_EBREAK;
|
||||
case URET_F:
|
||||
return OP_URET;
|
||||
case SRET_F:
|
||||
return OP_SRET;
|
||||
case MRET_F:
|
||||
return OP_MRET;
|
||||
}
|
||||
break;
|
||||
case CSRRW:
|
||||
return OP_CSRRW;
|
||||
break;
|
||||
case CSRRS:
|
||||
return OP_CSRRS;
|
||||
break;
|
||||
case CSRRC:
|
||||
return OP_CSRRC;
|
||||
break;
|
||||
case CSRRWI:
|
||||
return OP_CSRRWI;
|
||||
break;
|
||||
case CSRRSI:
|
||||
return OP_CSRRSI;
|
||||
break;
|
||||
case CSRRCI:
|
||||
return OP_CSRRCI;
|
||||
break;
|
||||
}
|
||||
}
|
||||
default:
|
||||
return OP_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
extension_t Instruction::check_extension() {
|
||||
if (m_instr.range(1,0) == 0b11) {
|
||||
return BASE_EXTENSION;
|
||||
} else if (m_instr.range(1,0) == 0b00) {
|
||||
return C_EXTENSION;
|
||||
} else if (m_instr.range(1,0) == 0b01) {
|
||||
return C_EXTENSION;
|
||||
} else if (m_instr.range(1,0) == 0b10) {
|
||||
return C_EXTENSION;
|
||||
} else if (m_instr.range(6,0) == 0b0110011) {
|
||||
return M_EXTENSION;
|
||||
} else if (m_instr.range(6,0) == 0b0101111) {
|
||||
return A_EXTENSION;
|
||||
} else {
|
||||
return UNKNOWN_EXTENSION;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,8 @@
|
|||
|
||||
Registers::Registers() {
|
||||
|
||||
memset(register_bank, 0, sizeof(int32_t)*32); // 32 registers of 32 bits each
|
||||
memset(register_bank, 0, sizeof(uint32_t)*32); // 32 registers of 32 bits each
|
||||
memset(CSR, 0, sizeof(uint32_t)*4096);
|
||||
perf = Performance::getInstance();
|
||||
|
||||
register_bank[sp] = 1024-1; // SP points to end of memory
|
||||
|
|
|
|||
Loading…
Reference in New Issue