From acf38332d52c6a4b11ab3d2f298664038574d5ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=C3=A0rius=20Mont=C3=B3n?= Date: Fri, 8 Jul 2022 12:02:30 +0200 Subject: [PATCH] cast to u32 --- inc/BASE_ISA.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/inc/BASE_ISA.h b/inc/BASE_ISA.h index 5fb79df..9e21d9e 100644 --- a/inc/BASE_ISA.h +++ b/inc/BASE_ISA.h @@ -10,6 +10,7 @@ #define Execute_H #define SC_INCLUDE_DYNAMIC_PROCESSES +#include #include "systemc" #include "tlm.h" @@ -175,6 +176,12 @@ namespace riscv_tlm { */ using extension_base::extension_base; + /** + * @brief Deduce signed type for T type + */ + using signed_T = typename std::make_signed::type; + + /** * @brief Access to funct7 field * @return funct7 field @@ -348,7 +355,7 @@ namespace riscv_tlm { rd = this->get_rd(); imm = get_imm_U() << 12; - this->regs->setValue(rd, static_cast(imm)); + this->regs->setValue(rd, static_cast(imm)); this->logger->debug("{} ns. PC: 0x{:x}. LUI: x{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), this->regs->getPC(), @@ -360,11 +367,11 @@ namespace riscv_tlm { bool Exec_AUIPC() const { unsigned int rd; std::uint32_t imm; - std::uint32_t new_pc; + T new_pc; rd = this->get_rd(); imm = get_imm_U() << 12; - new_pc = static_cast(this->regs->getPC() + imm); + new_pc = static_cast(this->regs->getPC() + imm); this->regs->setValue(rd, new_pc); @@ -379,7 +386,7 @@ namespace riscv_tlm { bool Exec_JAL() const { std::int32_t mem_addr; unsigned int rd; - std::uint32_t new_pc, old_pc; + T new_pc, old_pc; rd = this->get_rd(); mem_addr = get_imm_J(); @@ -401,7 +408,7 @@ namespace riscv_tlm { bool Exec_JALR() { std::uint32_t mem_addr; unsigned int rd, rs1; - std::uint32_t new_pc, old_pc; + T new_pc, old_pc; rd = this->get_rd(); rs1 = this->get_rs1();