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Màrius Montón 2022-09-30 16:23:05 +02:00
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@ -7,7 +7,7 @@ This is another RISC-V ISA simulator, this is coded in SystemC + TLM-2.
It supports RV32IMAC and RV64IMAC Instruction set. It supports RV32IMAC and RV64IMAC Instruction set.
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