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risc-v-tlm
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add TRACE support to TODO list

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Màrius Montón 2022-10-06 08:33:47 +02:00
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README.md
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@ -105,6 +105,7 @@ Task to do:
* [ ] Improve structure and modules hierarchy
* [X] Add 64 architecture (RV64I)
* [x] Debug capabilities
* [ ] Add [Trace v2.0](https://github.com/riscv-non-isa/riscv-trace-spec) support
## Compile
In order to compile the project you need SystemC-2.3.2 installed in your system.
@ -147,7 +148,7 @@ make
### Arguments
-L loglevel: 3 for detailed (INFO) log, 0 to ERROR log level
-f filename .hex filename to use
-f filename .hex binary filename to use
-D Enter in Debug mode, simulator starts gdb server (Beta)