diff --git a/inc/BusCtrl.h b/inc/BusCtrl.h
index 3ef60d2..5f06458 100644
--- a/inc/BusCtrl.h
+++ b/inc/BusCtrl.h
@@ -72,7 +72,7 @@ public:
 	 * @brief constructor
 	 * @param name module's name
 	 */
-	explicit BusCtrl(sc_core::sc_module_name name);
+	explicit BusCtrl(sc_core::sc_module_name const &name);
 
 	/**
 	 * @brief TLM-2 blocking mechanism
@@ -83,7 +83,6 @@ public:
 			sc_core::sc_time &delay);
 
 private:
-	Log *log;
 
 	bool instr_direct_mem_ptr(tlm::tlm_generic_payload&,
 			tlm::tlm_dmi &dmi_data);
diff --git a/inc/CPU.h b/inc/CPU.h
index 033cb1e..48a0c60 100644
--- a/inc/CPU.h
+++ b/inc/CPU.h
@@ -54,7 +54,7 @@ public:
 	 * @param PC   Program Counter initialize value
 	 * @param debug To start debugging
 	 */
-	CPU(sc_core::sc_module_name name, uint32_t PC, bool debug);
+	CPU(sc_core::sc_module_name const &name, uint32_t PC, bool debug);
 
 	/**
 	 * @brief Destructor
diff --git a/src/BusCtrl.cpp b/src/BusCtrl.cpp
index fb4cb76..712cfb4 100644
--- a/src/BusCtrl.cpp
+++ b/src/BusCtrl.cpp
@@ -9,13 +9,12 @@
 #include "BusCtrl.h"
 
 SC_HAS_PROCESS(BusCtrl);
-BusCtrl::BusCtrl(sc_core::sc_module_name const name) :
+BusCtrl::BusCtrl(sc_core::sc_module_name const &name) :
 		sc_module(name), cpu_instr_socket("cpu_instr_socket"), cpu_data_socket(
 				"cpu_data_socket"), memory_socket("memory_socket"), trace_socket(
 				"trace_socket") {
 	cpu_instr_socket.register_b_transport(this, &BusCtrl::b_transport);
 	cpu_data_socket.register_b_transport(this, &BusCtrl::b_transport);
-	log = Log::getInstance();
 	cpu_instr_socket.register_get_direct_mem_ptr(this,
 			&BusCtrl::instr_direct_mem_ptr);
 	memory_socket.register_invalidate_direct_mem_ptr(this,
diff --git a/src/CPU.cpp b/src/CPU.cpp
index dc057e0..ed3f038 100644
--- a/src/CPU.cpp
+++ b/src/CPU.cpp
@@ -8,7 +8,7 @@
 #include "CPU.h"
 
 SC_HAS_PROCESS(CPU);
-CPU::CPU(sc_core::sc_module_name const name, uint32_t PC, bool debug) :
+CPU::CPU(sc_core::sc_module_name const &name, uint32_t PC, bool debug) :
 		sc_module(name), instr_bus("instr_bus"), default_time(10,
 				sc_core::SC_NS), INSTR(0) {
 	register_bank = new Registers();
diff --git a/src/Simulator.cpp b/src/Simulator.cpp
index d47a8d9..a0eb4cc 100644
--- a/src/Simulator.cpp
+++ b/src/Simulator.cpp
@@ -30,14 +30,15 @@ bool debug_session = false;
  *
  * @brief Top simulation entity
  */
-SC_MODULE(Simulator) {
-	CPU *cpu;
+class Simulator : sc_core::sc_module {
+public:
+    CPU *cpu;
 	Memory *MainMemory;
 	BusCtrl *Bus;
 	Trace *trace;
 	Timer *timer;
 
-	SC_CTOR(Simulator) {
+	explicit Simulator(sc_core::sc_module_name const &name): sc_module(name) {
 		uint32_t start_PC;
 
 		MainMemory = new Memory("Main_Memory", filename);