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risc-v-tlm
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Add missing colon for BASIC instruction log 

Better for analysis the RISC-V code stream
This commit is contained in:
hsufit 2021-08-20 16:19:26 +08:00 committed by GitHub
parent b4461cab61
commit cc5a14e1cd
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 7 additions and 7 deletions
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14
src/BASE_ISA.cpp
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@ -91,7 +91,7 @@ bool BASE_ISA::Exec_LUI() const {
regs->setValue(rd, static_cast<int32_t>(imm)); regs->setValue(rd, static_cast<int32_t>(imm));
if (log->getLogLevel() >= Log::INFO) { if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "LUI x" << std::dec << rd << " <- 0x" << std::hex log->SC_log(Log::INFO) << "LUI: x" << std::dec << rd << " <- 0x" << std::hex
<< imm << "\n"; << imm << "\n";
} }
@ -110,7 +110,7 @@ bool BASE_ISA::Exec_AUIPC() const {
regs->setValue(rd, new_pc); regs->setValue(rd, new_pc);
if (log->getLogLevel() >= Log::INFO) { if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "AUIPC x" << std::dec << rd << " <- 0x" log->SC_log(Log::INFO) << "AUIPC: x" << std::dec << rd << " <- 0x"
<< std::hex << imm << " + PC (0x" << new_pc << ")" << "\n"; << std::hex << imm << " + PC (0x" << new_pc << ")" << "\n";
} }
@ -179,7 +179,7 @@ bool BASE_ISA::Exec_BEQ() const {
} }
if (log->getLogLevel() >= Log::INFO) { if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BEQ x" << std::dec << rs1 << "(0x" << std::hex log->SC_log(Log::INFO) << "BEQ: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") == x" << std::dec << rs2 << "(0x" << regs->getValue(rs1) << ") == x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex << std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << "\n"; << new_pc << ")" << std::dec << "\n";
@ -232,7 +232,7 @@ bool BASE_ISA::Exec_BLT() const {
} }
if (log->getLogLevel() >= Log::INFO) { if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BLT x" << std::dec << rs1 << "(0x" << std::hex log->SC_log(Log::INFO) << "BLT: x" << std::dec << rs1 << "(0x" << std::hex
<< (int32_t) regs->getValue(rs1) << ") < x" << std::dec << rs2 << (int32_t) regs->getValue(rs1) << ") < x" << std::dec << rs2
<< "(0x" << std::hex << (int32_t) regs->getValue(rs2) << "(0x" << std::hex << (int32_t) regs->getValue(rs2)
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec << ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
@ -257,7 +257,7 @@ bool BASE_ISA::Exec_BGE() const {
} }
if (log->getLogLevel() >= Log::INFO) { if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BGE x" << std::dec << rs1 << "(0x" << std::hex log->SC_log(Log::INFO) << "BGE: x" << std::dec << rs1 << "(0x" << std::hex
<< (int32_t) regs->getValue(rs1) << ") > x" << std::dec << rs2 << (int32_t) regs->getValue(rs1) << ") > x" << std::dec << rs2
<< "(0x" << std::hex << (int32_t) regs->getValue(rs2) << "(0x" << std::hex << (int32_t) regs->getValue(rs2)
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec << ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
@ -283,7 +283,7 @@ bool BASE_ISA::Exec_BLTU() const {
} }
if (log->getLogLevel() >= Log::INFO) { if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BLTU x" << std::dec << rs1 << "(0x" << std::hex log->SC_log(Log::INFO) << "BLTU: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") < x" << std::dec << rs2 << "(0x" << regs->getValue(rs1) << ") < x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex << std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << "\n"; << new_pc << ")" << std::dec << "\n";
@ -307,7 +307,7 @@ bool BASE_ISA::Exec_BGEU() const {
} }
if (log->getLogLevel() >= Log::INFO) { if (log->getLogLevel() >= Log::INFO) {
log->SC_log(Log::INFO) << "BGEU x" << std::dec << rs1 << "(0x" << std::hex log->SC_log(Log::INFO) << "BGEU: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") > x" << std::dec << rs2 << "(0x" << regs->getValue(rs1) << ") > x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex << std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << "\n"; << new_pc << ")" << std::dec << "\n";