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risc-v-tlm
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No nested namespaces

This commit is contained in:
mariusmonton 2021-11-29 22:21:20 +01:00
parent 8d3d3bb35b
commit d430b23fc6
4 changed files with 158 additions and 152 deletions
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4
inc/Timer.h
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@ -21,7 +21,8 @@
#include "BusCtrl.h" #include "BusCtrl.h"
namespace riscv_tlm::peripherals { namespace riscv_tlm {
namespace peripherals {
/** /**
* @brief Simple timer peripheral * @brief Simple timer peripheral
* *
@ -67,5 +68,6 @@ namespace riscv_tlm::peripherals {
sc_dt::sc_uint<64> m_mtimecmp; /**< mtimecmp register */ sc_dt::sc_uint<64> m_mtimecmp; /**< mtimecmp register */
sc_core::sc_event timer_event; /**< event */ sc_core::sc_event timer_event; /**< event */
}; };
}
} }
#endif #endif

6
inc/Trace.h
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@ -19,8 +19,9 @@
#include "tlm.h" #include "tlm.h"
#include "tlm_utils/simple_target_socket.h" #include "tlm_utils/simple_target_socket.h"
namespace riscv_tlm::peripherals { namespace riscv_tlm {
/** namespace peripherals {
/**
* @brief Simple trace peripheral * @brief Simple trace peripheral
* *
* This peripheral outputs to cout any character written to its unique register * This peripheral outputs to cout any character written to its unique register
@ -60,5 +61,6 @@ namespace riscv_tlm::peripherals {
int ptMaster{}; int ptMaster{};
int xtermPid{}; int xtermPid{};
}; };
}
} }
#endif #endif

5
src/Timer.cpp
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@ -9,7 +9,8 @@
#include <cstdint> #include <cstdint>
#include "Timer.h" #include "Timer.h"
namespace riscv_tlm::peripherals { namespace riscv_tlm {
namespace peripherals {
SC_HAS_PROCESS(Timer); SC_HAS_PROCESS(Timer);
Timer::Timer(sc_core::sc_module_name const &name) : Timer::Timer(sc_core::sc_module_name const &name) :
@ -101,5 +102,5 @@ namespace riscv_tlm::peripherals {
trans.set_response_status(tlm::TLM_OK_RESPONSE); trans.set_response_status(tlm::TLM_OK_RESPONSE);
} }
}
} }

5
src/Trace.cpp
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@ -20,7 +20,8 @@
#include "Trace.h" #include "Trace.h"
namespace riscv_tlm::peripherals { namespace riscv_tlm {
namespace peripherals {
void Trace::xtermLaunch(char *slaveName) const { void Trace::xtermLaunch(char *slaveName) const {
char *arg; char *arg;
@ -112,5 +113,5 @@ namespace riscv_tlm::peripherals {
trans.set_response_status(tlm::TLM_OK_RESPONSE); trans.set_response_status(tlm::TLM_OK_RESPONSE);
} }
}
} }