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risc-v-tlm
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if condition clarified

This commit is contained in:
Màrius Montón 2019-09-24 11:12:47 +02:00
parent 70e9313025
commit d575410a06
1 changed files with 1 additions and 2 deletions
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3
src/CPU.cpp
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@ -40,8 +40,7 @@ bool CPU::cpu_process_IRQ() {
if (interrupt == true) {
csr_temp = register_bank->getCSR(CSR_MSTATUS);
if (csr_temp & MSTATUS_MIE) {
} else {
if ( (csr_temp & MSTATUS_MIE) == 0) {
log->SC_log(Log::DEBUG) << "interrupt delayed" << endl;
return ret_value;
}