diff --git a/src/CPU.cpp b/src/CPU.cpp
index d5ce378..ff271fe 100644
--- a/src/CPU.cpp
+++ b/src/CPU.cpp
@@ -442,7 +442,7 @@ bool CPU::process_base_instruction(Instruction &inst) {
 		//sc_stop();
 		break;
 	}
-
+     
 	return PC_not_affected;
 }
 
@@ -483,7 +483,6 @@ void CPU::CPU_thread(void) {
 			/* if memory_offset at Memory module is set, this won't work */
 			memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
 		} else {
-			cout << "No DMI access" << endl;
 			trans->set_address(register_bank->getPC());
 			instr_bus->b_transport(*trans, delay);
 
@@ -491,10 +490,13 @@ void CPU::CPU_thread(void) {
 				SC_REPORT_ERROR("CPU base", "Read memory");
 			}
 
-			dmi_ptr_valid = instr_bus->get_direct_mem_ptr(*trans, dmi_data);
-			if (dmi_ptr_valid) {
-				dmi_ptr = dmi_data.get_dmi_ptr();
-			}
+			if (trans->is_dmi_allowed()) {
+                dmi_ptr_valid = instr_bus->get_direct_mem_ptr(*trans, dmi_data);
+                if (dmi_ptr_valid) {
+                    std::cout << "Get DMI_PTR " << std::endl;
+                    dmi_ptr = dmi_data.get_dmi_ptr();
+                }
+            }
 		}
 
 		perf->codeMemoryRead();
diff --git a/src/Memory.cpp b/src/Memory.cpp
index 674f22d..9326774 100644
--- a/src/Memory.cpp
+++ b/src/Memory.cpp
@@ -49,7 +49,6 @@ void Memory::b_transport( tlm::tlm_generic_payload& trans, sc_time& delay )
   unsigned char*   byt = trans.get_byte_enable_ptr();
   unsigned int     wid = trans.get_streaming_width();
 
-
   adr = adr - memory_offset;
   // Obliged to check address range and check for unsupported features,
   //   i.e. byte enables, streaming, and bursts
@@ -101,6 +100,10 @@ void Memory::b_transport( tlm::tlm_generic_payload& trans, sc_time& delay )
 bool Memory::get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
                                 tlm::tlm_dmi& dmi_data)
 {
+  if (memory_offset != 0) {
+    return false;
+  }
+    
   // Permit read and write access
   dmi_data.allow_read_write();