colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Use spdlog library as logger.

This commit is contained in:
Màrius Montón 2021-11-25 12:11:18 +01:00
parent 6ff0da0313
commit e6bf4e30a4
No known key found for this signature in database
GPG Key ID: FA199E7A752699F0
17 changed files with 233 additions and 441 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
inc/A_extension.h
View File

@ -13,7 +13,6 @@
#include <set>
#include "Log.h"
#include "Registers.h"
#include "MemoryInterface.h"
#include "extension_base.h"

2
inc/BASE_ISA.h
View File

@ -22,8 +22,6 @@
#include "M_extension.h"
#include "A_extension.h"
#include "Registers.h"
#include "Log.h"
typedef enum {
OP_LUI,

2
inc/BusCtrl.h
View File

@ -20,8 +20,6 @@
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
#include "Log.h"
/**
* Memory mapped Trace peripheral address
*/

3
inc/CPU.h
View File

@ -21,7 +21,6 @@
#include "MemoryInterface.h"
#include "BASE_ISA.h"
#include "Registers.h"
#include "Log.h"
#include "Instruction.h"
#include "C_extension.h"
#include "M_extension.h"
@ -65,7 +64,7 @@ public:
private:
Registers *register_bank;
Performance *perf;
// Log *log;
std::shared_ptr<spdlog::logger> logger;
Instruction *inst;
C_extension *c_inst;
M_extension *m_inst;

173
inc/Log.h
View File

@ -1,173 +0,0 @@
/**
* https://www.drdobbs.com/cpp/logging-in-c/201804215?pgno=2
*/
#ifndef __LOG_H__
#define __LOG_H__
#include <sstream>
#include <string>
#include <stdio.h>
inline std::string NowTime();
enum TLogLevel {logERROR, logWARNING, logINFO, logDEBUG, logDEBUG1, logDEBUG2, logDEBUG3, logDEBUG4};
template <typename T>
class Log
{
public:
Log();
virtual ~Log();
std::ostringstream& Get(TLogLevel level = logINFO);
public:
static TLogLevel& ReportingLevel();
static std::string ToString(TLogLevel level);
static TLogLevel FromString(const std::string& level);
protected:
std::ostringstream os;
private:
Log(const Log&);
Log& operator =(const Log&);
};
template <typename T>
Log<T>::Log()
{
}
template <typename T>
std::ostringstream& Log<T>::Get(TLogLevel level)
{
os << std::string(level > logDEBUG ? level - logDEBUG : 0, '\t');
return os;
}
template <typename T>
Log<T>::~Log()
{
T::Output(os.str());
}
template <typename T>
TLogLevel& Log<T>::ReportingLevel()
{
static TLogLevel reportingLevel = logDEBUG4;
return reportingLevel;
}
template <typename T>
std::string Log<T>::ToString(TLogLevel level)
{
static const char* const buffer[] = {"ERROR", "WARNING", "INFO", "DEBUG", "DEBUG1", "DEBUG2", "DEBUG3", "DEBUG4"};
return buffer[level];
}
template <typename T>
TLogLevel Log<T>::FromString(const std::string& level)
{
if (level == "DEBUG4")
return logDEBUG4;
if (level == "DEBUG3")
return logDEBUG3;
if (level == "DEBUG2")
return logDEBUG2;
if (level == "DEBUG1")
return logDEBUG1;
if (level == "DEBUG")
return logDEBUG;
if (level == "INFO")
return logINFO;
if (level == "WARNING")
return logWARNING;
if (level == "ERROR")
return logERROR;
Log<T>().Get(logWARNING) << "Unknown logging level '" << level << "'. Using INFO level as default.";
return logINFO;
}
class Output2FILE
{
public:
static FILE*& Stream();
static void Output(const std::string& msg);
};
inline FILE*& Output2FILE::Stream()
{
static FILE* pStream = stderr;
return pStream;
}
inline void Output2FILE::Output(const std::string& msg)
{
FILE* pStream = Stream();
if (!pStream)
return;
fprintf(pStream, "%s", msg.c_str());
fflush(pStream);
}
#if defined(WIN32) || defined(_WIN32) || defined(__WIN32__)
# if defined (BUILDING_FILELOG_DLL)
# define FILELOG_DECLSPEC __declspec (dllexport)
# elif defined (USING_FILELOG_DLL)
# define FILELOG_DECLSPEC __declspec (dllimport)
# else
# define FILELOG_DECLSPEC
# endif // BUILDING_DBSIMPLE_DLL
#else
# define FILELOG_DECLSPEC
#endif // _WIN32
class FILELOG_DECLSPEC FILELog : public Log<Output2FILE> {};
//typedef Log<Output2FILE> FILELog;
#ifndef FILELOG_MAX_LEVEL
#define FILELOG_MAX_LEVEL logDEBUG4
#endif
#define FILE_LOG(level) \
if (level > FILELOG_MAX_LEVEL) ;\
else if (level > FILELog::ReportingLevel() || !Output2FILE::Stream()) ; \
else FILELog().Get(level)
#if defined(WIN32) || defined(_WIN32) || defined(__WIN32__)
#include <windows.h>
inline std::string NowTime()
{
const int MAX_LEN = 200;
char buffer[MAX_LEN];
if (GetTimeFormatA(LOCALE_USER_DEFAULT, 0, 0,
"HH':'mm':'ss", buffer, MAX_LEN) == 0)
return "Error in NowTime()";
char result[100] = {0};
static DWORD first = GetTickCount();
std::sprintf(result, "%s.%03ld", buffer, (long)(GetTickCount() - first) % 1000);
return result;
}
#else
#include <sys/time.h>
inline std::string NowTime()
{
char buffer[11];
time_t t;
time(&t);
tm r = {0};
strftime(buffer, sizeof(buffer), "%X", localtime_r(&t, &r));
struct timeval tv;
gettimeofday(&tv, 0);
char result[100] = {0};
std::sprintf(result, "%s.%03ld", buffer, (long)tv.tv_usec / 1000);
return result;
}
#endif //WIN32
#endif //__LOG_H__

1
inc/M_extension.h
View File

@ -12,7 +12,6 @@
#include "systemc"
#include "extension_base.h"
#include "Log.h"
#include "Registers.h"
typedef enum {

6
inc/Memory.h
View File

@ -19,8 +19,8 @@
#include "tlm.h"
#include "tlm_utils/simple_target_socket.h"
#include "Log.h"
#include "spdlog/spdlog.h"
#include "spdlog/sinks/basic_file_sink.h"
/**
* @brief Basic TLM-2 memory
*/
@ -71,7 +71,7 @@ private:
/**
* @brief Log class
*/
// Log *log;
std::shared_ptr<spdlog::logger> logger;
/**
* @brief Program counter (PC) read from hex file

1
inc/MemoryInterface.h
View File

@ -16,7 +16,6 @@
#include "tlm_utils/tlm_quantumkeeper.h"
#include "memory.h"
#include "Log.h"
/**
* @brief Memory Interface

6
inc/extension_base.h
View File

@ -13,9 +13,11 @@
#include "Instruction.h"
#include "Registers.h"
#include "Log.h"
#include "MemoryInterface.h"
#include "spdlog/spdlog.h"
#include "spdlog/sinks/basic_file_sink.h"
#define EXCEPTION_CAUSE_INSTRUCTION_MISALIGN 0
#define EXCEPTION_CAUSE_INSTRUCTION_ACCESS 1
#define EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION 2
@ -51,8 +53,8 @@ protected:
sc_dt::sc_uint<32> m_instr;
Registers *regs;
Performance *perf;
// Log *log;
MemoryInterface *mem_intf;
std::shared_ptr<spdlog::logger> logger;
};
#endif /* INC_EXTENSION_BASE_H_ */

29
src/A_extension.cpp
View File

@ -75,8 +75,8 @@ bool A_extension::Exec_A_LR() {
TLB_reserve(mem_addr);
FILE_LOG(logINFO) << std::dec << "LR.W: x" << rs1 << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.LR.W: x{:d}(0x{:x}) -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, mem_addr, rd, data);
return true;
}
@ -100,9 +100,8 @@ bool A_extension::Exec_A_SC() {
regs->setValue(rd, 1); // SC writes nonzero on failure
}
FILE_LOG(logINFO) << std::dec << "SC.W: (@0x" << std::hex << mem_addr
<< std::dec << ") <- x" << rs2 << std::hex << "(0x" << data << ")"
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.SC.W: (0x{:x}) <- x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(),
mem_addr, rs2, data);
return true;
}
@ -130,7 +129,8 @@ bool A_extension::Exec_A_AMOSWAP() {
mem_intf->writeDataMem(mem_addr, aux, 4);
FILE_LOG(logINFO) << std::dec << "AMOSWAP " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOSWAP");
return true;
}
@ -155,7 +155,7 @@ bool A_extension::Exec_A_AMOADD() {
mem_intf->writeDataMem(mem_addr, data, 4);
FILE_LOG(logINFO) << std::dec << "AMOADD " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOADD");
return true;
}
@ -181,7 +181,7 @@ bool A_extension::Exec_A_AMOXOR() {
mem_intf->writeDataMem(mem_addr, data, 4);
FILE_LOG(logINFO) << std::dec << "AMOXOR " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOXOR");
return true;
}
@ -206,7 +206,7 @@ bool A_extension::Exec_A_AMOAND() {
mem_intf->writeDataMem(mem_addr, data, 4);
FILE_LOG(logINFO) << std::dec << "AMOAND " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOAND");
return true;
}
@ -232,7 +232,8 @@ bool A_extension::Exec_A_AMOOR() {
mem_intf->writeDataMem(mem_addr, data, 4);
FILE_LOG(logINFO) << std::dec << "AMOOR " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOOR");
return true;
}
bool A_extension::Exec_A_AMOMIN() {
@ -260,7 +261,7 @@ bool A_extension::Exec_A_AMOMIN() {
mem_intf->writeDataMem(mem_addr, aux, 4);
FILE_LOG(logINFO) << std::dec << "AMOMIN " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOMIN");
return true;
}
@ -289,7 +290,7 @@ bool A_extension::Exec_A_AMOMAX() {
mem_intf->writeDataMem(mem_addr, aux, 4);
FILE_LOG(logINFO) << std::dec << "AMOMAX " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOMAX");
return true;
}
@ -318,7 +319,7 @@ bool A_extension::Exec_A_AMOMINU() {
mem_intf->writeDataMem(mem_addr, aux, 4);
FILE_LOG(logINFO) << std::dec << "AMOMINU " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOMINU");
return true;
}
@ -347,7 +348,7 @@ bool A_extension::Exec_A_AMOMAXU() {
mem_intf->writeDataMem(mem_addr, aux, 4);
FILE_LOG(logINFO) << std::dec << "AMOMAXU " << std::endl;
logger->debug("{} ns. PC: 0x{:x}. A.AMOMAXU");
return true;
}

252
src/BASE_ISA.cpp
View File

@ -6,6 +6,9 @@
*/
// SPDX-License-Identifier: GPL-3.0-or-later
#include "spdlog/spdlog.h"
#include "BASE_ISA.h"
typedef enum {
@ -90,8 +93,8 @@ bool BASE_ISA::Exec_LUI() {
imm = get_imm_U() << 12;
regs->setValue(rd, imm);
FILE_LOG(logINFO) << "LUI x" << std::dec << rd << " <- 0x" << std::hex
<< imm << std::endl;
logger->debug("{} ns. PC: 0x{:x}. LUI: x{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, imm);
return true;
}
@ -107,8 +110,8 @@ bool BASE_ISA::Exec_AUIPC() {
regs->setValue(rd, new_pc);
FILE_LOG(logINFO) << "AUIPC x" << std::dec << rd << " <- 0x"
<< std::hex << imm << " + PC (0x" << new_pc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. AUIPC: x{:d} <- 0x{:x} + PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, imm, new_pc);
return true;
}
@ -128,9 +131,8 @@ bool BASE_ISA::Exec_JAL() {
old_pc = old_pc + 4;
regs->setValue(rd, old_pc);
FILE_LOG(logINFO) << "JAL: x" << std::dec << rd << " <- 0x" << std::hex
<< old_pc << std::dec << ". PC + 0x" << std::hex << mem_addr
<< " -> PC (0x" << new_pc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. JAL: x{:d} <- 0x{:x}. PC + 0x{:x} -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc, mem_addr, new_pc);
return true;
}
@ -150,10 +152,10 @@ bool BASE_ISA::Exec_JALR() {
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
regs->setPC(new_pc);
FILE_LOG(logINFO) << "JALR: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc + 4 << " PC <- 0x" << new_pc << std::endl;
logger->debug("{} ns. PC: 0x{:x}. JALR: x{:d} <- 0x{:x}. PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc + 4, new_pc);
return true;
return true;
}
bool BASE_ISA::Exec_BEQ() {
@ -171,11 +173,8 @@ bool BASE_ISA::Exec_BEQ() {
new_pc = regs->getPC();
}
FILE_LOG(logINFO) << "BEQ x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") == x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << std::endl;
logger->debug("{} ns. PC: 0x{:x}. BEQ: x{:d}(0x{:x}) == x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -199,10 +198,8 @@ bool BASE_ISA::Exec_BNE() {
new_pc = regs->getPC();
}
FILE_LOG(logINFO) << "BNE: x" << std::dec << rs1 << "(0x" << std::hex
<< val1 << ") == x" << std::dec << rs2 << "(0x" << std::hex << val2
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. BNE: x{:d}(0x{:x}) != x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, rs2, val2, new_pc);
return true;
}
@ -221,11 +218,8 @@ bool BASE_ISA::Exec_BLT() {
regs->incPC();
}
FILE_LOG(logINFO) << "BLT x" << std::dec << rs1 << "(0x" << std::hex
<< (int32_t) regs->getValue(rs1) << ") < x" << std::dec << rs2
<< "(0x" << std::hex << (int32_t) regs->getValue(rs2)
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. BLT: x{:d}(0x{:x}) < x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -244,11 +238,8 @@ bool BASE_ISA::Exec_BGE() {
regs->incPC();
}
FILE_LOG(logINFO) << "BGE x" << std::dec << rs1 << "(0x" << std::hex
<< (int32_t) regs->getValue(rs1) << ") > x" << std::dec << rs2
<< "(0x" << std::hex << (int32_t) regs->getValue(rs2)
<< ")? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. BGE: x{:d}(0x{:x}) > x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -268,10 +259,8 @@ bool BASE_ISA::Exec_BLTU() {
new_pc = regs->getPC();
}
FILE_LOG(logINFO) << "BLTU x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") < x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << std::endl;
logger->debug("{} ns. PC: 0x{:x}. BLTU: x{:d}(0x{:x}) < x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -290,10 +279,8 @@ bool BASE_ISA::Exec_BGEU() {
regs->incPC();
}
FILE_LOG(logINFO) << "BGEU x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") > x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ")? -> PC (0x" << std::hex
<< new_pc << ")" << std::dec << std::endl;
logger->debug("{} ns. PC: 0x{:x}. BGEU: x{:d}(0x{:x}) > x{:d}(0x{:x}) -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true;
}
@ -312,8 +299,8 @@ bool BASE_ISA::Exec_LB() {
data = mem_intf->readDataMem(mem_addr, 1);
regs->setValue(rd, data);
FILE_LOG(logINFO) << "LB: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. LB: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -332,8 +319,8 @@ bool BASE_ISA::Exec_LH() {
data = mem_intf->readDataMem(mem_addr, 2);
regs->setValue(rd, data);
FILE_LOG(logINFO) << "LH: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. LH: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -352,10 +339,9 @@ bool BASE_ISA::Exec_LW() {
data = mem_intf->readDataMem(mem_addr, 4);
regs->setValue(rd, data);
FILE_LOG(logINFO) << std::dec << "LW: x" << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + " << std::dec << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::hex
<< " (0x" << data << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. LW: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -373,8 +359,9 @@ bool BASE_ISA::Exec_LBU() {
data = mem_intf->readDataMem(mem_addr, 1);
regs->setValue(rd, data);
FILE_LOG(logINFO) << "LBU: x" << rs1 << " + " << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. LBU: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -392,9 +379,8 @@ bool BASE_ISA::Exec_LHU() {
data = mem_intf->readDataMem(mem_addr, 2);
regs->setValue(rd, data);
FILE_LOG(logINFO) << "LHU: x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ") -> x" << rd
<< "(0x" << std::hex << data << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. LHU: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd);
return true;
}
@ -414,9 +400,8 @@ bool BASE_ISA::Exec_SB() {
mem_intf->writeDataMem(mem_addr, data, 1);
FILE_LOG(logINFO) << "SB: x" << std::dec << rs2 << " -> x" << rs1
<< " + 0x" << std::hex << imm << " (@0x" << std::hex << mem_addr
<< std::dec << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SB: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, rs1, imm, mem_addr);
return true;
}
@ -436,9 +421,8 @@ bool BASE_ISA::Exec_SH() {
mem_intf->writeDataMem(mem_addr, data, 2);
FILE_LOG(logINFO) << "SH: x" << std::dec << rs2 << " -> x" << rs1
<< " + 0x" << std::hex << imm << " (@0x" << std::hex << mem_addr
<< std::dec << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SH: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, rs1, imm, mem_addr);
return true;
}
@ -458,9 +442,9 @@ bool BASE_ISA::Exec_SW() {
mem_intf->writeDataMem(mem_addr, data, 4);
FILE_LOG(logINFO) << "SW: x" << std::dec << rs2 << "(0x" << std::hex
<< data << ") -> x" << std::dec << rs1 << " + 0x" << std::hex << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SW: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, rs1, imm, mem_addr);
return true;
}
@ -476,9 +460,8 @@ bool BASE_ISA::Exec_ADDI() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "ADDI: x" << std::dec << rs1 << " + " << imm
<< " -> x" << std::dec << rd << "(0x" << std::hex << calc << ")"
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. ADDI: x{:d} + x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd, calc);
return true;
}
@ -493,12 +476,13 @@ bool BASE_ISA::Exec_SLTI() {
if (regs->getValue(rs1) < imm) {
regs->setValue(rd, 1);
FILE_LOG(logINFO) << "SLTI: x" << rs1 << " < " << imm << " => "
<< "1 -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLTI: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
} else {
regs->setValue(rd, 0);
FILE_LOG(logINFO) << "SLTI: x" << rs1 << " < " << imm << " => "
<< "0 -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLTI: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
}
return true;
@ -514,12 +498,12 @@ bool BASE_ISA::Exec_SLTIU() {
if ((uint32_t) regs->getValue(rs1) < (uint32_t) imm) {
regs->setValue(rd, 1);
FILE_LOG(logINFO) << "SLTIU: x" << rs1 << " < " << imm << " => "
<< "1 -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLTIU: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
} else {
regs->setValue(rd, 0);
FILE_LOG(logINFO) << "SLTIU: x" << rs1 << " < " << imm << " => "
<< "0 -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLTIU: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
}
return true;
@ -537,8 +521,8 @@ bool BASE_ISA::Exec_XORI() {
calc = regs->getValue(rs1) ^ imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "XORI: x" << rs1 << " XOR " << imm << "-> x" << rd
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. XORI: x{:d} XOR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
return true;
}
@ -555,8 +539,8 @@ bool BASE_ISA::Exec_ORI() {
calc = regs->getValue(rs1) | imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "ORI: x" << rs1 << " OR " << imm << "-> x" << rd
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. ORI: x{:d} OR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
return true;
}
@ -575,9 +559,8 @@ bool BASE_ISA::Exec_ANDI() {
calc = aux & imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "ANDI: x" << rs1 << "(0x" << std::hex << aux
<< ") AND 0x" << imm << " -> x" << std::dec << rd << "(0x"
<< std::hex << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. ANDI: x{:d} AND x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd);
return true;
}
@ -603,8 +586,8 @@ bool BASE_ISA::Exec_SLLI() {
calc = ((uint32_t) regs->getValue(rs1)) << shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "SLLI: x" << std::dec << rs1 << " << " << shift
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLLI: x{:d} << {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -623,8 +606,8 @@ bool BASE_ISA::Exec_SRLI() {
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "SRLI: x" << std::dec << rs1 << " >> " << shift
<< " -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SRLI: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -643,8 +626,8 @@ bool BASE_ISA::Exec_SRAI() {
calc = regs->getValue(rs1) >> shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "SRAI: x" << std::dec << rs1 << " >> " << shift
<< " -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SRAI: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -660,8 +643,8 @@ bool BASE_ISA::Exec_ADD() {
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "ADD: x" << std::dec << rs1 << " + x" << rs2
<< " -> x" << rd << std::hex << "(0x" << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. ADD: x{:d} + x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -676,8 +659,8 @@ bool BASE_ISA::Exec_SUB() {
calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "SUB: x" << rs1 << " - x" << rs2 << " -> x" << rd
<< "(" << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SUB: x{:d} - x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -696,8 +679,8 @@ bool BASE_ISA::Exec_SLL() {
calc = ((uint32_t) regs->getValue(rs1)) << shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "SLL: x" << rs1 << " << " << shift << " -> x"
<< rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLL: x{:d} << x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -711,12 +694,12 @@ bool BASE_ISA::Exec_SLT() {
if (regs->getValue(rs1) < regs->getValue(rs2)) {
regs->setValue(rd, 1);
FILE_LOG(logINFO) << "SLT: x" << rs1 << " < x" << rs2 << " => "
<< "1 -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLT: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
} else {
regs->setValue(rd, 0);
FILE_LOG(logINFO) << "SLT: x" << rs1 << " < x" << rs2 << " => "
<< "0 -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLT: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
}
return true;
@ -731,12 +714,12 @@ bool BASE_ISA::Exec_SLTU() {
if ((uint32_t) regs->getValue(rs1) < (uint32_t) regs->getValue(rs2)) {
regs->setValue(rd, 1);
FILE_LOG(logINFO) << "SLTU: x" << rs1 << " < x" << rs2 << " => "
<< "1 -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLTU: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
} else {
regs->setValue(rd, 0);
FILE_LOG(logINFO) << "SLTU: x" << rs1 << " < x" << rs2 << " => "
<< "0 -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SLTU: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
}
return true;
@ -753,8 +736,8 @@ bool BASE_ISA::Exec_XOR() {
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "XOR: x" << rs1 << " XOR x" << rs2 << "-> x" << rd
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. XOR: x{:d} XOR x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -773,8 +756,8 @@ bool BASE_ISA::Exec_SRL() {
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "SRL: x" << rs1 << " >> " << shift << " -> x"
<< rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SRL: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -793,8 +776,8 @@ bool BASE_ISA::Exec_SRA() {
calc = regs->getValue(rs1) >> shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "SRA: x" << rs1 << " >> " << shift << " -> x"
<< rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SRA: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -810,8 +793,8 @@ bool BASE_ISA::Exec_OR() {
calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "OR: x" << rs1 << " OR x" << rs2 << "-> x" << rd
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. OR: x{:d} OR x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -827,21 +810,22 @@ bool BASE_ISA::Exec_AND() {
calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "AND: x" << rs1 << " AND x" << rs2 << "-> x" << rd
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. AND: x{:d} AND x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
bool BASE_ISA::Exec_FENCE() {
FILE_LOG(logINFO) << "FENCE" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. FENCE");
return true;
}
bool BASE_ISA::Exec_ECALL() {
FILE_LOG(logINFO) << "ECALL" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. ECALL");
std::cout << std::endl << "ECALL Instruction called, stopping simulation"
<< std::endl;
regs->dump();
@ -861,7 +845,7 @@ bool BASE_ISA::Exec_ECALL() {
bool BASE_ISA::Exec_EBREAK() {
FILE_LOG(logINFO) << "EBREAK" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. EBREAK");
std::cout << std::endl << "EBRAK Instruction called, dumping information"
<< std::endl;
regs->dump();
@ -891,9 +875,8 @@ bool BASE_ISA::Exec_CSRRW() {
aux = regs->getValue(rs1);
regs->setCSR(csr, aux);
FILE_LOG(logINFO) << std::hex << "CSRRW: CSR #" << csr << " -> x"
<< std::dec << rd << ". x" << rs1 << "-> CSR #" << std::hex << csr
<< " (0x" << aux << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. CSRRW: CSR #{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, aux);
return true;
}
@ -908,8 +891,7 @@ bool BASE_ISA::Exec_CSRRS() {
csr = get_csr();
if (rd == 0) {
FILE_LOG(logINFO) << "CSRRS with rd1 == 0, doing nothing."
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. CSRRS with rd1 == 0, doing nothing.");
return false;
}
@ -922,9 +904,8 @@ bool BASE_ISA::Exec_CSRRS() {
aux2 = aux | bitmask;
regs->setCSR(csr, aux2);
FILE_LOG(logINFO) << "CSRRS: CSR #" << csr << "(0x" << std::hex << aux
<< ") -> x" << std::dec << rd << ". x" << rs1 << " & CSR #" << csr
<< " <- 0x" << std::hex << aux2 << std::endl;
logger->debug("{} ns. PC: 0x{:x}. CSRRS: CSR #{:d}(0x{:x}) -> x{:d}(0x{:x}) & CSR #{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, aux, rd, rs1, csr, aux2);
return true;
}
@ -939,8 +920,7 @@ bool BASE_ISA::Exec_CSRRC() {
csr = get_csr();
if (rd == 0) {
FILE_LOG(logINFO) << "CSRRC with rd1 == 0, doing nothing."
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. CSRRC with rd1 == 0, doing nothing.");
return true;
}
@ -953,9 +933,8 @@ bool BASE_ISA::Exec_CSRRC() {
aux2 = aux & ~bitmask;
regs->setCSR(csr, aux2);
FILE_LOG(logINFO) << "CSRRC: CSR #" << csr << "(0x" << std::hex << aux
<< ") -> x" << std::dec << rd << ". x" << rs1 << " & CSR #" << csr
<< " <- 0x" << std::hex << aux2 << std::endl;
logger->debug("{} ns. PC: 0x{:x}. CSRRC: CSR #{:d}(0x{:x}) -> x{:d}(0x{:x}) & CSR #{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, aux, rd, rs1, csr, aux2);
return true;
}
@ -977,8 +956,8 @@ bool BASE_ISA::Exec_CSRRWI() {
aux = rs1;
regs->setCSR(csr, aux);
FILE_LOG(logINFO) << "CSRRWI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << "-> CSR #" << csr << std::endl;
logger->debug("{} ns. PC: 0x{:x}. CSRRWI: CSR #{:d} -> x{:d}. x{:d} -> CSR #{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr);
return true;
}
@ -1004,9 +983,8 @@ bool BASE_ISA::Exec_CSRRSI() {
aux = aux | bitmask;
regs->setCSR(csr, aux);
FILE_LOG(logINFO) << "CSRRSI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << " & CSR #" << csr << "(0x" << std::hex << aux << ")"
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. CSRRSI: CSR #{:d} -> x{:d}. x{:d} & CSR #{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr, aux);
return true;
}
@ -1032,9 +1010,8 @@ bool BASE_ISA::Exec_CSRRCI() {
aux = aux & ~bitmask;
regs->setCSR(csr, aux);
FILE_LOG(logINFO) << "CSRRCI: CSR #" << csr << " -> x" << rd << ". x"
<< rs1 << " & CSR #" << csr << "(0x" << std::hex << aux << ")"
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. CSRRCI: CSR #{:d} -> x{:d}. x{:d} & CSR #{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr, aux);
return true;
}
@ -1047,8 +1024,7 @@ bool BASE_ISA::Exec_MRET() {
new_pc = regs->getCSR(CSR_MEPC);
regs->setPC(new_pc);
FILE_LOG(logINFO) << "MRET: PC <- 0x" << std::hex << new_pc
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. MRET: PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), new_pc);
// update mstatus
uint32_t csr_temp;
@ -1068,21 +1044,17 @@ bool BASE_ISA::Exec_SRET() {
new_pc = regs->getCSR(CSR_SEPC);
regs->setPC(new_pc);
FILE_LOG(logINFO) << "SRET: PC <- 0x" << std::hex << new_pc
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. SRET: PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC());
return true;
}
bool BASE_ISA::Exec_WFI() {
FILE_LOG(logINFO) << "WFI" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. WFI");
return true;
}
bool BASE_ISA::Exec_SFENCE() {
FILE_LOG(logINFO) << "SFENCE" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. SFENCE");
return true;
}

23
src/CPU.cpp
View File

@ -40,6 +40,8 @@ CPU::CPU(sc_core::sc_module_name name, uint32_t PC) :
m_qk = new tlm_utils::tlm_quantumkeeper();
logger = spdlog::get("my_logger");
SC_THREAD(CPU_thread);
}
@ -67,7 +69,8 @@ bool CPU::cpu_process_IRQ() {
if (interrupt == true) {
csr_temp = register_bank->getCSR(CSR_MSTATUS);
if ((csr_temp & MSTATUS_MIE) == 0) {
FILE_LOG(logDEBUG) << "interrupt delayed" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(), register_bank->getPC());
return ret_value;
}
@ -76,13 +79,16 @@ bool CPU::cpu_process_IRQ() {
if ((csr_temp & MIP_MEIP) == 0) {
csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
register_bank->setCSR(CSR_MIP, csr_temp);
FILE_LOG(logDEBUG) << "Interrupt!" << std::endl;
/* updated MEPC register */
logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(), register_bank->getPC());
/* updated MEPC register */
old_pc = register_bank->getPC();
register_bank->setCSR(CSR_MEPC, old_pc);
FILE_LOG(logINFO) << "Old PC Value 0x" << std::hex << old_pc
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(), register_bank->getPC(),
old_pc);
/* update MCAUSE register */
register_bank->setCSR(CSR_MCAUSE, 0x80000000);
@ -90,8 +96,8 @@ bool CPU::cpu_process_IRQ() {
/* set new PC address */
new_pc = register_bank->getCSR(CSR_MTVEC);
//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
FILE_LOG(logDEBUG) << "NEW PC Value 0x" << std::hex << new_pc
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(), register_bank->getPC(),
new_pc);
register_bank->setPC(new_pc);
ret_value = true;
@ -154,9 +160,6 @@ void CPU::CPU_thread(void) {
perf->codeMemoryRead();
FILE_LOG(logINFO) << "PC: 0x" << std::hex << register_bank->getPC()
<< ". ";
inst->setInstr(INSTR);
/* check what type of instruction is and execute it */

112
src/C_extension.cpp
View File

@ -140,7 +140,6 @@ op_C_Codes C_extension::decode() {
default:
return OP_C_ERROR;
break;
}
return OP_C_ERROR;
@ -157,7 +156,7 @@ bool C_extension::Exec_C_JR() {
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
regs->setPC(new_pc);
FILE_LOG(logINFO) << "JR: PC <- 0x" << std::hex << new_pc << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.JR: PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), new_pc);
return true;
}
@ -173,10 +172,8 @@ bool C_extension::Exec_C_MV() {
calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.MV: x" << std::dec << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + x" << std::dec << rs2 << "(0x"
<< std::hex << regs->getValue(rs2) << ") -> x" << std::dec << rd
<< "(0x" << std::hex << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.MV: x{:d}(0x{:x}) + x{:d}(0x{:x}) -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), rd, calc);
return true;
}
@ -192,8 +189,8 @@ bool C_extension::Exec_C_ADD() {
calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.ADD: x" << std::dec << rs1 << " + x" << rs2
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.ADD: x{:d} + x{} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, calc);
return true;
}
@ -215,9 +212,8 @@ bool C_extension::Exec_C_LWSP() {
regs->setValue(rd, data);
FILE_LOG(logINFO) << "C.LWSP: x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ") -> x" << rd
<< "(" << std::hex << data << ")" << std::dec << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.LWSP: x{:d} + {:d}(@0x{:x}) -> x{:d}({:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd, data);
return true;
}
@ -239,9 +235,8 @@ bool C_extension::Exec_C_ADDI4SPN() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << std::dec << "C.ADDI4SPN: x" << rs1 << "(0x"
<< std::hex << regs->getValue(rs1) << ") + " << std::dec << imm
<< " -> x" << rd << "(0x" << std::hex << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.ADDI4SN: x{:d} + (0x{:x}) + {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, rd, calc);
return true;
}
@ -260,16 +255,16 @@ bool C_extension::Exec_C_ADDI16SP() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << std::dec << "C.ADDI16SP: x" << rs1 << " + "
<< std::dec << imm << " -> x" << rd << "(0x" << std::hex << calc
<< ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.ADDI16SP: x{:d} + {:d} -> x{:d} (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd, calc);
} else {
/* C.LUI OPCODE */
rd = get_rd();
imm = get_imm_LUI();
regs->setValue(rd, imm);
FILE_LOG(logINFO) << std::dec << "C.LUI x" << rd << " <- 0x"
<< std::hex << imm << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.LUI: x{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, imm);
}
return true;
@ -291,9 +286,8 @@ bool C_extension::Exec_C_SWSP() {
mem_intf->writeDataMem(mem_addr, data, 4);
FILE_LOG(logINFO) << std::dec << "C.SWSP: x" << rs2 << "(0x"
<< std::hex << data << ") -> x" << std::dec << rs1 << " + " << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.SWSP: x{:d}(0x{:x}) -> x{:d} + {} (@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, data, rs1, imm, mem_addr);
return true;
}
@ -314,9 +308,8 @@ bool C_extension::Exec_C_BEQZ() {
new_pc = regs->getPC();
}
FILE_LOG(logINFO) << "C.BEQZ: x" << std::dec << rs1 << "(" << val1
<< ") == 0? -> PC (0x" << std::hex << new_pc << ")" << std::dec
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.BEQZ: x{:d}(0x{:x}) == 0? -> PC (0xx{:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, new_pc);
return true;
}
@ -337,10 +330,8 @@ bool C_extension::Exec_C_BNEZ() {
new_pc = regs->getPC();
}
FILE_LOG(logINFO) << "C.BNEZ: x" << std::dec << rs1 << "(0x"
<< std::hex << val1 << ") != 0? -> PC (0x" << std::hex << new_pc
<< ")" << std::dec << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.BNEZ: x{:d}(0x{:x}) != 0? -> PC (0xx{:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, new_pc);
return true;
}
@ -357,9 +348,8 @@ bool C_extension::Exec_C_LI() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << std::dec << "C.LI: x" << rs1 << "("
<< regs->getValue(rs1) << ") + " << imm << " -> x" << rd << "("
<< calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.LI: x{:d} ({:d}) + {:d} -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, rd, calc);
return true;
}
@ -378,8 +368,8 @@ bool C_extension::Exec_C_SRLI() {
calc = ((uint32_t) regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.SRLI: x" << rs1 << " >> " << shift << " -> x"
<< rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.SRLI: x{:d} >> {} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd);
return true;
}
@ -398,9 +388,8 @@ bool C_extension::Exec_C_SRAI() {
calc = (int32_t) regs->getValue(rs1) >> shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.SRAI: x" << rs1 << " >> " << std::dec << shift
<< " -> x" << rd << "(" << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.SRAI: x{:d} >> {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -419,8 +408,8 @@ bool C_extension::Exec_C_SLLI() {
calc = ((uint32_t) regs->getValue(rs1)) << shift;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.SLLI: x" << std::dec << rs1 << " << " << shift
<< " -> x" << rd << "(0x" << calc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.SLLI: x{:d} << {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, shift, rd, calc);
return true;
}
@ -439,8 +428,8 @@ bool C_extension::Exec_C_ANDI() {
calc = aux & imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.ANDI: x" << rs1 << "(" << aux << ") AND "
<< imm << " -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.ANDI: x{:d}({:d}) AND {:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, aux, imm, rd);
return true;
}
@ -456,8 +445,8 @@ bool C_extension::Exec_C_SUB() {
calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.SUB: x" << std::dec << rs1 << " - x" << rs2
<< " -> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.SUB: x{:d} - x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
return true;
}
@ -473,8 +462,8 @@ bool C_extension::Exec_C_XOR() {
calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.XOR: x" << std::dec << rs1 << " XOR x" << rs2
<< "-> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.XOR: x{:d} XOR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
return true;
}
@ -490,8 +479,8 @@ bool C_extension::Exec_C_OR() {
calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C_OR: x" << std::dec << rs1 << " OR x" << rs2
<< "-> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.OR: x{:d} OR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
return true;
}
@ -507,8 +496,8 @@ bool C_extension::Exec_C_AND() {
calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.AND: x" << std::dec << rs1 << " AND x" << rs2
<< "-> x" << rd << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.AND: x{:d} AND x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd);
return true;
}
@ -525,9 +514,7 @@ bool C_extension::Exec_C_ADDI() {
calc = regs->getValue(rs1) + imm;
regs->setValue(rd, calc);
FILE_LOG(logINFO) << "C.ADDI: x" << std::dec << rs1 << " + " << imm
<< " -> x" << std::dec << rd << "(0x" << std::hex << calc << ")"
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.ADDI: x{:d} + {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), rs1, imm, rd, calc);
return true;
}
@ -546,9 +533,8 @@ bool C_extension::Exec_C_JALR() {
new_pc = (regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE;
regs->setPC(new_pc);
FILE_LOG(logINFO) << "C.JALR: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc + 4 << " PC <- 0x" << std::hex << new_pc
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.JALR: x{:d} <- 0x{:x} PC <- 0xx{:x}", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc + 4, new_pc);
return true;
}
@ -567,10 +553,8 @@ bool C_extension::Exec_C_LW() {
data = mem_intf->readDataMem(mem_addr, 4);
regs->setValue(rd, data);
FILE_LOG(logINFO) << std::dec << "C.LW: x" << rs1 << "(0x" << std::hex
<< regs->getValue(rs1) << ") + " << std::dec << imm << " (@0x"
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::hex
<< " (0x" << data << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.LW: x{:d}(0x{:x}) + {:d} (@0x{:x}) -> {:d} (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, mem_addr, rd, data);
return true;
}
@ -590,9 +574,8 @@ bool C_extension::Exec_C_SW() {
mem_intf->writeDataMem(mem_addr, data, 4);
FILE_LOG(logINFO) << "C.SW: x" << std::dec << rs2 << "(0x" << std::hex
<< data << ") -> x" << std::dec << rs1 << " + 0x" << std::hex << imm
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.SW: x{:d}(0x{:x}) -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, data, rs1, imm, mem_addr);
return true;
}
@ -612,9 +595,8 @@ bool C_extension::Exec_C_JAL(int m_rd) {
old_pc = old_pc + 2;
regs->setValue(rd, old_pc);
FILE_LOG(logINFO) << "C.JAL: x" << std::dec << rd << " <- 0x"
<< std::hex << old_pc << std::dec << ". PC + 0x" << std::hex
<< mem_addr << " -> PC (0x" << new_pc << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. C.JAL: x{:d} <- 0x{:x}. PC + 0x{:x} -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc, mem_addr, new_pc);
return true;
}

33
src/M_extension.cpp
View File

@ -8,6 +8,7 @@
#include "M_extension.h"
op_M_Codes M_extension::decode() {
switch (opcode()) {
@ -59,8 +60,8 @@ bool M_extension::Exec_M_MUL() {
result = result & 0x00000000FFFFFFFF;
regs->setValue(rd, result);
FILE_LOG(logDEBUG) << std::dec << "MUL: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. M.MUL: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -83,8 +84,8 @@ bool M_extension::Exec_M_MULH() {
ret_value = (int32_t) ((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value);
FILE_LOG(logDEBUG) << std::dec << "MULH: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. M.MULH: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -106,8 +107,8 @@ bool M_extension::Exec_M_MULHSU() {
result = (result >> 32) & 0x00000000FFFFFFFF;
regs->setValue(rd, result);
FILE_LOG(logDEBUG) << std::dec << "MULHSU: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. M.MULHSU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -129,8 +130,8 @@ bool M_extension::Exec_M_MULHU() {
ret_value = (uint32_t) (result >> 32) & 0x00000000FFFFFFFF;
regs->setValue(rd, ret_value);
FILE_LOG(logDEBUG) << std::dec << "MULHU: x" << rs1 << " * x" << rs2
<< " -> x" << rd << "(" << ret_value << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. M.MULHU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -158,8 +159,8 @@ bool M_extension::Exec_M_DIV() {
regs->setValue(rd, result);
FILE_LOG(logDEBUG) << std::dec << "DIV: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. M.DIV: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -185,8 +186,8 @@ bool M_extension::Exec_M_DIVU() {
regs->setValue(rd, result);
FILE_LOG(logDEBUG) << std::dec << "DIVU: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. M.DIVU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -213,8 +214,8 @@ bool M_extension::Exec_M_REM() {
regs->setValue(rd, result);
FILE_LOG(logDEBUG) << std::dec << "REM: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. M.REM: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
@ -239,8 +240,8 @@ bool M_extension::Exec_M_REMU() {
regs->setValue(rd, result);
FILE_LOG(logDEBUG) << std::dec << "REMU: x" << rs1 << " / x" << rs2
<< " -> x" << rd << "(" << result << ")" << std::endl;
logger->debug("{} ns. PC: 0x{:x}. M.REMU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}

6
src/Memory.cpp
View File

@ -22,7 +22,8 @@ Memory::Memory(sc_core::sc_module_name name, std::string filename) :
memory_offset = 0;
readHexFile(filename);
FILE_LOG(logINFO) << "Using file: " << filename << std::endl;
logger = spdlog::get("my_logger");
logger->debug("Using file {}", filename);
}
Memory::Memory(sc_core::sc_module_name name, bool use_file) :
@ -35,7 +36,8 @@ Memory::Memory(sc_core::sc_module_name name, bool use_file) :
mem = new uint8_t[SIZE];
FILE_LOG(logINFO) << "Memory instantiated wihtout file" << std::endl;
logger = spdlog::get("my_logger");
logger->debug("Memory instantiated wihtout file");
}
Memory::~Memory() {

19
src/Simulator.cpp
View File

@ -21,6 +21,9 @@
#include "Trace.h"
#include "Timer.h"
#include "spdlog/spdlog.h"
#include "spdlog/sinks/basic_file_sink.h"
std::string filename;
/**
@ -71,6 +74,7 @@ SC_MODULE(Simulator) {
};
Simulator *top;
std::shared_ptr<spdlog::logger> logger;
void intHandler(int dummy) {
delete top;
@ -91,19 +95,19 @@ void process_arguments(int argc, char *argv[]) {
switch (debug_level) {
case 3:
// log->setLogLevel(Log::INFO);
logger->set_level(spdlog::level::info);
break;
case 2:
// log->setLogLevel(Log::WARNING);
logger->set_level(spdlog::level::warn);
break;
case 1:
// log->setLogLevel(Log::DEBUG);
logger->set_level(spdlog::level::debug);
break;
case 0:
// log->setLogLevel(Log::ERROR);
logger->set_level(spdlog::level::err);
break;
default:
// log->setLogLevel(Log::INFO);
logger->set_level(spdlog::level::info);
break;
}
break;
@ -130,6 +134,11 @@ int sc_main(int argc, char *argv[]) {
/* SystemC time resolution set to 1 ns*/
sc_core::sc_set_time_resolution(1, sc_core::SC_NS);
spdlog::filename_t filename = SPDLOG_FILENAME_T("newlog.txt");
logger = spdlog::create<spdlog::sinks::basic_file_sink_mt>("my_logger", filename);
logger->set_pattern("%v");
logger->set_level(spdlog::level::info);
/* Parse and process program arguments. -f is mandatory */
process_arguments(argc, argv);

5
src/extension_base.cpp
View File

@ -13,6 +13,7 @@ extension_base::extension_base(sc_dt::sc_uint<32> instr,
m_instr(instr), regs(register_bank), mem_intf(mem_interface) {
perf = Performance::getInstance();
logger = spdlog::get("my_logger");
}
extension_base::~extension_base() {
@ -48,8 +49,8 @@ void extension_base::RaiseException(uint32_t cause, uint32_t inst) {
regs->setPC(new_pc);
FILE_LOG(logERROR) << "Exception! new PC 0x" << std::hex << new_pc
<< std::endl;
logger->debug("{} ns. PC: 0x{:x}. Exception! new PC 0x{:x} ", sc_core::sc_time_stamp().value(), regs->getPC(),
new_pc);
regs->dump();
std::cout << "Simulation time " << sc_core::sc_time_stamp() << std::endl;