add missing CSR register MCYcLE and similars
This commit is contained in:
parent
92a450b75e
commit
e75a4bfdfd
|
@ -49,6 +49,11 @@
|
||||||
#define CSR_STVAL (0x143)
|
#define CSR_STVAL (0x143)
|
||||||
#define CSR_SIP (0x144)
|
#define CSR_SIP (0x144)
|
||||||
|
|
||||||
|
#define CSR_MCYCLE (0xB00)
|
||||||
|
#define CSR_MINSTRET (0xB02)
|
||||||
|
#define CSR_MCYCLEH (0xB80)
|
||||||
|
#define CSR_MINSTRETH (0xB82)
|
||||||
|
|
||||||
#define CSR_CYCLE (0xC00)
|
#define CSR_CYCLE (0xC00)
|
||||||
#define CSR_TIME (0xC01)
|
#define CSR_TIME (0xC01)
|
||||||
#define CSR_INSTRET (0xC02)
|
#define CSR_INSTRET (0xC02)
|
||||||
|
|
|
@ -92,10 +92,12 @@ uint32_t Registers::getCSR(int csr) {
|
||||||
|
|
||||||
switch (csr) {
|
switch (csr) {
|
||||||
case CSR_CYCLE:
|
case CSR_CYCLE:
|
||||||
|
case CSR_MCYCLE:
|
||||||
ret_value = (uint64_t)(sc_time(sc_time_stamp()
|
ret_value = (uint64_t)(sc_time(sc_time_stamp()
|
||||||
- sc_time(SC_ZERO_TIME)).to_double()) & 0x00000000FFFFFFFF;
|
- sc_time(SC_ZERO_TIME)).to_double()) & 0x00000000FFFFFFFF;
|
||||||
break;
|
break;
|
||||||
case CSR_CYCLEH:
|
case CSR_CYCLEH:
|
||||||
|
case CSR_MCYCLEH:
|
||||||
ret_value = (uint32_t)((uint64_t)(sc_time(sc_time_stamp()
|
ret_value = (uint32_t)((uint64_t)(sc_time(sc_time_stamp()
|
||||||
- sc_time(SC_ZERO_TIME)).to_double()) >> 32 & 0x00000000FFFFFFFF);
|
- sc_time(SC_ZERO_TIME)).to_double()) >> 32 & 0x00000000FFFFFFFF);
|
||||||
break;
|
break;
|
||||||
|
|
Loading…
Reference in New Issue