fixed ISR memory alignement
This commit is contained in:
parent
d83a15eec5
commit
e9ef03890f
|
@ -0,0 +1,3 @@
|
||||||
|
riscv32-unknown-elf-gcc -Wall -I. -O0 -static -march=rv32imac -mabi=ilp32 --specs=nosys.specs timer.c timerasm.S -o timer.elf
|
||||||
|
objcopy -Oihex timer.elf timer.hex
|
||||||
|
riscv32-unknown-elf-objdump timer.elf -d > dump
|
|
@ -1,10 +1,10 @@
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
|
|
||||||
#define TIMER (*(uint64_t *)0x40004000)
|
#define TIMER (*(uint64_t volatile *)0x40004000)
|
||||||
#define TIMER_CMP (*(uint64_t *)0x40004008)
|
#define TIMER_CMP (*(uint64_t volatile *)0x40004008)
|
||||||
#define TRACE (*(unsigned char *)0x40000000)
|
#define TRACE (*(unsigned char volatile *)0x40000000)
|
||||||
|
|
||||||
volatile int ticks = 0;
|
volatile uint32_t ticks = 0;
|
||||||
|
|
||||||
int _write(int file, const char *ptr, int len) {
|
int _write(int file, const char *ptr, int len) {
|
||||||
int x;
|
int x;
|
||||||
|
@ -17,20 +17,22 @@ int _write(int file, const char *ptr, int len) {
|
||||||
}
|
}
|
||||||
|
|
||||||
void timer_ISR() {
|
void timer_ISR() {
|
||||||
uint32_t timer_value;
|
volatile uint32_t timer_value;
|
||||||
|
|
||||||
ticks++;
|
ticks++;
|
||||||
if (ticks < 10) {
|
|
||||||
timer_value = TIMER;
|
timer_value = TIMER;
|
||||||
// timer is in nanoseconds, set to 1 ms.
|
|
||||||
// comparator value fixed to take into account number of instructions executed
|
// timer is in nanoseconds, set to 1 ms.
|
||||||
TIMER_CMP = timer_value + 590;
|
// comparator value fixed to take into account number of instructions executed
|
||||||
}
|
TIMER_CMP = timer_value + 610;
|
||||||
}
|
}
|
||||||
|
|
||||||
void register_timer_isr() {
|
void register_timer_isr() {
|
||||||
asm volatile("la t0, TIMER_CMP_INT \n csrw mtvec, t0");
|
asm volatile("la t0, TIMER_CMP_INT");
|
||||||
asm volatile("li t1, 0x888 \n csrw mie, t1");
|
asm volatile("csrw mtvec, t0");
|
||||||
|
asm volatile("li t1, 0x888");
|
||||||
|
asm volatile("csrw mie, t1");
|
||||||
}
|
}
|
||||||
|
|
||||||
int main(void) {
|
int main(void) {
|
||||||
|
@ -43,14 +45,20 @@ int main(void) {
|
||||||
start_time = TIMER;
|
start_time = TIMER;
|
||||||
TIMER_CMP = start_time + 10000;
|
TIMER_CMP = start_time + 10000;
|
||||||
printf("set timer to %ld ns\n", start_time + 10000);
|
printf("set timer to %ld ns\n", start_time + 10000);
|
||||||
|
|
||||||
do {
|
do {
|
||||||
timer_value = TIMER;
|
timer_value = TIMER;
|
||||||
} while (timer_value < start_time + 200000);
|
} while (timer_value < start_time + 2000000);
|
||||||
|
|
||||||
printf("Timer: %ld ns\n", timer_value);
|
printf("Timer: %ld ns\n", timer_value);
|
||||||
printf("ticks: %ld\n", ticks);
|
printf("ticks: %ld\n", ticks);
|
||||||
|
|
||||||
|
if (ticks > 2100) {
|
||||||
|
printf("Test OK!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("Finish\n");
|
||||||
|
|
||||||
asm volatile ("ecall");
|
asm volatile ("ecall");
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -8,7 +8,7 @@
|
||||||
#define LOAD lw
|
#define LOAD lw
|
||||||
#define REGBYTES 4
|
#define REGBYTES 4
|
||||||
|
|
||||||
|
.align 2
|
||||||
TIMER_CMP_INT:
|
TIMER_CMP_INT:
|
||||||
/* store execution context on the stack (register content) */
|
/* store execution context on the stack (register content) */
|
||||||
addi sp, sp, -REGBYTES * 32
|
addi sp, sp, -REGBYTES * 32
|
||||||
|
@ -32,7 +32,7 @@ STORE x31, 30 * REGBYTES(sp)
|
||||||
|
|
||||||
/* load interrupt/trap reason and call external C function to handle it */
|
/* load interrupt/trap reason and call external C function to handle it */
|
||||||
csrr a0, mcause
|
csrr a0, mcause
|
||||||
jal timer_ISR
|
jal timer_ISR
|
||||||
|
|
||||||
/* re-store the saved context */
|
/* re-store the saved context */
|
||||||
LOAD x1, 0x0(sp)
|
LOAD x1, 0x0(sp)
|
||||||
|
@ -54,4 +54,3 @@ LOAD x30, 29 * REGBYTES(sp)
|
||||||
LOAD x31, 30 * REGBYTES(sp)
|
LOAD x31, 30 * REGBYTES(sp)
|
||||||
addi sp, sp, REGBYTES * 32
|
addi sp, sp, REGBYTES * 32
|
||||||
mret
|
mret
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue