diff --git a/inc/A_extension.h b/inc/A_extension.h
index 00667fb..a7d67be 100644
--- a/inc/A_extension.h
+++ b/inc/A_extension.h
@@ -133,7 +133,7 @@ public:
 	bool Exec_A_AMOMINU();
 	bool Exec_A_AMOMAXU();
 
-	bool process_instruction(Instruction &inst);
+	bool process_instruction(Instruction *inst);
 
 	void TLB_reserve(uint32_t address);
 	bool TLB_reserved(uint32_t address);
diff --git a/inc/BASE_ISA.h b/inc/BASE_ISA.h
index 4546cf5..36c994b 100644
--- a/inc/BASE_ISA.h
+++ b/inc/BASE_ISA.h
@@ -411,7 +411,7 @@ public:
 	 * @param  inst instruction to execute
 	 * @return  true if PC is affected by instruction
 	 */
-	bool process_instruction(Instruction &inst);
+	bool process_instruction(Instruction *inst);
 
 	/**
 	 * @brief Decodes opcode of instruction
diff --git a/inc/C_extension.h b/inc/C_extension.h
index 54fd6d4..df5ca80 100644
--- a/inc/C_extension.h
+++ b/inc/C_extension.h
@@ -416,7 +416,7 @@ public:
 	bool Exec_C_SW();
 	bool Exec_C_JAL(int m_rd);
 
-	bool process_instruction(Instruction &inst);
+	bool process_instruction(Instruction *inst);
 };
 
 #endif
diff --git a/inc/Instruction.h b/inc/Instruction.h
index e88f1b0..d1ff21f 100644
--- a/inc/Instruction.h
+++ b/inc/Instruction.h
@@ -35,7 +35,7 @@ typedef enum {
 class Instruction {
 public:
 
-	Instruction(sc_dt::sc_uint<32> instr);
+	Instruction(uint32_t instr);
 
 	/**
 	 * @brief returns what instruction extension
@@ -59,7 +59,7 @@ public:
 	}
 
 private:
-	sc_dt::sc_uint<32> m_instr;
+	uint32_t m_instr;
 };
 
 #endif
diff --git a/inc/M_extension.h b/inc/M_extension.h
index 14dcc4b..13dbf6f 100644
--- a/inc/M_extension.h
+++ b/inc/M_extension.h
@@ -69,7 +69,7 @@ public:
 	bool Exec_M_REM();
 	bool Exec_M_REMU();
 
-	bool process_instruction(Instruction &inst);
+	bool process_instruction(Instruction *inst);
 
 private:
 
diff --git a/inc/Performance.h b/inc/Performance.h
index 354af6d..3111729 100644
--- a/inc/Performance.h
+++ b/inc/Performance.h
@@ -87,13 +87,13 @@ private:
 	static Performance *instance;
 	Performance();
 
-	uint64_t data_memory_read;
-	uint64_t data_memory_write;
-	uint64_t code_memory_read;
-	uint64_t code_memory_write;
-	uint64_t register_read;
-	uint64_t register_write;
-	uint64_t instructions_executed;
+	uint_fast64_t data_memory_read;
+	uint_fast64_t data_memory_write;
+	uint_fast64_t code_memory_read;
+	uint_fast64_t code_memory_write;
+	uint_fast64_t register_read;
+	uint_fast64_t register_write;
+	uint_fast64_t instructions_executed;
 };
 
 #endif
diff --git a/inc/Registers.h b/inc/Registers.h
index eef56a0..deffb1e 100644
--- a/inc/Registers.h
+++ b/inc/Registers.h
@@ -245,7 +245,7 @@ private:
 	/**
 	 * bank of registers (32 regs of 32bits each)
 	 */
-	int32_t register_bank[32];
+	std::array<int,32> register_bank{0};
 
 	/**
 	 * Program counter (32 bits width)
@@ -256,7 +256,7 @@ private:
 	 * CSR registers (4096 maximum)
 	 */
 	//uint32_t CSR[4096];
-	std::unordered_map<unsigned int, uint32_t> CSR;
+	std::unordered_map<unsigned int, uint32_t> CSR{0};
 
 
 	Performance *perf;
diff --git a/src/A_extension.cpp b/src/A_extension.cpp
index 8c2e91a..2f5b385 100644
--- a/src/A_extension.cpp
+++ b/src/A_extension.cpp
@@ -367,10 +367,10 @@ bool A_extension::TLB_reserved(uint32_t address) {
 	}
 }
 
-bool A_extension::process_instruction(Instruction &inst) {
+bool A_extension::process_instruction(Instruction *inst) {
 	bool PC_not_affected = true;
 
-	setInstr(inst.getInstr());
+	setInstr(inst->getInstr());
 
 	switch (decode()) {
 	case OP_A_LR:
@@ -408,7 +408,7 @@ bool A_extension::process_instruction(Instruction &inst) {
 		break;
 	[[unlikely]] default:
 		std::cout << "A instruction not implemented yet" << std::endl;
-		inst.dump();
+		inst->dump();
 		NOP();
 		break;
 	}
diff --git a/src/BASE_ISA.cpp b/src/BASE_ISA.cpp
index e493d63..45379e6 100644
--- a/src/BASE_ISA.cpp
+++ b/src/BASE_ISA.cpp
@@ -1150,10 +1150,10 @@ bool BASE_ISA::Exec_SFENCE() {
 	return true;
 }
 
-bool BASE_ISA::process_instruction(Instruction &inst) {
+bool BASE_ISA::process_instruction(Instruction *inst) {
 	bool PC_not_affected = true;
 
-	setInstr(inst.getInstr());
+	setInstr(inst->getInstr());
 
 	switch (decode()) {
 	case OP_LUI:
@@ -1318,7 +1318,7 @@ bool BASE_ISA::process_instruction(Instruction &inst) {
 		break;
 	[[unlikely]] default:
 		std::cout << "Wrong instruction" << "\n";
-		inst.dump();
+		inst->dump();
 		NOP();
 		//sc_stop();
 		break;
diff --git a/src/BusCtrl.cpp b/src/BusCtrl.cpp
index 52fa20a..80c0bf6 100644
--- a/src/BusCtrl.cpp
+++ b/src/BusCtrl.cpp
@@ -24,7 +24,7 @@ BusCtrl::BusCtrl(sc_core::sc_module_name name) :
 
 void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
 		sc_core::sc_time &delay) {
-	//tlm::tlm_command cmd = trans.get_command();
+
 	sc_dt::uint64 adr = trans.get_address() / 4;
 
 	switch (adr) {
diff --git a/src/CPU.cpp b/src/CPU.cpp
index 90f6ace..11bb4ae 100644
--- a/src/CPU.cpp
+++ b/src/CPU.cpp
@@ -163,19 +163,19 @@ void CPU::CPU_thread(void) {
 		/* check what type of instruction is and execute it */
 		switch (inst->check_extension()) {
 		[[likely]] case BASE_EXTENSION:
-			PC_not_affected = exec->process_instruction(*inst);
+			PC_not_affected = exec->process_instruction(inst);
 			incPCby2 = false;
 			break;
 		case C_EXTENSION:
-			PC_not_affected = c_inst->process_instruction(*inst);
+			PC_not_affected = c_inst->process_instruction(inst);
 			incPCby2 = true;
 			break;
 		case M_EXTENSION:
-			PC_not_affected = m_inst->process_instruction(*inst);
+			PC_not_affected = m_inst->process_instruction(inst);
 			incPCby2 = false;
 			break;
 		case A_EXTENSION:
-			PC_not_affected = a_inst->process_instruction(*inst);
+			PC_not_affected = a_inst->process_instruction(inst);
 			incPCby2 = false;
 			break;
 		[[unlikely]] default:
@@ -202,10 +202,8 @@ void CPU::CPU_thread(void) {
 			m_qk->sync();
 		}
 #else
-		sc_core::wait(10, sc_core::SC_NS);
-
+		//sc_core::wait(10, sc_core::SC_NS);
 #endif
-
 	} // while(1)
 } // CPU_thread
 
diff --git a/src/CPU64.cpp b/src/CPU64.cpp
index 8c5d04c..1af765a 100644
--- a/src/CPU64.cpp
+++ b/src/CPU64.cpp
@@ -163,19 +163,19 @@ void CPU64::CPU_thread(void) {
 		/* check what type of instruction is and execute it */
 		switch (inst->check_extension()) {
 		[[likely]] case BASE_EXTENSION:
-			PC_not_affected = exec->process_instruction(*inst);
+			PC_not_affected = exec->process_instruction(inst);
 			incPCby2 = false;
 			break;
 		case C_EXTENSION:
-			PC_not_affected = c_inst->process_instruction(*inst);
+			PC_not_affected = c_inst->process_instruction(inst);
 			incPCby2 = true;
 			break;
 		case M_EXTENSION:
-			PC_not_affected = m_inst->process_instruction(*inst);
+			PC_not_affected = m_inst->process_instruction(inst);
 			incPCby2 = false;
 			break;
 		case A_EXTENSION:
-			PC_not_affected = a_inst->process_instruction(*inst);
+			PC_not_affected = a_inst->process_instruction(inst);
 			incPCby2 = false;
 			break;
 		[[unlikely]] default:
diff --git a/src/C_extension.cpp b/src/C_extension.cpp
index 52a7931..d8f6e9d 100644
--- a/src/C_extension.cpp
+++ b/src/C_extension.cpp
@@ -661,10 +661,10 @@ bool C_extension::Exec_C_JAL(int m_rd) {
 	return true;
 }
 
-bool C_extension::process_instruction(Instruction &inst) {
+bool C_extension::process_instruction(Instruction *inst) {
 	bool PC_not_affected = true;
 
-	setInstr(inst.getInstr());
+	setInstr(inst->getInstr());
 
 	switch (decode()) {
 	case OP_C_ADDI4SPN:
@@ -747,7 +747,7 @@ bool C_extension::process_instruction(Instruction &inst) {
 		break;
 	[[unlikely]] default:
 		std::cout << "C instruction not implemented yet" << "\n";
-		inst.dump();
+		inst->dump();
 		NOP();
 		break;
 	}
diff --git a/src/Instruction.cpp b/src/Instruction.cpp
index 42fe19e..24fda9d 100644
--- a/src/Instruction.cpp
+++ b/src/Instruction.cpp
@@ -8,26 +8,29 @@
 
 #include "Instruction.h"
 
-Instruction::Instruction(sc_dt::sc_uint<32> instr) {
+Instruction::Instruction(uint32_t instr) {
 	m_instr = instr;
 }
 
 extension_t Instruction::check_extension() {
-	if ((m_instr.range(6, 0) == 0b0110011)
-			&& (m_instr.range(31, 25) == 0b0000001)) {
+	if (((m_instr & 0x0000007F) == 0b0110011)
+			&& ( ((m_instr & 0x7F000000) >> 25) == 0b0000001)) {
 		return M_EXTENSION;
-	} else if (m_instr.range(6, 0) == 0b0101111) {
+	} else if ((m_instr & 0x0000007F) == 0b0101111) {
 		return A_EXTENSION;
-	} else if (m_instr.range(1, 0) == 0b11) {
+	} else if ((m_instr & 0x00000003) == 0b11) {
 		return BASE_EXTENSION;
-	} else if (m_instr.range(1, 0) == 0b00) {
+	} else if ((m_instr & 0x00000003) == 0b00) {
 		return C_EXTENSION;
-	} else if (m_instr.range(1, 0) == 0b01) {
+	} else if ((m_instr & 0x00000003) == 0b01) {
 		return C_EXTENSION;
-	} else if (m_instr.range(1, 0) == 0b10) {
+	} else if ((m_instr & 0x00000003) == 0b10) {
 		return C_EXTENSION;
 	} else {
+		std::cout << "Unknown\n";
 		return UNKNOWN_EXTENSION;
 	}
 }
 
+
+
diff --git a/src/M_extension.cpp b/src/M_extension.cpp
index 76b99cb..b442c29 100644
--- a/src/M_extension.cpp
+++ b/src/M_extension.cpp
@@ -245,10 +245,10 @@ bool M_extension::Exec_M_REMU() {
 	return true;
 }
 
-bool M_extension::process_instruction(Instruction &inst) {
+bool M_extension::process_instruction(Instruction *inst) {
 	bool PC_not_affected = true;
 
-	setInstr(inst.getInstr());
+	setInstr(inst->getInstr());
 
 	switch (decode()) {
 	case OP_M_MUL:
@@ -277,7 +277,7 @@ bool M_extension::process_instruction(Instruction &inst) {
 		break;
 	[[unlikely]] default:
 		std::cout << "M instruction not implemented yet" << "\n";
-		inst.dump();
+		inst->dump();
 		//NOP(inst);
 		sc_core::sc_stop();
 		break;
diff --git a/src/Memory.cpp b/src/Memory.cpp
index 6edf358..7003a28 100644
--- a/src/Memory.cpp
+++ b/src/Memory.cpp
@@ -58,6 +58,7 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
 	unsigned int wid = trans.get_streaming_width();
 
 	adr = adr - memory_offset;
+
 	// Obliged to check address range and check for unsupported features,
 	//   i.e. byte enables, streaming, and bursts
 	// Can ignore extensions
@@ -65,7 +66,6 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
 	// *********************************************
 	// Generate the appropriate error response
 	// *********************************************
-
 	if (adr >= sc_dt::uint64(SIZE)) {
 		trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
 		return;
@@ -79,6 +79,7 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
 		return;
 	}
 
+
 	// Obliged to implement read and write commands
 	if (cmd == tlm::TLM_READ_COMMAND)
 		memcpy(ptr, &mem[adr], len);
@@ -86,7 +87,7 @@ void Memory::b_transport(tlm::tlm_generic_payload &trans,
 		memcpy(&mem[adr], ptr, len);
 
 	// Illustrates that b_transport may block
-	sc_core::wait(delay);
+	//sc_core::wait(delay);
 
 	// Reset timing annotation after waiting
 	delay = sc_core::SC_ZERO_TIME;
diff --git a/src/Registers.cpp b/src/Registers.cpp
index fb08355..94ee631 100644
--- a/src/Registers.cpp
+++ b/src/Registers.cpp
@@ -10,8 +10,6 @@
 
 Registers::Registers() {
 
-	memset(register_bank, 0, sizeof(uint32_t) * 32); // 32 registers of 32 bits each
-	//memset(CSR, 0, sizeof(uint32_t) * 4096);
 	perf = Performance::getInstance();
 
 	initCSR();