colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added namespace to project

This commit is contained in:
mariusmonton 2021-11-29 20:35:26 +01:00
parent e2981d8a50
commit fb84f197bf
28 changed files with 4895 additions and 4632 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
inc/A_extension.h
View File

@ -17,6 +17,8 @@
#include "MemoryInterface.h" #include "MemoryInterface.h"
#include "extension_base.h" #include "extension_base.h"
namespace riscv_tlm {
typedef enum { typedef enum {
OP_A_LR, OP_A_LR,
OP_A_SC, OP_A_SC,
@ -77,24 +79,36 @@ public:
} }
bool Exec_A_LR(); bool Exec_A_LR();
bool Exec_A_SC(); bool Exec_A_SC();
bool Exec_A_AMOSWAP() const; bool Exec_A_AMOSWAP() const;
bool Exec_A_AMOADD() const; bool Exec_A_AMOADD() const;
bool Exec_A_AMOXOR() const; bool Exec_A_AMOXOR() const;
bool Exec_A_AMOAND() const; bool Exec_A_AMOAND() const;
bool Exec_A_AMOOR() const; bool Exec_A_AMOOR() const;
bool Exec_A_AMOMIN() const; bool Exec_A_AMOMIN() const;
bool Exec_A_AMOMAX() const; bool Exec_A_AMOMAX() const;
bool Exec_A_AMOMINU() const; bool Exec_A_AMOMINU() const;
bool Exec_A_AMOMAXU() const; bool Exec_A_AMOMAXU() const;
bool process_instruction(Instruction &inst); bool process_instruction(Instruction &inst);
void TLB_reserve(std::uint32_t address); void TLB_reserve(std::uint32_t address);
bool TLB_reserved(std::uint32_t address); bool TLB_reserved(std::uint32_t address);
private: private:
std::unordered_set<std::uint32_t> TLB_A_Entries; std::unordered_set<std::uint32_t> TLB_A_Entries;
}; };
}
#endif #endif

55
inc/BASE_ISA.h
View File

@ -23,6 +23,8 @@
#include "A_extension.h" #include "A_extension.h"
#include "Registers.h" #include "Registers.h"
namespace riscv_tlm {
typedef enum { typedef enum {
OP_LUI, OP_LUI,
OP_AUIPC, OP_AUIPC,
@ -119,7 +121,7 @@ public:
* @return immediate_I field * @return immediate_I field
*/ */
inline std::int32_t get_imm_I() const { inline std::int32_t get_imm_I() const {
std::int32_t aux = 0; std::uint32_t aux = 0;
aux = m_instr.range(31, 20); aux = m_instr.range(31, 20);
@ -128,7 +130,7 @@ public:
aux |= (0b11111111111111111111) << 12; aux |= (0b11111111111111111111) << 12;
} }
return aux; return static_cast<std::int32_t>(aux);
} }
/** /**
@ -144,7 +146,7 @@ public:
* @return immediate_S field * @return immediate_S field
*/ */
inline std::int32_t get_imm_S() const { inline std::int32_t get_imm_S() const {
std::int32_t aux = 0; std::uint32_t aux = 0;
aux = m_instr.range(31, 25) << 5; aux = m_instr.range(31, 25) << 5;
aux |= m_instr.range(11, 7); aux |= m_instr.range(11, 7);
@ -153,7 +155,7 @@ public:
aux |= (0b11111111111111111111) << 12; aux |= (0b11111111111111111111) << 12;
} }
return aux; return static_cast<std::int32_t>(aux);
} }
/** /**
@ -161,7 +163,7 @@ public:
* @return immediate_U field * @return immediate_U field
*/ */
inline std::int32_t get_imm_U() const { inline std::int32_t get_imm_U() const {
return m_instr.range(31, 12); return static_cast<std::int32_t>(m_instr.range(31, 12));
} }
/** /**
@ -266,67 +268,108 @@ public:
} }
bool Exec_LUI() const; bool Exec_LUI() const;
bool Exec_AUIPC() const; bool Exec_AUIPC() const;
bool Exec_JAL() const; bool Exec_JAL() const;
bool Exec_JALR(); bool Exec_JALR();
bool Exec_BEQ() const; bool Exec_BEQ() const;
bool Exec_BNE() const; bool Exec_BNE() const;
bool Exec_BLT() const; bool Exec_BLT() const;
bool Exec_BGE() const; bool Exec_BGE() const;
bool Exec_BLTU() const; bool Exec_BLTU() const;
bool Exec_BGEU() const; bool Exec_BGEU() const;
bool Exec_LB() const; bool Exec_LB() const;
bool Exec_LH() const; bool Exec_LH() const;
bool Exec_LW() const; bool Exec_LW() const;
bool Exec_LBU() const; bool Exec_LBU() const;
bool Exec_LHU() const; bool Exec_LHU() const;
bool Exec_SB() const; bool Exec_SB() const;
bool Exec_SH() const; bool Exec_SH() const;
bool Exec_SW() const; bool Exec_SW() const;
bool Exec_SBU() const; bool Exec_SBU() const;
bool Exec_SHU() const; bool Exec_SHU() const;
bool Exec_ADDI() const; bool Exec_ADDI() const;
bool Exec_SLTI() const; bool Exec_SLTI() const;
bool Exec_SLTIU() const; bool Exec_SLTIU() const;
bool Exec_XORI() const; bool Exec_XORI() const;
bool Exec_ORI() const; bool Exec_ORI() const;
bool Exec_ANDI() const; bool Exec_ANDI() const;
bool Exec_SLLI(); bool Exec_SLLI();
bool Exec_SRLI() const; bool Exec_SRLI() const;
bool Exec_SRAI() const; bool Exec_SRAI() const;
bool Exec_ADD() const; bool Exec_ADD() const;
bool Exec_SUB() const; bool Exec_SUB() const;
bool Exec_SLL() const; bool Exec_SLL() const;
bool Exec_SLT() const; bool Exec_SLT() const;
bool Exec_SLTU() const; bool Exec_SLTU() const;
bool Exec_XOR() const; bool Exec_XOR() const;
bool Exec_SRL() const; bool Exec_SRL() const;
bool Exec_SRA() const; bool Exec_SRA() const;
bool Exec_OR() const; bool Exec_OR() const;
bool Exec_AND() const; bool Exec_AND() const;
bool Exec_FENCE() const; bool Exec_FENCE() const;
bool Exec_ECALL(); bool Exec_ECALL();
bool Exec_EBREAK(); bool Exec_EBREAK();
bool Exec_CSRRW() const; bool Exec_CSRRW() const;
bool Exec_CSRRS() const; bool Exec_CSRRS() const;
bool Exec_CSRRC() const; bool Exec_CSRRC() const;
bool Exec_CSRRWI() const; bool Exec_CSRRWI() const;
bool Exec_CSRRSI() const; bool Exec_CSRRSI() const;
bool Exec_CSRRCI() const; bool Exec_CSRRCI() const;
/*********************** Privileged Instructions ******************************/ /*********************** Privileged Instructions ******************************/
bool Exec_MRET() const; bool Exec_MRET() const;
bool Exec_SRET() const; bool Exec_SRET() const;
bool Exec_WFI() const; bool Exec_WFI() const;
bool Exec_SFENCE() const; bool Exec_SFENCE() const;
/** /**
@ -342,5 +385,5 @@ public:
*/ */
opCodes decode(); opCodes decode();
}; };
}
#endif #endif

5
inc/BusCtrl.h
View File

@ -20,6 +20,8 @@
#include "tlm_utils/simple_initiator_socket.h" #include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h" #include "tlm_utils/simple_target_socket.h"
namespace riscv_tlm {
/** /**
* Memory mapped Trace peripheral address * Memory mapped Trace peripheral address
*/ */
@ -85,7 +87,8 @@ public:
private: private:
bool instr_direct_mem_ptr(tlm::tlm_generic_payload &, bool instr_direct_mem_ptr(tlm::tlm_generic_payload &,
tlm::tlm_dmi &dmi_data); tlm::tlm_dmi &dmi_data);
void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end); void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
}; };
}
#endif #endif

4
inc/CPU.h
View File

@ -26,6 +26,8 @@
#include "M_extension.h" #include "M_extension.h"
#include "A_extension.h" #include "A_extension.h"
namespace riscv_tlm {
/** /**
* @brief ISC_V CPU model * @brief ISC_V CPU model
* @param name name of the module * @param name name of the module
@ -89,7 +91,6 @@ private:
unsigned char *dmi_ptr = nullptr; unsigned char *dmi_ptr = nullptr;
/** /**
* *
* @brief Process and triggers IRQ if all conditions met * @brief Process and triggers IRQ if all conditions met
@ -121,4 +122,5 @@ private:
void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end); void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
}; };
}
#endif #endif

26
inc/C_extension.h
View File

@ -12,6 +12,8 @@
#include "systemc" #include "systemc"
#include "extension_base.h" #include "extension_base.h"
namespace riscv_tlm {
typedef enum { typedef enum {
OP_C_ADDI4SPN, OP_C_ADDI4SPN,
OP_C_FLD, OP_C_FLD,
@ -237,6 +239,7 @@ public:
m_instr.range(11, 7) = aux.range(4, 1); m_instr.range(11, 7) = aux.range(4, 1);
m_instr[6] = aux[11]; m_instr[6] = aux[11];
} }
/** /**
* @brief Access to immediate field for J-type * @brief Access to immediate field for J-type
* @return immediate_J field * @return immediate_J field
@ -380,32 +383,55 @@ public:
op_C_Codes decode() const; op_C_Codes decode() const;
bool Exec_C_JR(); bool Exec_C_JR();
bool Exec_C_MV(); bool Exec_C_MV();
bool Exec_C_LWSP(); bool Exec_C_LWSP();
bool Exec_C_ADDI4SPN(); bool Exec_C_ADDI4SPN();
bool Exec_C_SLLI(); bool Exec_C_SLLI();
bool Exec_C_ADDI16SP(); bool Exec_C_ADDI16SP();
bool Exec_C_SWSP(); bool Exec_C_SWSP();
bool Exec_C_BEQZ(); bool Exec_C_BEQZ();
bool Exec_C_BNEZ(); bool Exec_C_BNEZ();
bool Exec_C_LI(); bool Exec_C_LI();
bool Exec_C_SRLI(); bool Exec_C_SRLI();
bool Exec_C_SRAI(); bool Exec_C_SRAI();
bool Exec_C_ANDI(); bool Exec_C_ANDI();
bool Exec_C_ADD(); bool Exec_C_ADD();
bool Exec_C_SUB(); bool Exec_C_SUB();
bool Exec_C_XOR(); bool Exec_C_XOR();
bool Exec_C_OR(); bool Exec_C_OR();
bool Exec_C_AND(); bool Exec_C_AND();
bool Exec_C_ADDI() const; bool Exec_C_ADDI() const;
bool Exec_C_JALR(); bool Exec_C_JALR();
bool Exec_C_LW(); bool Exec_C_LW();
bool Exec_C_SW(); bool Exec_C_SW();
bool Exec_C_JAL(int m_rd); bool Exec_C_JAL(int m_rd);
bool Exec_C_EBREAK(); bool Exec_C_EBREAK();
bool process_instruction(Instruction &inst, bool *breakpoint = nullptr); bool process_instruction(Instruction &inst, bool *breakpoint = nullptr);
}; };
}
#endif #endif

4
inc/Instruction.h
View File

@ -12,6 +12,8 @@
#include "systemc" #include "systemc"
#include "extension_base.h" #include "extension_base.h"
namespace riscv_tlm {
typedef enum { typedef enum {
BASE_EXTENSION, BASE_EXTENSION,
M_EXTENSION, M_EXTENSION,
@ -46,6 +48,7 @@ public:
void setInstr(std::uint32_t p_instr) { void setInstr(std::uint32_t p_instr) {
m_instr = p_instr; m_instr = p_instr;
} }
/** /**
* @brief return instruction * @brief return instruction
* @return all instruction bits (31:0) * @return all instruction bits (31:0)
@ -61,5 +64,6 @@ public:
private: private:
std::uint32_t m_instr; std::uint32_t m_instr;
}; };
}
#endif #endif

10
inc/M_extension.h
View File

@ -14,6 +14,8 @@
#include "extension_base.h" #include "extension_base.h"
#include "Registers.h" #include "Registers.h"
namespace riscv_tlm {
typedef enum { typedef enum {
OP_M_MUL, OP_M_MUL,
OP_M_MULH, OP_M_MULH,
@ -60,12 +62,19 @@ public:
} }
bool Exec_M_MUL() const; bool Exec_M_MUL() const;
bool Exec_M_MULH() const; bool Exec_M_MULH() const;
bool Exec_M_MULHSU() const; bool Exec_M_MULHSU() const;
bool Exec_M_MULHU() const; bool Exec_M_MULHU() const;
bool Exec_M_DIV() const; bool Exec_M_DIV() const;
bool Exec_M_DIVU() const; bool Exec_M_DIVU() const;
bool Exec_M_REM() const; bool Exec_M_REM() const;
bool Exec_M_REMU() const; bool Exec_M_REMU() const;
bool process_instruction(Instruction &inst); bool process_instruction(Instruction &inst);
@ -81,5 +90,6 @@ private:
} }
}; };
}
#endif #endif

4
inc/Memory.h
View File

@ -21,6 +21,8 @@
#include "spdlog/spdlog.h" #include "spdlog/spdlog.h"
#include "spdlog/sinks/basic_file_sink.h" #include "spdlog/sinks/basic_file_sink.h"
namespace riscv_tlm {
/** /**
* @brief Basic TLM-2 memory * @brief Basic TLM-2 memory
*/ */
@ -36,6 +38,7 @@ public:
const sc_core::sc_time LATENCY; const sc_core::sc_time LATENCY;
Memory(sc_core::sc_module_name const &name, std::string const &filename); Memory(sc_core::sc_module_name const &name, std::string const &filename);
explicit Memory(const sc_core::sc_module_name &name); explicit Memory(const sc_core::sc_module_name &name);
~Memory() override; ~Memory() override;
@ -89,4 +92,5 @@ private:
*/ */
void readHexFile(const std::string &filename); void readHexFile(const std::string &filename);
}; };
}
#endif /* __MEMORY_H__ */ #endif /* __MEMORY_H__ */

6
inc/MemoryInterface.h
View File

@ -17,6 +17,8 @@
#include "memory.h" #include "memory.h"
namespace riscv_tlm {
/** /**
* @brief Memory Interface * @brief Memory Interface
*/ */
@ -26,8 +28,10 @@ public:
tlm_utils::simple_initiator_socket<MemoryInterface> data_bus; tlm_utils::simple_initiator_socket<MemoryInterface> data_bus;
MemoryInterface(); MemoryInterface();
std::uint32_t readDataMem(std::uint32_t addr, int size); std::uint32_t readDataMem(std::uint32_t addr, int size);
void writeDataMem(std::uint32_t addr, std::uint32_t data, int size); void writeDataMem(std::uint32_t addr, std::uint32_t data, int size);
}; };
}
#endif /* INC_MEMORYINTERFACE_H_ */ #endif /* INC_MEMORYINTERFACE_H_ */

6
inc/Registers.h
View File

@ -19,6 +19,8 @@
#include "Performance.h" #include "Performance.h"
#include "Memory.h" #include "Memory.h"
namespace riscv_tlm {
#define MISA_A_EXTENSION (1 << 0) #define MISA_A_EXTENSION (1 << 0)
#define MISA_B_EXTENSION (1 << 1) #define MISA_B_EXTENSION (1 << 1)
#define MISA_C_EXTENSION (1 << 2) #define MISA_C_EXTENSION (1 << 2)
@ -180,6 +182,7 @@ public:
t5 = x30, t5 = x30,
t6 = x31 t6 = x31
}; };
/** /**
* Default constructor * Default constructor
*/ */
@ -240,6 +243,7 @@ public:
* Dump register data to console * Dump register data to console
*/ */
void dump(); void dump();
private: private:
/** /**
* bank of registers (32 regs of 32bits each) * bank of registers (32 regs of 32bits each)
@ -261,5 +265,5 @@ private:
void initCSR(); void initCSR();
}; };
}
#endif #endif

3
inc/Timer.h
View File

@ -21,6 +21,7 @@
#include "BusCtrl.h" #include "BusCtrl.h"
namespace riscv_tlm::peripherals {
/** /**
* @brief Simple timer peripheral * @brief Simple timer peripheral
* *
@ -66,5 +67,5 @@ private:
sc_dt::sc_uint<64> m_mtimecmp; /**< mtimecmp register */ sc_dt::sc_uint<64> m_mtimecmp; /**< mtimecmp register */
sc_core::sc_event timer_event; /**< event */ sc_core::sc_event timer_event; /**< event */
}; };
}
#endif #endif

5
inc/Trace.h
View File

@ -19,6 +19,7 @@
#include "tlm.h" #include "tlm.h"
#include "tlm_utils/simple_target_socket.h" #include "tlm_utils/simple_target_socket.h"
namespace riscv_tlm::peripherals {
/** /**
* @brief Simple trace peripheral * @brief Simple trace peripheral
* *
@ -50,12 +51,14 @@ private:
sc_core::sc_time &delay); sc_core::sc_time &delay);
void xtermLaunch(char *slaveName) const; void xtermLaunch(char *slaveName) const;
void xtermKill(); void xtermKill();
void xtermSetup(); void xtermSetup();
int ptSlave{}; int ptSlave{};
int ptMaster{}; int ptMaster{};
int xtermPid{}; int xtermPid{};
}; };
}
#endif #endif

6
inc/extension_base.h
View File

@ -26,15 +26,20 @@
#define EXCEPTION_CAUSE_LOAD_ADDR_MISALIGN 4 #define EXCEPTION_CAUSE_LOAD_ADDR_MISALIGN 4
#define EXCEPTION_CAUSE_LOAD_ACCESS_FAULT 5 #define EXCEPTION_CAUSE_LOAD_ACCESS_FAULT 5
namespace riscv_tlm {
class extension_base { class extension_base {
public: public:
extension_base(const sc_dt::sc_uint<32> &instr, Registers *register_bank, extension_base(const sc_dt::sc_uint<32> &instr, Registers *register_bank,
MemoryInterface *mem_interface); MemoryInterface *mem_interface);
virtual ~extension_base() = 0; virtual ~extension_base() = 0;
void setInstr(std::uint32_t p_instr); void setInstr(std::uint32_t p_instr);
void RaiseException(std::uint32_t cause, std::uint32_t inst); void RaiseException(std::uint32_t cause, std::uint32_t inst);
bool NOP(); bool NOP();
/* pure virtual functions */ /* pure virtual functions */
@ -81,5 +86,6 @@ protected:
MemoryInterface *mem_intf; MemoryInterface *mem_intf;
std::shared_ptr<spdlog::logger> logger; std::shared_ptr<spdlog::logger> logger;
}; };
}
#endif /* INC_EXTENSION_BASE_H_ */ #endif /* INC_EXTENSION_BASE_H_ */

13
src/A_extension.cpp
View File

@ -8,6 +8,8 @@
#include "A_extension.h" #include "A_extension.h"
namespace riscv_tlm {
op_A_Codes A_extension::decode() const { op_A_Codes A_extension::decode() const {
switch (opcode()) { switch (opcode()) {
@ -76,7 +78,8 @@ bool A_extension::Exec_A_LR() {
TLB_reserve(mem_addr); TLB_reserve(mem_addr);
logger->debug("{} ns. PC: 0x{:x}. A.LR.W: x{:d}(0x{:x}) -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. A.LR.W: x{:d}(0x{:x}) -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, mem_addr, rd, data); rs1, mem_addr, rd, data);
return true; return true;
@ -102,7 +105,8 @@ bool A_extension::Exec_A_SC() {
regs->setValue(rd, 1); // SC writes nonzero on failure regs->setValue(rd, 1); // SC writes nonzero on failure
} }
logger->debug("{} ns. PC: 0x{:x}. A.SC.W: (0x{:x}) <- x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. A.SC.W: (0x{:x}) <- x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(),
regs->getPC(),
mem_addr, rs2, data); mem_addr, rs2, data);
return true; return true;
@ -192,6 +196,7 @@ bool A_extension::Exec_A_AMOXOR() const {
return true; return true;
} }
bool A_extension::Exec_A_AMOAND() const { bool A_extension::Exec_A_AMOAND() const {
std::uint32_t mem_addr; std::uint32_t mem_addr;
int rd, rs1, rs2; int rd, rs1, rs2;
@ -279,6 +284,7 @@ bool A_extension::Exec_A_AMOMIN() const {
return true; return true;
} }
bool A_extension::Exec_A_AMOMAX() const { bool A_extension::Exec_A_AMOMAX() const {
std::uint32_t mem_addr; std::uint32_t mem_addr;
int rd, rs1, rs2; int rd, rs1, rs2;
@ -310,6 +316,7 @@ bool A_extension::Exec_A_AMOMAX() const {
return true; return true;
} }
bool A_extension::Exec_A_AMOMINU() const { bool A_extension::Exec_A_AMOMINU() const {
std::uint32_t mem_addr; std::uint32_t mem_addr;
int rd, rs1, rs2; int rd, rs1, rs2;
@ -341,6 +348,7 @@ bool A_extension::Exec_A_AMOMINU() const {
return true; return true;
} }
bool A_extension::Exec_A_AMOMAXU() const { bool A_extension::Exec_A_AMOMAXU() const {
std::uint32_t mem_addr; std::uint32_t mem_addr;
int rd, rs1, rs2; int rd, rs1, rs2;
@ -434,3 +442,4 @@ bool A_extension::process_instruction(Instruction &inst) {
return PC_not_affected; return PC_not_affected;
} }
}

149
src/BASE_ISA.cpp
View File

@ -11,6 +11,8 @@
#include "BASE_ISA.h" #include "BASE_ISA.h"
namespace riscv_tlm {
enum Codes { enum Codes {
LUI = 0b0110111, LUI = 0b0110111,
AUIPC = 0b0010111, AUIPC = 0b0010111,
@ -110,14 +112,15 @@ bool BASE_ISA::Exec_AUIPC() const {
regs->setValue(rd, new_pc); regs->setValue(rd, new_pc);
logger->debug("{} ns. PC: 0x{:x}. AUIPC: x{:d} <- 0x{:x} + PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. AUIPC: x{:d} <- 0x{:x} + PC (0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rd, imm, new_pc); rd, imm, new_pc);
return true; return true;
} }
bool BASE_ISA::Exec_JAL() const { bool BASE_ISA::Exec_JAL() const {
int32_t mem_addr; std::int32_t mem_addr;
int rd; int rd;
std::uint32_t new_pc, old_pc; std::uint32_t new_pc, old_pc;
@ -131,7 +134,8 @@ bool BASE_ISA::Exec_JAL() const {
old_pc = old_pc + 4; old_pc = old_pc + 4;
regs->setValue(rd, old_pc); regs->setValue(rd, old_pc);
logger->debug("{} ns. PC: 0x{:x}. JAL: x{:d} <- 0x{:x}. PC + 0x{:x} -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. JAL: x{:d} <- 0x{:x}. PC + 0x{:x} -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc, mem_addr, new_pc); rd, old_pc, mem_addr, new_pc);
return true; return true;
@ -153,7 +157,8 @@ bool BASE_ISA::Exec_JALR() {
if ((new_pc & 0x00000003) != 0) { if ((new_pc & 0x00000003) != 0) {
// not aligned // not aligned
logger->debug("{} ns. PC: 0x{:x}. JALR: x{:d} <- 0x{:x} PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. JALR: x{:d} <- 0x{:x} PC <- 0x{:x}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rd, old_pc + 4, new_pc); rd, old_pc + 4, new_pc);
logger->debug("{} ns. PC: 0x{:x}. JALR : Exception"); logger->debug("{} ns. PC: 0x{:x}. JALR : Exception");
@ -162,7 +167,8 @@ bool BASE_ISA::Exec_JALR() {
regs->setPC(new_pc); regs->setPC(new_pc);
} }
logger->debug("{} ns. PC: 0x{:x}. JALR: x{:d} <- 0x{:x}. PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. JALR: x{:d} <- 0x{:x}. PC <- 0x{:x}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rd, old_pc + 4, new_pc); rd, old_pc + 4, new_pc);
return true; return true;
@ -183,7 +189,8 @@ bool BASE_ISA::Exec_BEQ() const {
new_pc = static_cast<std::uint32_t>(regs->getPC()); new_pc = static_cast<std::uint32_t>(regs->getPC());
} }
logger->debug("{} ns. PC: 0x{:x}. BEQ: x{:d}(0x{:x}) == x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. BEQ: x{:d}(0x{:x}) == x{:d}(0x{:x})? -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc); rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true; return true;
@ -208,7 +215,8 @@ bool BASE_ISA::Exec_BNE() const {
new_pc = static_cast<std::uint32_t>(regs->getPC()); new_pc = static_cast<std::uint32_t>(regs->getPC());
} }
logger->debug("{} ns. PC: 0x{:x}. BNE: x{:d}(0x{:x}) != x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. BNE: x{:d}(0x{:x}) != x{:d}(0x{:x})? -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, rs2, val2, new_pc); rs1, val1, rs2, val2, new_pc);
return true; return true;
@ -228,7 +236,8 @@ bool BASE_ISA::Exec_BLT() const {
regs->incPC(); regs->incPC();
} }
logger->debug("{} ns. PC: 0x{:x}. BLT: x{:d}(0x{:x}) < x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. BLT: x{:d}(0x{:x}) < x{:d}(0x{:x})? -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc); rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true; return true;
@ -248,7 +257,8 @@ bool BASE_ISA::Exec_BGE() const {
regs->incPC(); regs->incPC();
} }
logger->debug("{} ns. PC: 0x{:x}. BGE: x{:d}(0x{:x}) > x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. BGE: x{:d}(0x{:x}) > x{:d}(0x{:x})? -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc); rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true; return true;
@ -269,7 +279,8 @@ bool BASE_ISA::Exec_BLTU() const {
new_pc = static_cast<std::uint32_t>(regs->getPC()); new_pc = static_cast<std::uint32_t>(regs->getPC());
} }
logger->debug("{} ns. PC: 0x{:x}. BLTU: x{:d}(0x{:x}) < x{:d}(0x{:x})? -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. BLTU: x{:d}(0x{:x}) < x{:d}(0x{:x})? -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc); rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
return true; return true;
@ -285,12 +296,14 @@ bool BASE_ISA::Exec_BGEU() const {
std::uint32_t new_pc; std::uint32_t new_pc;
new_pc = static_cast<std::uint32_t>(regs->getPC() + get_imm_B()); new_pc = static_cast<std::uint32_t>(regs->getPC() + get_imm_B());
logger->debug("{} ns. PC: 0x{:x}. BGEU: x{:d}(0x{:x}) > x{:d}(0x{:x}) -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. BGEU: x{:d}(0x{:x}) > x{:d}(0x{:x}) -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc); rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), new_pc);
regs->setPC(new_pc); regs->setPC(new_pc);
} else { } else {
logger->debug("{} ns. PC: 0x{:x}. BGEU: x{:d}(0x{:x}) > x{:d}(0x{:x}) -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. BGEU: x{:d}(0x{:x}) > x{:d}(0x{:x}) -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), regs->getPC() + 4); rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), regs->getPC() + 4);
regs->incPC(); regs->incPC();
} }
@ -313,7 +326,8 @@ bool BASE_ISA::Exec_LB() const {
perf->dataMemoryRead(); perf->dataMemoryRead();
regs->setValue(rd, data); regs->setValue(rd, data);
logger->debug("{} ns. PC: 0x{:x}. LB: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. LB: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, mem_addr, rd); rs1, imm, mem_addr, rd);
return true; return true;
@ -334,7 +348,8 @@ bool BASE_ISA::Exec_LH() const {
perf->dataMemoryRead(); perf->dataMemoryRead();
regs->setValue(rd, data); regs->setValue(rd, data);
logger->debug("{} ns. PC: 0x{:x}. LH: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. LH: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, mem_addr, rd); rs1, imm, mem_addr, rd);
return true; return true;
@ -355,7 +370,8 @@ bool BASE_ISA::Exec_LW() const {
perf->dataMemoryRead(); perf->dataMemoryRead();
regs->setValue(rd, static_cast<std::int32_t>(data)); regs->setValue(rd, static_cast<std::int32_t>(data));
logger->debug("{} ns. PC: 0x{:x}. LW: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. LW: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, mem_addr, rd); rs1, imm, mem_addr, rd);
return true; return true;
@ -376,7 +392,8 @@ bool BASE_ISA::Exec_LBU() const {
perf->dataMemoryRead(); perf->dataMemoryRead();
regs->setValue(rd, static_cast<std::int32_t>(data)); regs->setValue(rd, static_cast<std::int32_t>(data));
logger->debug("{} ns. PC: 0x{:x}. LBU: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. LBU: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, mem_addr, rd); rs1, imm, mem_addr, rd);
return true; return true;
@ -398,7 +415,8 @@ bool BASE_ISA::Exec_LHU() const {
regs->setValue(rd, data); regs->setValue(rd, data);
logger->debug("{} ns. PC: 0x{:x}. LHU: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. LHU: x{:d} + x{:d}(0x{:x}) -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, mem_addr, rd); rs1, imm, mem_addr, rd);
return true; return true;
@ -420,7 +438,8 @@ bool BASE_ISA::Exec_SB() const {
mem_intf->writeDataMem(mem_addr, data, 1); mem_intf->writeDataMem(mem_addr, data, 1);
perf->dataMemoryWrite(); perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. SB: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SB: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs2, rs1, imm, mem_addr); rs2, rs1, imm, mem_addr);
return true; return true;
@ -442,7 +461,8 @@ bool BASE_ISA::Exec_SH() const {
mem_intf->writeDataMem(mem_addr, data, 2); mem_intf->writeDataMem(mem_addr, data, 2);
perf->dataMemoryWrite(); perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. SH: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SH: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs2, rs1, imm, mem_addr); rs2, rs1, imm, mem_addr);
return true; return true;
@ -464,7 +484,8 @@ bool BASE_ISA::Exec_SW() const {
mem_intf->writeDataMem(mem_addr, data, 4); mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite(); perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. SW: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SW: x{:d} -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs2, rs1, imm, mem_addr); rs2, rs1, imm, mem_addr);
return true; return true;
@ -482,7 +503,8 @@ bool BASE_ISA::Exec_ADDI() const {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm; calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
logger->debug("{} ns. PC: 0x{:x}. ADDI: x{:d} + x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. ADDI: x{:d} + x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, rd, calc); rs1, imm, rd, calc);
return true; return true;
@ -499,11 +521,13 @@ bool BASE_ISA::Exec_SLTI() const {
if (static_cast<std::int32_t>(regs->getValue(rs1)) < imm) { if (static_cast<std::int32_t>(regs->getValue(rs1)) < imm) {
regs->setValue(rd, 1); regs->setValue(rd, 1);
logger->debug("{} ns. PC: 0x{:x}. SLTI: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLTI: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, rd); rs1, imm, rd);
} else { } else {
regs->setValue(rd, 0); regs->setValue(rd, 0);
logger->debug("{} ns. PC: 0x{:x}. SLTI: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLTI: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, rd); rs1, imm, rd);
} }
@ -520,11 +544,13 @@ bool BASE_ISA::Exec_SLTIU() const {
if (static_cast<std::uint32_t>(regs->getValue(rs1)) < static_cast<std::uint32_t>(imm)) { if (static_cast<std::uint32_t>(regs->getValue(rs1)) < static_cast<std::uint32_t>(imm)) {
regs->setValue(rd, 1); regs->setValue(rd, 1);
logger->debug("{} ns. PC: 0x{:x}. SLTIU: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLTIU: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, rd); rs1, imm, rd);
} else { } else {
regs->setValue(rd, 0); regs->setValue(rd, 0);
logger->debug("{} ns. PC: 0x{:x}. SLTIU: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLTIU: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, rd); rs1, imm, rd);
} }
@ -543,7 +569,8 @@ bool BASE_ISA::Exec_XORI() const {
calc = regs->getValue(rs1) ^ imm; calc = regs->getValue(rs1) ^ imm;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. XORI: x{:d} XOR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. XORI: x{:d} XOR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, rd); rs1, imm, rd);
return true; return true;
@ -561,7 +588,8 @@ bool BASE_ISA::Exec_ORI() const {
calc = regs->getValue(rs1) | imm; calc = regs->getValue(rs1) | imm;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. ORI: x{:d} OR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. ORI: x{:d} OR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, imm, rd); rs1, imm, rd);
return true; return true;
@ -581,7 +609,8 @@ bool BASE_ISA::Exec_ANDI() const {
calc = aux & imm; calc = aux & imm;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. ANDI: x{:d}(0x{:x}) AND 0x{:x} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. ANDI: x{:d}(0x{:x}) AND 0x{:x} -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, aux, imm, rd); rs1, aux, imm, rd);
return true; return true;
@ -608,7 +637,8 @@ bool BASE_ISA::Exec_SLLI() {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift; calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. SLLI: x{:d} << {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLLI: x{:d} << {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd, calc); rs1, shift, rd, calc);
return true; return true;
@ -628,7 +658,8 @@ bool BASE_ISA::Exec_SRLI() const {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift; calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. SRLI: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SRLI: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd, calc); rs1, shift, rd, calc);
return true; return true;
@ -648,7 +679,8 @@ bool BASE_ISA::Exec_SRAI() const {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift; calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
logger->debug("{} ns. PC: 0x{:x}. SRAI: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SRAI: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd, calc); rs1, shift, rd, calc);
return true; return true;
@ -665,7 +697,8 @@ bool BASE_ISA::Exec_ADD() const {
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. ADD: x{:d} + x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. ADD: x{:d} + x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, calc); rs1, rs2, rd, calc);
return true; return true;
@ -681,7 +714,8 @@ bool BASE_ISA::Exec_SUB() const {
calc = regs->getValue(rs1) - regs->getValue(rs2); calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. SUB: x{:d} - x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SUB: x{:d} - x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, calc); rs1, rs2, rd, calc);
return true; return true;
@ -701,7 +735,8 @@ bool BASE_ISA::Exec_SLL() const {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift; calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. SLL: x{:d} << x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLL: x{:d} << x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd, calc); rs1, shift, rd, calc);
return true; return true;
@ -716,11 +751,13 @@ bool BASE_ISA::Exec_SLT() const {
if (regs->getValue(rs1) < regs->getValue(rs2)) { if (regs->getValue(rs1) < regs->getValue(rs2)) {
regs->setValue(rd, 1); regs->setValue(rd, 1);
logger->debug("{} ns. PC: 0x{:x}. SLT: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLT: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd); rs1, rs2, rd);
} else { } else {
regs->setValue(rd, 0); regs->setValue(rd, 0);
logger->debug("{} ns. PC: 0x{:x}. SLT: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLT: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd); rs1, rs2, rd);
} }
@ -736,11 +773,13 @@ bool BASE_ISA::Exec_SLTU() const {
if (static_cast<std::uint32_t>(regs->getValue(rs1)) < static_cast<std::uint32_t>(regs->getValue(rs2))) { if (static_cast<std::uint32_t>(regs->getValue(rs1)) < static_cast<std::uint32_t>(regs->getValue(rs2))) {
regs->setValue(rd, 1); regs->setValue(rd, 1);
logger->debug("{} ns. PC: 0x{:x}. SLTU: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLTU: x{:d} < x{:d} => 1 -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd); rs1, rs2, rd);
} else { } else {
regs->setValue(rd, 0); regs->setValue(rd, 0);
logger->debug("{} ns. PC: 0x{:x}. SLTU: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SLTU: x{:d} < x{:d} => 0 -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd); rs1, rs2, rd);
} }
@ -758,7 +797,8 @@ bool BASE_ISA::Exec_XOR() const {
calc = regs->getValue(rs1) ^ regs->getValue(rs2); calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. XOR: x{:d} XOR x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. XOR: x{:d} XOR x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, calc); rs1, rs2, rd, calc);
return true; return true;
@ -778,7 +818,8 @@ bool BASE_ISA::Exec_SRL() const {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift; calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. SRL: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SRL: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd, calc); rs1, shift, rd, calc);
return true; return true;
@ -798,7 +839,8 @@ bool BASE_ISA::Exec_SRA() const {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift; calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
logger->debug("{} ns. PC: 0x{:x}. SRA: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. SRA: x{:d} >> {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd, calc); rs1, shift, rd, calc);
return true; return true;
@ -815,7 +857,8 @@ bool BASE_ISA::Exec_OR() const {
calc = regs->getValue(rs1) | regs->getValue(rs2); calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. OR: x{:d} OR x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. OR: x{:d} OR x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, calc); rs1, rs2, rd, calc);
return true; return true;
@ -832,7 +875,8 @@ bool BASE_ISA::Exec_AND() const {
calc = regs->getValue(rs1) & regs->getValue(rs2); calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. AND: x{:d} AND x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. AND: x{:d} AND x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, calc); rs1, rs2, rd, calc);
return true; return true;
@ -901,7 +945,8 @@ bool BASE_ISA::Exec_CSRRW() const {
aux = regs->getValue(rs1); aux = regs->getValue(rs1);
regs->setCSR(csr, aux); regs->setCSR(csr, aux);
logger->debug("{} ns. PC: 0x{:x}. CSRRW: CSR #{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. CSRRW: CSR #{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
csr, rd, aux); csr, rd, aux);
return true; return true;
@ -930,7 +975,8 @@ bool BASE_ISA::Exec_CSRRS() const {
aux2 = aux | bitmask; aux2 = aux | bitmask;
regs->setCSR(csr, aux2); regs->setCSR(csr, aux2);
logger->debug("{} ns. PC: 0x{:x}. CSRRS: CSR #{:d}(0x{:x}) -> x{:d}(0x{:x}) & CSR #{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. CSRRS: CSR #{:d}(0x{:x}) -> x{:d}(0x{:x}) & CSR #{:d} <- 0x{:x}",
sc_core::sc_time_stamp().value(), regs->getPC(),
csr, aux, rd, rs1, csr, aux2); csr, aux, rd, rs1, csr, aux2);
return true; return true;
@ -959,7 +1005,8 @@ bool BASE_ISA::Exec_CSRRC() const {
aux2 = aux & ~bitmask; aux2 = aux & ~bitmask;
regs->setCSR(csr, aux2); regs->setCSR(csr, aux2);
logger->debug("{} ns. PC: 0x{:x}. CSRRC: CSR #{:d}(0x{:x}) -> x{:d}(0x{:x}) & CSR #{:d} <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. CSRRC: CSR #{:d}(0x{:x}) -> x{:d}(0x{:x}) & CSR #{:d} <- 0x{:x}",
sc_core::sc_time_stamp().value(), regs->getPC(),
csr, aux, rd, rs1, csr, aux2); csr, aux, rd, rs1, csr, aux2);
return true; return true;
@ -982,7 +1029,8 @@ bool BASE_ISA::Exec_CSRRWI() const {
aux = rs1; aux = rs1;
regs->setCSR(csr, aux); regs->setCSR(csr, aux);
logger->debug("{} ns. PC: 0x{:x}. CSRRWI: CSR #{:d} -> x{:d}. x{:d} -> CSR #{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. CSRRWI: CSR #{:d} -> x{:d}. x{:d} -> CSR #{:d}",
sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr); csr, rd, rs1, csr);
return true; return true;
@ -1009,7 +1057,8 @@ bool BASE_ISA::Exec_CSRRSI() const {
aux = aux | bitmask; aux = aux | bitmask;
regs->setCSR(csr, aux); regs->setCSR(csr, aux);
logger->debug("{} ns. PC: 0x{:x}. CSRRSI: CSR #{:d} -> x{:d}. x{:d} & CSR #{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. CSRRSI: CSR #{:d} -> x{:d}. x{:d} & CSR #{:d}(0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr, aux); csr, rd, rs1, csr, aux);
return true; return true;
@ -1036,7 +1085,8 @@ bool BASE_ISA::Exec_CSRRCI() const {
aux = aux & ~bitmask; aux = aux & ~bitmask;
regs->setCSR(csr, aux); regs->setCSR(csr, aux);
logger->debug("{} ns. PC: 0x{:x}. CSRRCI: CSR #{:d} -> x{:d}. x{:d} & CSR #{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. CSRRCI: CSR #{:d} -> x{:d}. x{:d} & CSR #{:d}(0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
csr, rd, rs1, csr, aux); csr, rd, rs1, csr, aux);
return true; return true;
@ -1430,3 +1480,4 @@ opCodes BASE_ISA::decode() {
return OP_ERROR; return OP_ERROR;
} }
}

5
src/BusCtrl.cpp
View File

@ -8,7 +8,10 @@
#include "BusCtrl.h" #include "BusCtrl.h"
namespace riscv_tlm {
SC_HAS_PROCESS(BusCtrl); SC_HAS_PROCESS(BusCtrl);
BusCtrl::BusCtrl(sc_core::sc_module_name const &name) : BusCtrl::BusCtrl(sc_core::sc_module_name const &name) :
sc_module(name), cpu_instr_socket("cpu_instr_socket"), cpu_data_socket( sc_module(name), cpu_instr_socket("cpu_instr_socket"), cpu_data_socket(
"cpu_data_socket"), memory_socket("memory_socket"), trace_socket( "cpu_data_socket"), memory_socket("memory_socket"), trace_socket(
@ -68,4 +71,4 @@ void BusCtrl::invalidate_direct_mem_ptr(sc_dt::uint64 start,
sc_dt::uint64 end) { sc_dt::uint64 end) {
cpu_instr_socket->invalidate_direct_mem_ptr(start, end); cpu_instr_socket->invalidate_direct_mem_ptr(start, end);
} }
}

16
src/CPU.cpp
View File

@ -7,7 +7,10 @@
// SPDX-License-Identifier: GPL-3.0-or-later // SPDX-License-Identifier: GPL-3.0-or-later
#include "CPU.h" #include "CPU.h"
namespace riscv_tlm {
SC_HAS_PROCESS(CPU); SC_HAS_PROCESS(CPU);
CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) : CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
sc_module(name), instr_bus("instr_bus"), inst(0), default_time(10, sc_module(name), instr_bus("instr_bus"), inst(0), default_time(10,
sc_core::SC_NS), INSTR(0) { sc_core::SC_NS), INSTR(0) {
@ -69,7 +72,8 @@ bool CPU::cpu_process_IRQ() {
if (interrupt) { if (interrupt) {
csr_temp = register_bank->getCSR(CSR_MSTATUS); csr_temp = register_bank->getCSR(CSR_MSTATUS);
if ((csr_temp & MSTATUS_MIE) == 0) { if ((csr_temp & MSTATUS_MIE) == 0) {
logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(), register_bank->getPC()); logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(),
register_bank->getPC());
return ret_value; return ret_value;
} }
@ -80,14 +84,16 @@ bool CPU::cpu_process_IRQ() {
csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit) csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
register_bank->setCSR(CSR_MIP, csr_temp); register_bank->setCSR(CSR_MIP, csr_temp);
logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(), register_bank->getPC()); logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(),
register_bank->getPC());
/* updated MEPC register */ /* updated MEPC register */
std::uint32_t old_pc = register_bank->getPC(); std::uint32_t old_pc = register_bank->getPC();
register_bank->setCSR(CSR_MEPC, old_pc); register_bank->setCSR(CSR_MEPC, old_pc);
logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(), register_bank->getPC(), logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
register_bank->getPC(),
old_pc); old_pc);
/* update MCAUSE register */ /* update MCAUSE register */
@ -96,7 +102,8 @@ bool CPU::cpu_process_IRQ() {
/* set new PC address */ /* set new PC address */
std::uint32_t new_pc = register_bank->getCSR(CSR_MTVEC); std::uint32_t new_pc = register_bank->getCSR(CSR_MTVEC);
//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0 //new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(), register_bank->getPC(), logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
register_bank->getPC(),
new_pc); new_pc);
register_bank->setPC(new_pc); register_bank->setPC(new_pc);
@ -226,3 +233,4 @@ void CPU::invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end) {
(void) end; (void) end;
dmi_ptr_valid = false; dmi_ptr_valid = false;
} }
}

76
src/C_extension.cpp
View File

@ -6,6 +6,8 @@
*/ */
#include "C_extension.h" #include "C_extension.h"
namespace riscv_tlm {
op_C_Codes C_extension::decode() const { op_C_Codes C_extension::decode() const {
switch (opcode()) { switch (opcode()) {
@ -131,7 +133,8 @@ op_C_Codes C_extension::decode() const {
return OP_C_SWSP; return OP_C_SWSP;
break; break;
case C_FWWSP: case C_FWWSP:
[[unlikely]] default: [[unlikely]]
default:
return OP_C_ERROR; return OP_C_ERROR;
break; break;
} }
@ -153,7 +156,8 @@ bool C_extension::Exec_C_JR() {
rs1 = get_rs1(); rs1 = get_rs1();
mem_addr = 0; mem_addr = 0;
new_pc = static_cast<std::int32_t>(static_cast<std::int32_t>((regs->getValue(rs1)) + static_cast<std::int32_t>(mem_addr)) & 0xFFFFFFFE); new_pc = static_cast<std::int32_t>(
static_cast<std::int32_t>((regs->getValue(rs1)) + static_cast<std::int32_t>(mem_addr)) & 0xFFFFFFFE);
logger->debug("{} ns. PC: 0x{:x}. C.JR: PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), new_pc); logger->debug("{} ns. PC: 0x{:x}. C.JR: PC <- 0x{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), new_pc);
@ -173,7 +177,8 @@ bool C_extension::Exec_C_MV() {
calc = regs->getValue(rs1) + regs->getValue(rs2); calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.MV: x{:d}(0x{:x}) + x{:d}(0x{:x}) -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.MV: x{:d}(0x{:x}) + x{:d}(0x{:x}) -> x{:d}(0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), rd, calc); rs1, regs->getValue(rs1), rs2, regs->getValue(rs2), rd, calc);
return true; return true;
@ -190,7 +195,8 @@ bool C_extension::Exec_C_ADD() {
calc = regs->getValue(rs1) + regs->getValue(rs2); calc = regs->getValue(rs1) + regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.ADD: x{:d} + x{} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.ADD: x{:d} + x{} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, calc); rs1, rs2, rd, calc);
return true; return true;
@ -215,7 +221,8 @@ bool C_extension::Exec_C_LWSP() {
regs->setValue(rd, data); regs->setValue(rd, data);
logger->debug("{} ns. PC: 0x{:x}. C.LWSP: x{:d} + {:d}(@0x{:x}) -> x{:d}({:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.LWSP: x{:d} + {:d}(@0x{:x}) -> x{:d}({:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, mem_addr, rd, data); rs1, imm, mem_addr, rd, data);
return true; return true;
@ -238,7 +245,8 @@ bool C_extension::Exec_C_ADDI4SPN() {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm; calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
logger->debug("{} ns. PC: 0x{:x}. C.ADDI4SN: x{:d} + (0x{:x}) + {:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.ADDI4SN: x{:d} + (0x{:x}) + {:d} -> x{:d}(0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, rd, calc); rs1, regs->getValue(rs1), imm, rd, calc);
return true; return true;
@ -260,7 +268,8 @@ bool C_extension::Exec_C_ADDI16SP() {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm; calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
logger->debug("{} ns. PC: 0x{:x}. C.ADDI16SP: x{:d} + {:d} -> x{:d} (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.ADDI16SP: x{:d} + {:d} -> x{:d} (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, imm, rd, calc); rs1, imm, rd, calc);
} else { } else {
/* C.LUI OPCODE */ /* C.LUI OPCODE */
@ -292,7 +301,8 @@ bool C_extension::Exec_C_SWSP() {
mem_intf->writeDataMem(mem_addr, data, 4); mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite(); perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. C.SWSP: x{:d}(0x{:x}) -> x{:d} + {} (@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.SWSP: x{:d}(0x{:x}) -> x{:d} + {} (@0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, data, rs1, imm, mem_addr); rs2, data, rs1, imm, mem_addr);
return true; return true;
@ -314,7 +324,8 @@ bool C_extension::Exec_C_BEQZ() {
new_pc = static_cast<std::int32_t>(regs->getPC()); new_pc = static_cast<std::int32_t>(regs->getPC());
} }
logger->debug("{} ns. PC: 0x{:x}. C.BEQZ: x{:d}(0x{:x}) == 0? -> PC (0xx{:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.BEQZ: x{:d}(0x{:x}) == 0? -> PC (0xx{:d})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, new_pc); rs1, val1, new_pc);
return true; return true;
@ -336,7 +347,8 @@ bool C_extension::Exec_C_BNEZ() {
new_pc = static_cast<std::int32_t>(regs->getPC()); new_pc = static_cast<std::int32_t>(regs->getPC());
} }
logger->debug("{} ns. PC: 0x{:x}. C.BNEZ: x{:d}(0x{:x}) != 0? -> PC (0xx{:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.BNEZ: x{:d}(0x{:x}) != 0? -> PC (0xx{:d})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, val1, new_pc); rs1, val1, new_pc);
return true; return true;
@ -354,7 +366,8 @@ bool C_extension::Exec_C_LI() {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm; calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
logger->debug("{} ns. PC: 0x{:x}. C.LI: x{:d} ({:d}) + {:d} -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.LI: x{:d} ({:d}) + {:d} -> x{:d}(0x{:x}) ",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, rd, calc); rs1, regs->getValue(rs1), imm, rd, calc);
return true; return true;
@ -374,7 +387,8 @@ bool C_extension::Exec_C_SRLI() {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift; calc = static_cast<std::uint32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.SRLI: x{:d} >> {} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.SRLI: x{:d} >> {} -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd); rs1, shift, rd);
return true; return true;
@ -394,7 +408,8 @@ bool C_extension::Exec_C_SRAI() {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift; calc = static_cast<std::int32_t>(regs->getValue(rs1)) >> shift;
regs->setValue(rd, calc); regs->setValue(rd, calc);
logger->debug("{} ns. PC: 0x{:x}. C.SRAI: x{:d} >> {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.SRAI: x{:d} >> {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd, calc); rs1, shift, rd, calc);
return true; return true;
@ -414,7 +429,8 @@ bool C_extension::Exec_C_SLLI() {
calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift; calc = static_cast<std::uint32_t>(regs->getValue(rs1)) << shift;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.SLLI: x{:d} << {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.SLLI: x{:d} << {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, shift, rd, calc); rs1, shift, rd, calc);
return true; return true;
@ -434,7 +450,8 @@ bool C_extension::Exec_C_ANDI() {
calc = aux & imm; calc = aux & imm;
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.ANDI: x{:d}(0x{:x}) AND 0x{:x} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.ANDI: x{:d}(0x{:x}) AND 0x{:x} -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, aux, imm, rd); rs1, aux, imm, rd);
return true; return true;
@ -451,7 +468,8 @@ bool C_extension::Exec_C_SUB() {
calc = regs->getValue(rs1) - regs->getValue(rs2); calc = regs->getValue(rs1) - regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.SUB: x{:d} - x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.SUB: x{:d} - x{:d} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, calc); rs1, rs2, rd, calc);
return true; return true;
@ -468,7 +486,8 @@ bool C_extension::Exec_C_XOR() {
calc = regs->getValue(rs1) ^ regs->getValue(rs2); calc = regs->getValue(rs1) ^ regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.XOR: x{:d} XOR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.XOR: x{:d} XOR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd); rs1, rs2, rd);
return true; return true;
@ -485,7 +504,8 @@ bool C_extension::Exec_C_OR() {
calc = regs->getValue(rs1) | regs->getValue(rs2); calc = regs->getValue(rs1) | regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.OR: x{:d} OR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.OR: x{:d} OR x{:d} -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd); rs1, rs2, rd);
return true; return true;
@ -502,7 +522,8 @@ bool C_extension::Exec_C_AND() {
calc = regs->getValue(rs1) & regs->getValue(rs2); calc = regs->getValue(rs1) & regs->getValue(rs2);
regs->setValue(rd, static_cast<std::int32_t>(calc)); regs->setValue(rd, static_cast<std::int32_t>(calc));
logger->debug("{} ns. PC: 0x{:x}. C.AND: x{:d} AND x{:d} -> x{:d}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.AND: x{:d} AND x{:d} -> x{:d}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd); rs1, rs2, rd);
return true; return true;
@ -520,7 +541,8 @@ bool C_extension::Exec_C_ADDI() const {
calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm; calc = static_cast<std::int32_t>(regs->getValue(rs1)) + imm;
regs->setValue(rd, calc); regs->setValue(rd, calc);
logger->debug("{} ns. PC: 0x{:x}. C.ADDI: x{:d} + {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), rs1, imm, rd, calc); logger->debug("{} ns. PC: 0x{:x}. C.ADDI: x{:d} + {} -> x{:d}(0x{:x})", sc_core::sc_time_stamp().value(),
regs->getPC(), rs1, imm, rd, calc);
return true; return true;
} }
@ -539,7 +561,8 @@ bool C_extension::Exec_C_JALR() {
new_pc = static_cast<std::int32_t>((regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE); new_pc = static_cast<std::int32_t>((regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE);
regs->setPC(new_pc); regs->setPC(new_pc);
logger->debug("{} ns. PC: 0x{:x}. C.JALR: x{:d} <- 0x{:x} PC <- 0xx{:x}", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.JALR: x{:d} <- 0x{:x} PC <- 0xx{:x}", sc_core::sc_time_stamp().value(),
regs->getPC(),
rd, old_pc + 4, new_pc); rd, old_pc + 4, new_pc);
return true; return true;
@ -560,7 +583,8 @@ bool C_extension::Exec_C_LW() {
perf->dataMemoryRead(); perf->dataMemoryRead();
regs->setValue(rd, static_cast<std::int32_t>(data)); regs->setValue(rd, static_cast<std::int32_t>(data));
logger->debug("{} ns. PC: 0x{:x}. C.LW: x{:d}(0x{:x}) + {:d} (@0x{:x}) -> {:d} (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.LW: x{:d}(0x{:x}) + {:d} (@0x{:x}) -> {:d} (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, regs->getValue(rs1), imm, mem_addr, rd, data); rs1, regs->getValue(rs1), imm, mem_addr, rd, data);
return true; return true;
@ -582,7 +606,8 @@ bool C_extension::Exec_C_SW() {
mem_intf->writeDataMem(mem_addr, data, 4); mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite(); perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. C.SW: x{:d}(0x{:x}) -> x{:d} + 0x{:x}(@0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.SW: x{:d}(0x{:x}) -> x{:d} + 0x{:x}(@0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rs2, data, rs1, imm, mem_addr); rs2, data, rs1, imm, mem_addr);
return true; return true;
@ -603,7 +628,8 @@ bool C_extension::Exec_C_JAL(int m_rd) {
old_pc = old_pc + 2; old_pc = old_pc + 2;
regs->setValue(rd, old_pc); regs->setValue(rd, old_pc);
logger->debug("{} ns. PC: 0x{:x}. C.JAL: x{:d} <- 0x{:x}. PC + 0x{:x} -> PC (0x{:x})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. C.JAL: x{:d} <- 0x{:x}. PC + 0x{:x} -> PC (0x{:x})",
sc_core::sc_time_stamp().value(), regs->getPC(),
rd, old_pc, mem_addr, new_pc); rd, old_pc, mem_addr, new_pc);
return true; return true;
@ -723,3 +749,5 @@ bool C_extension::process_instruction(Instruction &inst, bool *breakpoint) {
return PC_not_affected; return PC_not_affected;
} }
}

6
src/Debug.cpp
View File

@ -18,10 +18,12 @@
#include "Debug.h" #include "Debug.h"
namespace riscv_tlm {
constexpr char nibble_to_hex[16] = {'0', '1', '2', '3', '4', '5', '6', '7', constexpr char nibble_to_hex[16] = {'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', 'a', 'b', 'c', 'd', 'e', 'f'}; '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'};
Debug::Debug(CPU *cpu, Memory* mem): sc_module(sc_core::sc_module_name("Debug")) { Debug::Debug(riscv_tlm::CPU *cpu, Memory *mem) : sc_module(sc_core::sc_module_name("Debug")) {
dbg_cpu = cpu; dbg_cpu = cpu;
dbg_mem = mem; dbg_mem = mem;
@ -249,3 +251,5 @@ std::string Debug::compute_checksum_string(const std::string &msg) {
return {high, low}; return {high, low};
} }
}

4
src/Instruction.cpp
View File

@ -8,6 +8,8 @@
#include "Instruction.h" #include "Instruction.h"
namespace riscv_tlm {
Instruction::Instruction(std::uint32_t instr) { Instruction::Instruction(std::uint32_t instr) {
m_instr = instr; m_instr = instr;
} }
@ -29,5 +31,5 @@ extension_t Instruction::check_extension() const {
} }
} }
}

28
src/M_extension.cpp
View File

@ -8,6 +8,8 @@
#include "M_extension.h" #include "M_extension.h"
namespace riscv_tlm {
op_M_Codes M_extension::decode() const { op_M_Codes M_extension::decode() const {
switch (opcode()) { switch (opcode()) {
@ -59,7 +61,8 @@ bool M_extension::Exec_M_MUL() const {
result = result & 0x00000000FFFFFFFF; result = result & 0x00000000FFFFFFFF;
regs->setValue(rd, static_cast<std::int32_t>(result)); regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.MUL: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. M.MUL: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result); rs1, rs2, rd, result);
return true; return true;
@ -83,7 +86,8 @@ bool M_extension::Exec_M_MULH() const {
ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF); ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value); regs->setValue(rd, ret_value);
logger->debug("{} ns. PC: 0x{:x}. M.MULH: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. M.MULH: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result); rs1, rs2, rd, result);
return true; return true;
@ -106,7 +110,8 @@ bool M_extension::Exec_M_MULHSU() const {
result = (result >> 32) & 0x00000000FFFFFFFF; result = (result >> 32) & 0x00000000FFFFFFFF;
regs->setValue(rd, static_cast<std::int32_t>(result)); regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.MULHSU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. M.MULHSU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result); rs1, rs2, rd, result);
return true; return true;
@ -129,7 +134,8 @@ bool M_extension::Exec_M_MULHU() const {
ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF); ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value); regs->setValue(rd, ret_value);
logger->debug("{} ns. PC: 0x{:x}. M.MULHU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. M.MULHU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result); rs1, rs2, rd, result);
return true; return true;
@ -158,7 +164,8 @@ bool M_extension::Exec_M_DIV() const {
regs->setValue(rd, static_cast<std::int32_t>(result)); regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.DIV: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. M.DIV: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result); rs1, rs2, rd, result);
return true; return true;
@ -185,7 +192,8 @@ bool M_extension::Exec_M_DIVU() const {
regs->setValue(rd, static_cast<std::int32_t>(result)); regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.DIVU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. M.DIVU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result); rs1, rs2, rd, result);
return true; return true;
@ -213,7 +221,8 @@ bool M_extension::Exec_M_REM() const {
regs->setValue(rd, result); regs->setValue(rd, result);
logger->debug("{} ns. PC: 0x{:x}. M.REM: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. M.REM: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result); rs1, rs2, rd, result);
return true; return true;
@ -239,7 +248,8 @@ bool M_extension::Exec_M_REMU() const {
regs->setValue(rd, static_cast<std::int32_t>(result)); regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.REMU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(), logger->debug("{} ns. PC: 0x{:x}. M.REMU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result); rs1, rs2, rd, result);
return true; return true;
@ -285,3 +295,5 @@ bool M_extension::process_instruction(Instruction &inst) {
return PC_not_affected; return PC_not_affected;
} }
}

5
src/Memory.cpp
View File

@ -8,7 +8,10 @@
#include "Memory.h" #include "Memory.h"
namespace riscv_tlm {
SC_HAS_PROCESS(Memory); SC_HAS_PROCESS(Memory);
Memory::Memory(sc_core::sc_module_name const &name, std::string const &filename) : Memory::Memory(sc_core::sc_module_name const &name, std::string const &filename) :
sc_module(name), socket("socket"), LATENCY(sc_core::SC_ZERO_TIME) { sc_module(name), socket("socket"), LATENCY(sc_core::SC_ZERO_TIME) {
// Register callbacks for incoming interface method calls // Register callbacks for incoming interface method calls
@ -42,6 +45,7 @@ std::uint32_t Memory::getPCfromHEX() {
return program_counter; return program_counter;
} }
void Memory::b_transport(tlm::tlm_generic_payload &trans, void Memory::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) { sc_core::sc_time &delay) {
tlm::tlm_command cmd = trans.get_command(); tlm::tlm_command cmd = trans.get_command();
@ -199,3 +203,4 @@ void Memory::readHexFile(std::string const& filename) {
SC_REPORT_ERROR("Memory", "Open file error"); SC_REPORT_ERROR("Memory", "Open file error");
} }
} }
}

2
src/MemoryInterface.cpp
View File

@ -8,6 +8,7 @@
#include "MemoryInterface.h" #include "MemoryInterface.h"
namespace riscv_tlm {
MemoryInterface::MemoryInterface() : MemoryInterface::MemoryInterface() :
data_bus("data_bus") {} data_bus("data_bus") {}
@ -62,3 +63,4 @@ void MemoryInterface::writeDataMem(std::uint32_t addr, std::uint32_t data, int s
data_bus->b_transport(trans, delay); data_bus->b_transport(trans, delay);
} }
}

3
src/Registers.cpp
View File

@ -8,6 +8,8 @@
#include "Registers.h" #include "Registers.h"
namespace riscv_tlm {
Registers::Registers() { Registers::Registers() {
perf = Performance::getInstance(); perf = Performance::getInstance();
@ -171,3 +173,4 @@ void Registers::initCSR() {
| MISA_A_EXTENSION | MISA_I_BASE; | MISA_A_EXTENSION | MISA_I_BASE;
CSR[CSR_MSTATUS] = MISA_MXL; CSR[CSR_MSTATUS] = MISA_MXL;
} }
}

22
src/Simulator.cpp
View File

@ -39,23 +39,23 @@ uint32_t dump_addr_end = 0;
*/ */
class Simulator : sc_core::sc_module { class Simulator : sc_core::sc_module {
public: public:
CPU *cpu; riscv_tlm::CPU *cpu;
Memory *MainMemory; riscv_tlm::Memory *MainMemory;
BusCtrl *Bus; riscv_tlm::BusCtrl *Bus;
Trace *trace; riscv_tlm::peripherals::Trace *trace;
Timer *timer; riscv_tlm::peripherals::Timer *timer;
explicit Simulator(sc_core::sc_module_name const &name): sc_module(name) { explicit Simulator(sc_core::sc_module_name const &name): sc_module(name) {
std::uint32_t start_PC; std::uint32_t start_PC;
MainMemory = new Memory("Main_Memory", filename); MainMemory = new riscv_tlm::Memory("Main_Memory", filename);
start_PC = MainMemory->getPCfromHEX(); start_PC = MainMemory->getPCfromHEX();
cpu = new CPU("cpu", start_PC, debug_session); cpu = new riscv_tlm::CPU("cpu", start_PC, debug_session);
Bus = new BusCtrl("BusCtrl"); Bus = new riscv_tlm::BusCtrl("BusCtrl");
trace = new Trace("Trace"); trace = new riscv_tlm::peripherals::Trace("Trace");
timer = new Timer("Timer"); timer = new riscv_tlm::peripherals::Timer("Timer");
cpu->instr_bus.bind(Bus->cpu_instr_socket); cpu->instr_bus.bind(Bus->cpu_instr_socket);
cpu->mem_intf->data_bus.bind(Bus->cpu_data_socket); cpu->mem_intf->data_bus.bind(Bus->cpu_data_socket);
@ -67,7 +67,7 @@ public:
timer->irq_line.bind(cpu->irq_line_socket); timer->irq_line.bind(cpu->irq_line_socket);
if (debug_session) { if (debug_session) {
Debug debug(cpu, MainMemory); riscv_tlm::Debug debug(cpu, MainMemory);
} }
} }

4
src/Timer.cpp
View File

@ -9,7 +9,9 @@
#include <cstdint> #include <cstdint>
#include "Timer.h" #include "Timer.h"
namespace riscv_tlm::peripherals {
SC_HAS_PROCESS(Timer); SC_HAS_PROCESS(Timer);
Timer::Timer(sc_core::sc_module_name const &name) : Timer::Timer(sc_core::sc_module_name const &name) :
sc_module(name), socket("timer_socket"), m_mtime(0), m_mtimecmp(0) { sc_module(name), socket("timer_socket"), m_mtime(0), m_mtimecmp(0) {
@ -99,3 +101,5 @@ void Timer::b_transport(tlm::tlm_generic_payload &trans,
trans.set_response_status(tlm::TLM_OK_RESPONSE); trans.set_response_status(tlm::TLM_OK_RESPONSE);
} }
}

5
src/Trace.cpp
View File

@ -20,6 +20,8 @@
#include "Trace.h" #include "Trace.h"
namespace riscv_tlm::peripherals {
void Trace::xtermLaunch(char *slaveName) const { void Trace::xtermLaunch(char *slaveName) const {
char *arg; char *arg;
char *fin = &(slaveName[strlen(slaveName) - 2]); char *fin = &(slaveName[strlen(slaveName) - 2]);
@ -86,6 +88,7 @@ void Trace::xtermSetup() {
} }
SC_HAS_PROCESS(Trace); SC_HAS_PROCESS(Trace);
Trace::Trace(sc_core::sc_module_name const &name) : Trace::Trace(sc_core::sc_module_name const &name) :
sc_module(name), socket("socket") { sc_module(name), socket("socket") {
@ -109,3 +112,5 @@ void Trace::b_transport(tlm::tlm_generic_payload &trans,
trans.set_response_status(tlm::TLM_OK_RESPONSE); trans.set_response_status(tlm::TLM_OK_RESPONSE);
} }
}

3
src/extension_base.cpp
View File

@ -8,6 +8,8 @@
#include "extension_base.h" #include "extension_base.h"
namespace riscv_tlm {
extension_base::extension_base(const sc_dt::sc_uint<32> &instr, extension_base::extension_base(const sc_dt::sc_uint<32> &instr,
Registers *register_bank, MemoryInterface *mem_interface) : Registers *register_bank, MemoryInterface *mem_interface) :
m_instr(instr), regs(register_bank), mem_intf(mem_interface) { m_instr(instr), regs(register_bank), mem_intf(mem_interface) {
@ -58,3 +60,4 @@ bool extension_base::NOP() {
sc_core::sc_stop(); sc_core::sc_stop();
return true; return true;
} }
}