colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added namespace to project

This commit is contained in:
mariusmonton 2021-11-29 20:35:26 +01:00
parent e2981d8a50
commit fb84f197bf
28 changed files with 4895 additions and 4632 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

144
inc/A_extension.h
View File

@ -17,84 +17,98 @@
#include "MemoryInterface.h"
#include "extension_base.h"
typedef enum {
OP_A_LR,
OP_A_SC,
OP_A_AMOSWAP,
OP_A_AMOADD,
OP_A_AMOXOR,
OP_A_AMOAND,
OP_A_AMOOR,
OP_A_AMOMIN,
OP_A_AMOMAX,
OP_A_AMOMINU,
OP_A_AMOMAXU,
namespace riscv_tlm {
OP_A_ERROR
} op_A_Codes;
typedef enum {
OP_A_LR,
OP_A_SC,
OP_A_AMOSWAP,
OP_A_AMOADD,
OP_A_AMOXOR,
OP_A_AMOAND,
OP_A_AMOOR,
OP_A_AMOMIN,
OP_A_AMOMAX,
OP_A_AMOMINU,
OP_A_AMOMAXU,
typedef enum {
A_LR = 0b00010,
A_SC = 0b00011,
A_AMOSWAP = 0b00001,
A_AMOADD = 0b00000,
A_AMOXOR = 0b00100,
A_AMOAND = 0b01100,
A_AMOOR = 0b01000,
A_AMOMIN = 0b10000,
A_AMOMAX = 0b10100,
A_AMOMINU = 0b11000,
A_AMOMAXU = 0b11100,
} A_Codes;
OP_A_ERROR
} op_A_Codes;
typedef enum {
A_LR = 0b00010,
A_SC = 0b00011,
A_AMOSWAP = 0b00001,
A_AMOADD = 0b00000,
A_AMOXOR = 0b00100,
A_AMOAND = 0b01100,
A_AMOOR = 0b01000,
A_AMOMIN = 0b10000,
A_AMOMAX = 0b10100,
A_AMOMINU = 0b11000,
A_AMOMAXU = 0b11100,
} A_Codes;
/**
* @brief Instruction decoding and fields access
*/
class A_extension: public extension_base {
public:
class A_extension : public extension_base {
public:
/**
* @brief Constructor, same as base class
*/
using extension_base::extension_base;
/**
* @brief Constructor, same as base class
*/
using extension_base::extension_base;
/**
* @brief Access to opcode field
* @return return opcode field
*/
inline int32_t opcode() const override {
return static_cast<int32_t>(m_instr.range(31, 27));
}
/**
* @brief Access to opcode field
* @return return opcode field
*/
inline int32_t opcode() const override {
return static_cast<int32_t>(m_instr.range(31, 27));
}
/**
* @brief Decodes opcode of instruction
* @return opcode of instruction
*/
op_A_Codes decode() const;
/**
* @brief Decodes opcode of instruction
* @return opcode of instruction
*/
op_A_Codes decode() const;
inline void dump() const override {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
}
inline void dump() const override {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
}
bool Exec_A_LR();
bool Exec_A_SC();
bool Exec_A_AMOSWAP() const;
bool Exec_A_AMOADD() const;
bool Exec_A_AMOXOR() const;
bool Exec_A_AMOAND() const;
bool Exec_A_AMOOR() const;
bool Exec_A_AMOMIN() const;
bool Exec_A_AMOMAX() const;
bool Exec_A_AMOMINU() const;
bool Exec_A_AMOMAXU() const;
bool Exec_A_LR();
bool process_instruction(Instruction &inst);
bool Exec_A_SC();
void TLB_reserve(std::uint32_t address);
bool TLB_reserved(std::uint32_t address);
bool Exec_A_AMOSWAP() const;
private:
std::unordered_set<std::uint32_t> TLB_A_Entries;
};
bool Exec_A_AMOADD() const;
bool Exec_A_AMOXOR() const;
bool Exec_A_AMOAND() const;
bool Exec_A_AMOOR() const;
bool Exec_A_AMOMIN() const;
bool Exec_A_AMOMAX() const;
bool Exec_A_AMOMINU() const;
bool Exec_A_AMOMAXU() const;
bool process_instruction(Instruction &inst);
void TLB_reserve(std::uint32_t address);
bool TLB_reserved(std::uint32_t address);
private:
std::unordered_set<std::uint32_t> TLB_A_Entries;
};
}
#endif

567
inc/BASE_ISA.h
View File

@ -23,324 +23,367 @@
#include "A_extension.h"
#include "Registers.h"
typedef enum {
OP_LUI,
OP_AUIPC,
OP_JAL,
OP_JALR,
namespace riscv_tlm {
OP_BEQ,
OP_BNE,
OP_BLT,
OP_BGE,
OP_BLTU,
OP_BGEU,
typedef enum {
OP_LUI,
OP_AUIPC,
OP_JAL,
OP_JALR,
OP_LB,
OP_LH,
OP_LW,
OP_LBU,
OP_LHU,
OP_BEQ,
OP_BNE,
OP_BLT,
OP_BGE,
OP_BLTU,
OP_BGEU,
OP_SB,
OP_SH,
OP_SW,
OP_LB,
OP_LH,
OP_LW,
OP_LBU,
OP_LHU,
OP_ADDI,
OP_SLTI,
OP_SLTIU,
OP_XORI,
OP_ORI,
OP_ANDI,
OP_SLLI,
OP_SRLI,
OP_SRAI,
OP_SB,
OP_SH,
OP_SW,
OP_ADD,
OP_SUB,
OP_SLL,
OP_SLT,
OP_SLTU,
OP_XOR,
OP_SRL,
OP_SRA,
OP_OR,
OP_AND,
OP_ADDI,
OP_SLTI,
OP_SLTIU,
OP_XORI,
OP_ORI,
OP_ANDI,
OP_SLLI,
OP_SRLI,
OP_SRAI,
OP_FENCE,
OP_ECALL,
OP_EBREAK,
OP_ADD,
OP_SUB,
OP_SLL,
OP_SLT,
OP_SLTU,
OP_XOR,
OP_SRL,
OP_SRA,
OP_OR,
OP_AND,
OP_CSRRW,
OP_CSRRS,
OP_CSRRC,
OP_CSRRWI,
OP_CSRRSI,
OP_CSRRCI,
OP_FENCE,
OP_ECALL,
OP_EBREAK,
OP_URET,
OP_SRET,
OP_MRET,
OP_WFI,
OP_SFENCE,
OP_CSRRW,
OP_CSRRS,
OP_CSRRC,
OP_CSRRWI,
OP_CSRRSI,
OP_CSRRCI,
OP_ERROR
} opCodes;
OP_URET,
OP_SRET,
OP_MRET,
OP_WFI,
OP_SFENCE,
OP_ERROR
} opCodes;
/**
* @brief Risc_V execute module
*/
class BASE_ISA: public extension_base {
public:
class BASE_ISA : public extension_base {
public:
/**
* @brief Constructor, same as base class
*/
using extension_base::extension_base;
/**
* @brief Constructor, same as base class
*/
using extension_base::extension_base;
/**
* @brief Access to funct7 field
* @return funct7 field
*/
inline std::int32_t get_funct7() const {
return m_instr.range(31, 25);
}
/**
* @brief Access to funct7 field
* @return funct7 field
*/
inline std::int32_t get_funct7() const {
return m_instr.range(31, 25);
}
/**
* @brief Sets func7 field
* @param value desired func7 value
*/
inline void set_func7(std::int32_t value) {
m_instr.range(31, 25) = value;
}
/**
* @brief Sets func7 field
* @param value desired func7 value
*/
inline void set_func7(std::int32_t value) {
m_instr.range(31, 25) = value;
}
/**
* @brief Gets immediate field value for I-type
* @return immediate_I field
*/
inline std::int32_t get_imm_I() const {
std::int32_t aux = 0;
/**
* @brief Gets immediate field value for I-type
* @return immediate_I field
*/
inline std::int32_t get_imm_I() const {
std::uint32_t aux = 0;
aux = m_instr.range(31, 20);
aux = m_instr.range(31, 20);
/* sign extension (optimize) */
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
/* sign extension (optimize) */
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
return static_cast<std::int32_t>(aux);
}
/**
* @brief Sets immediate field for I-type
* @param value desired I value
*/
inline void set_imm_I(std::int32_t value) {
m_instr.range(31, 20) = value;
}
/**
* @brief Sets immediate field for I-type
* @param value desired I value
*/
inline void set_imm_I(std::int32_t value) {
m_instr.range(31, 20) = value;
}
/**
* @brief Gets immediate field value for S-type
* @return immediate_S field
*/
inline std::int32_t get_imm_S() const {
std::int32_t aux = 0;
/**
* @brief Gets immediate field value for S-type
* @return immediate_S field
*/
inline std::int32_t get_imm_S() const {
std::uint32_t aux = 0;
aux = m_instr.range(31, 25) << 5;
aux |= m_instr.range(11, 7);
aux = m_instr.range(31, 25) << 5;
aux |= m_instr.range(11, 7);
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
return static_cast<std::int32_t>(aux);
}
/**
* @brief Gets immediate field value for U-type
* @return immediate_U field
*/
inline std::int32_t get_imm_U() const {
return m_instr.range(31, 12);
}
/**
* @brief Gets immediate field value for U-type
* @return immediate_U field
*/
inline std::int32_t get_imm_U() const {
return static_cast<std::int32_t>(m_instr.range(31, 12));
}
/**
* @brief Sets immediate field for U-type
* @param value desired U value
*/
inline void set_imm_U(std::int32_t value) {
m_instr.range(31, 12) = (value << 12);
}
/**
* @brief Sets immediate field for U-type
* @param value desired U value
*/
inline void set_imm_U(std::int32_t value) {
m_instr.range(31, 12) = (value << 12);
}
/**
* @brief Gets immediate field value for B-type
* @return immediate_B field
*/
inline std::int32_t get_imm_B() const {
std::int32_t aux = 0;
/**
* @brief Gets immediate field value for B-type
* @return immediate_B field
*/
inline std::int32_t get_imm_B() const {
std::int32_t aux = 0;
aux |= m_instr[7] << 11;
aux |= m_instr.range(30, 25) << 5;
aux |= m_instr[31] << 12;
aux |= m_instr.range(11, 8) << 1;
aux |= m_instr[7] << 11;
aux |= m_instr.range(30, 25) << 5;
aux |= m_instr[31] << 12;
aux |= m_instr.range(11, 8) << 1;
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
return aux;
}
/**
* @brief Sets immediate field for B-type
* @param value desired B value
*/
inline void set_imm_B(std::int32_t value) {
sc_dt::sc_uint<32> aux = value;
/**
* @brief Sets immediate field for B-type
* @param value desired B value
*/
inline void set_imm_B(std::int32_t value) {
sc_dt::sc_uint<32> aux = value;
m_instr[31] = aux[12];
m_instr.range(30, 25) = aux.range(10, 5);
m_instr.range(11, 7) = aux.range(4, 1);
m_instr[6] = aux[11];
}
m_instr[31] = aux[12];
m_instr.range(30, 25) = aux.range(10, 5);
m_instr.range(11, 7) = aux.range(4, 1);
m_instr[6] = aux[11];
}
/**
* @brief Gets immediate field value for J-type
* @return immediate_J field
*/
inline std::int32_t get_imm_J() const {
std::int32_t aux = 0;
/**
* @brief Gets immediate field value for J-type
* @return immediate_J field
*/
inline std::int32_t get_imm_J() const {
std::int32_t aux = 0;
aux = m_instr[31] << 20;
aux |= m_instr.range(19, 12) << 12;
aux |= m_instr[20] << 11;
aux |= m_instr.range(30, 21) << 1;
aux = m_instr[31] << 20;
aux |= m_instr.range(19, 12) << 12;
aux |= m_instr[20] << 11;
aux |= m_instr.range(30, 21) << 1;
/* bit extension (better way to do that?) */
if (m_instr[31] == 1) {
aux |= (0b111111111111) << 20;
}
/* bit extension (better way to do that?) */
if (m_instr[31] == 1) {
aux |= (0b111111111111) << 20;
}
return aux;
}
return aux;
}
/**
* @brief Sets immediate field for J-type
* @param value desired J value
*/
inline void set_imm_J(std::int32_t value) {
sc_dt::sc_uint<32> aux = (value << 20);
/**
* @brief Sets immediate field for J-type
* @param value desired J value
*/
inline void set_imm_J(std::int32_t value) {
sc_dt::sc_uint<32> aux = (value << 20);
m_instr[31] = aux[20];
m_instr.range(30, 21) = aux.range(10, 1);
m_instr[20] = aux[11];
m_instr.range(19, 12) = aux.range(19, 12);
}
m_instr[31] = aux[20];
m_instr.range(30, 21) = aux.range(10, 1);
m_instr[20] = aux[11];
m_instr.range(19, 12) = aux.range(19, 12);
}
/**
* @brief Returns shamt field for Shifts instructions
* @return value corresponding to inst(25:20)
*/
inline std::int32_t get_shamt() const {
return static_cast<std::int32_t>(m_instr.range(25, 20));
}
/**
* @brief Returns shamt field for Shifts instructions
* @return value corresponding to inst(25:20)
*/
inline std::int32_t get_shamt() const {
return static_cast<std::int32_t>(m_instr.range(25, 20));
}
/**
* @brief Returns CSR field for CSR instructions
* @return value corresponding to instr(31:20)
*/
inline std::int32_t get_csr() const {
std::int32_t aux = 0;
/**
* @brief Returns CSR field for CSR instructions
* @return value corresponding to instr(31:20)
*/
inline std::int32_t get_csr() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(31, 20));
aux = static_cast<std::int32_t>(m_instr.range(31, 20));
return aux;
}
return aux;
}
/**
* @brief Access to opcode field
* @return return opcode field
*/
inline std::int32_t opcode() const override {
return static_cast<std::int32_t>(m_instr.range(6, 0));
}
/**
* @brief Access to opcode field
* @return return opcode field
*/
inline std::int32_t opcode() const override {
return static_cast<std::int32_t>(m_instr.range(6, 0));
}
bool Exec_LUI() const;
bool Exec_AUIPC() const;
bool Exec_LUI() const;
bool Exec_JAL() const;
bool Exec_JALR();
bool Exec_AUIPC() const;
bool Exec_BEQ() const;
bool Exec_BNE() const;
bool Exec_BLT() const;
bool Exec_BGE() const;
bool Exec_BLTU() const;
bool Exec_BGEU() const;
bool Exec_JAL() const;
bool Exec_LB() const;
bool Exec_LH() const;
bool Exec_LW() const;
bool Exec_LBU() const;
bool Exec_LHU() const;
bool Exec_JALR();
bool Exec_SB() const;
bool Exec_SH() const;
bool Exec_SW() const;
bool Exec_SBU() const;
bool Exec_SHU() const;
bool Exec_BEQ() const;
bool Exec_ADDI() const;
bool Exec_SLTI() const;
bool Exec_SLTIU() const;
bool Exec_XORI() const;
bool Exec_ORI() const;
bool Exec_ANDI() const;
bool Exec_SLLI();
bool Exec_SRLI() const;
bool Exec_SRAI() const;
bool Exec_BNE() const;
bool Exec_ADD() const;
bool Exec_SUB() const;
bool Exec_SLL() const;
bool Exec_SLT() const;
bool Exec_SLTU() const;
bool Exec_BLT() const;
bool Exec_XOR() const;
bool Exec_SRL() const;
bool Exec_SRA() const;
bool Exec_OR() const;
bool Exec_AND() const;
bool Exec_BGE() const;
bool Exec_FENCE() const;
bool Exec_ECALL();
bool Exec_EBREAK();
bool Exec_BLTU() const;
bool Exec_CSRRW() const;
bool Exec_CSRRS() const;
bool Exec_CSRRC() const;
bool Exec_CSRRWI() const;
bool Exec_CSRRSI() const;
bool Exec_CSRRCI() const;
bool Exec_BGEU() const;
/*********************** Privileged Instructions ******************************/
bool Exec_MRET() const;
bool Exec_SRET() const;
bool Exec_WFI() const;
bool Exec_SFENCE() const;
bool Exec_LB() const;
/**
* @brief Executes default ISA instruction
* @param inst instruction to execute
* @return true if PC is affected by instruction
*/
bool process_instruction(Instruction &inst, bool *breakpoint = nullptr);
bool Exec_LH() const;
/**
* @brief Decodes opcode of instruction
* @return opcode of instruction
*/
opCodes decode();
};
bool Exec_LW() const;
bool Exec_LBU() const;
bool Exec_LHU() const;
bool Exec_SB() const;
bool Exec_SH() const;
bool Exec_SW() const;
bool Exec_SBU() const;
bool Exec_SHU() const;
bool Exec_ADDI() const;
bool Exec_SLTI() const;
bool Exec_SLTIU() const;
bool Exec_XORI() const;
bool Exec_ORI() const;
bool Exec_ANDI() const;
bool Exec_SLLI();
bool Exec_SRLI() const;
bool Exec_SRAI() const;
bool Exec_ADD() const;
bool Exec_SUB() const;
bool Exec_SLL() const;
bool Exec_SLT() const;
bool Exec_SLTU() const;
bool Exec_XOR() const;
bool Exec_SRL() const;
bool Exec_SRA() const;
bool Exec_OR() const;
bool Exec_AND() const;
bool Exec_FENCE() const;
bool Exec_ECALL();
bool Exec_EBREAK();
bool Exec_CSRRW() const;
bool Exec_CSRRS() const;
bool Exec_CSRRC() const;
bool Exec_CSRRWI() const;
bool Exec_CSRRSI() const;
bool Exec_CSRRCI() const;
/*********************** Privileged Instructions ******************************/
bool Exec_MRET() const;
bool Exec_SRET() const;
bool Exec_WFI() const;
bool Exec_SFENCE() const;
/**
* @brief Executes default ISA instruction
* @param inst instruction to execute
* @return true if PC is affected by instruction
*/
bool process_instruction(Instruction &inst, bool *breakpoint = nullptr);
/**
* @brief Decodes opcode of instruction
* @return opcode of instruction
*/
opCodes decode();
};
}
#endif

81
inc/BusCtrl.h
View File

@ -20,6 +20,8 @@
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
namespace riscv_tlm {
/**
* Memory mapped Trace peripheral address
*/
@ -41,51 +43,52 @@
* It will be expanded with more ports when required (for DMA,
* other peripherals, etc.)
*/
class BusCtrl: sc_core::sc_module {
public:
/**
* @brief TLM target socket CPU instruction memory bus
*/
tlm_utils::simple_target_socket<BusCtrl> cpu_instr_socket;
class BusCtrl : sc_core::sc_module {
public:
/**
* @brief TLM target socket CPU instruction memory bus
*/
tlm_utils::simple_target_socket<BusCtrl> cpu_instr_socket;
/**
* @brief TLM target socket CPU data memory bus
*/
tlm_utils::simple_target_socket<BusCtrl> cpu_data_socket;
/**
* @brief TLM target socket CPU data memory bus
*/
tlm_utils::simple_target_socket<BusCtrl> cpu_data_socket;
/**
* @brief TLM initiator socket Main memory bus
*/
tlm_utils::simple_initiator_socket<BusCtrl> memory_socket;
/**
* @brief TLM initiator socket Main memory bus
*/
tlm_utils::simple_initiator_socket<BusCtrl> memory_socket;
/**
* @brief TLM initiator socket Trace module
*/
tlm_utils::simple_initiator_socket<BusCtrl> trace_socket;
/**
* @brief TLM initiator socket Trace module
*/
tlm_utils::simple_initiator_socket<BusCtrl> trace_socket;
/**
* @brief TLM initiator socket Trace module
*/
tlm_utils::simple_initiator_socket<BusCtrl> timer_socket;
/**
* @brief TLM initiator socket Trace module
*/
tlm_utils::simple_initiator_socket<BusCtrl> timer_socket;
/**
* @brief constructor
* @param name module's name
*/
explicit BusCtrl(sc_core::sc_module_name const &name);
/**
* @brief constructor
* @param name module's name
*/
explicit BusCtrl(sc_core::sc_module_name const &name);
/**
* @brief TLM-2 blocking mechanism
* @param trans transtractino to perform
* @param delay delay associated to this transaction
*/
virtual void b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
/**
* @brief TLM-2 blocking mechanism
* @param trans transtractino to perform
* @param delay delay associated to this transaction
*/
virtual void b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
private:
bool instr_direct_mem_ptr(tlm::tlm_generic_payload&,
tlm::tlm_dmi &dmi_data);
void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
};
private:
bool instr_direct_mem_ptr(tlm::tlm_generic_payload &,
tlm::tlm_dmi &dmi_data);
void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
};
}
#endif

150
inc/CPU.h
View File

@ -26,99 +26,101 @@
#include "M_extension.h"
#include "A_extension.h"
namespace riscv_tlm {
/**
* @brief ISC_V CPU model
* @param name name of the module
*/
class CPU: sc_core::sc_module {
public:
class CPU : sc_core::sc_module {
public:
/**
* @brief Instruction Memory bus socket
* @param trans transction to perfoem
* @param delay time to annotate
*/
tlm_utils::simple_initiator_socket<CPU> instr_bus;
/**
* @brief Instruction Memory bus socket
* @param trans transction to perfoem
* @param delay time to annotate
*/
tlm_utils::simple_initiator_socket<CPU> instr_bus;
/**
* @brief IRQ line socket
* @param trans transction to perform (empty)
* @param delay time to annotate
*/
tlm_utils::simple_target_socket<CPU> irq_line_socket;
/**
* @brief IRQ line socket
* @param trans transction to perform (empty)
* @param delay time to annotate
*/
tlm_utils::simple_target_socket<CPU> irq_line_socket;
/**
* @brief Constructor
* @param name Module name
* @param PC Program Counter initialize value
* @param debug To start debugging
*/
CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug);
/**
* @brief Constructor
* @param name Module name
* @param PC Program Counter initialize value
* @param debug To start debugging
*/
CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug);
/**
* @brief Destructor
*/
~CPU() override;
/**
* @brief Destructor
*/
~CPU() override;
MemoryInterface *mem_intf;
MemoryInterface *mem_intf;
bool CPU_step();
bool CPU_step();
Registers *getRegisterBank() {return register_bank;}
Registers *getRegisterBank() { return register_bank; }
private:
Registers *register_bank;
Performance *perf;
std::shared_ptr<spdlog::logger> logger;
C_extension *c_inst;
M_extension *m_inst;
A_extension *a_inst;
BASE_ISA *exec;
tlm_utils::tlm_quantumkeeper *m_qk;
private:
Registers *register_bank;
Performance *perf;
std::shared_ptr<spdlog::logger> logger;
C_extension *c_inst;
M_extension *m_inst;
A_extension *a_inst;
BASE_ISA *exec;
tlm_utils::tlm_quantumkeeper *m_qk;
Instruction inst;
bool interrupt;
std::uint32_t int_cause;
bool irq_already_down;
sc_core::sc_time default_time;
bool dmi_ptr_valid;
Instruction inst;
bool interrupt;
std::uint32_t int_cause;
bool irq_already_down;
sc_core::sc_time default_time;
bool dmi_ptr_valid;
tlm::tlm_generic_payload trans;
std::uint32_t INSTR;
unsigned char *dmi_ptr = nullptr;
tlm::tlm_generic_payload trans;
std::uint32_t INSTR;
unsigned char *dmi_ptr = nullptr;
/**
*
* @brief Process and triggers IRQ if all conditions met
* @return true if IRQ is triggered, false otherwise
*/
bool cpu_process_IRQ();
/**
*
* @brief Process and triggers IRQ if all conditions met
* @return true if IRQ is triggered, false otherwise
*/
bool cpu_process_IRQ();
/**
* main thread for CPU simulation
* @brief CPU mai thread
*/
[[noreturn]] void CPU_thread();
/**
* main thread for CPU simulation
* @brief CPU mai thread
*/
[[noreturn]] void CPU_thread();
/**
* @brief callback for IRQ simple socket
* @param trans transaction to perform (empty)
* @param delay time to annotate
*
* it triggers an IRQ when called
*/
void call_interrupt(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
/**
* @brief callback for IRQ simple socket
* @param trans transaction to perform (empty)
* @param delay time to annotate
*
* it triggers an IRQ when called
*/
void call_interrupt(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
/**
* DMI pointer is not longer valid
* @param start memory address region start
* @param end memory address region end
*/
void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
};
/**
* DMI pointer is not longer valid
* @param start memory address region start
* @param end memory address region end
*/
void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
};
}
#endif

796
inc/C_extension.h
View File

@ -12,400 +12,426 @@
#include "systemc"
#include "extension_base.h"
typedef enum {
OP_C_ADDI4SPN,
OP_C_FLD,
OP_C_LW,
OP_C_FLW,
OP_C_FSD,
OP_C_SW,
OP_C_FSW,
namespace riscv_tlm {
OP_C_NOP,
OP_C_ADDI,
OP_C_JAL,
OP_C_LI,
OP_C_ADDI16SP,
OP_C_LUI,
OP_C_SRLI,
OP_C_SRAI,
OP_C_ANDI,
OP_C_SUB,
OP_C_XOR,
OP_C_OR,
OP_C_AND,
OP_C_J,
OP_C_BEQZ,
OP_C_BNEZ,
typedef enum {
OP_C_ADDI4SPN,
OP_C_FLD,
OP_C_LW,
OP_C_FLW,
OP_C_FSD,
OP_C_SW,
OP_C_FSW,
OP_C_SLLI,
OP_C_FLDSP,
OP_C_LWSP,
OP_C_FLWSP,
OP_C_JR,
OP_C_MV,
OP_C_EBREAK,
OP_C_JALR,
OP_C_ADD,
OP_C_FSDSP,
OP_C_SWSP,
OP_C_FSWSP,
OP_C_NOP,
OP_C_ADDI,
OP_C_JAL,
OP_C_LI,
OP_C_ADDI16SP,
OP_C_LUI,
OP_C_SRLI,
OP_C_SRAI,
OP_C_ANDI,
OP_C_SUB,
OP_C_XOR,
OP_C_OR,
OP_C_AND,
OP_C_J,
OP_C_BEQZ,
OP_C_BNEZ,
OP_C_ERROR
} op_C_Codes;
OP_C_SLLI,
OP_C_FLDSP,
OP_C_LWSP,
OP_C_FLWSP,
OP_C_JR,
OP_C_MV,
OP_C_EBREAK,
OP_C_JALR,
OP_C_ADD,
OP_C_FSDSP,
OP_C_SWSP,
OP_C_FSWSP,
typedef enum {
C_ADDI4SPN = 0b000,
C_FLD = 0b001,
C_LW = 0b010,
C_FLW = 0b011,
C_FSD = 0b101,
C_SW = 0b110,
C_FSW = 0b111,
OP_C_ERROR
} op_C_Codes;
C_ADDI = 0b000,
C_JAL = 0b001,
C_LI = 0b010,
C_ADDI16SP = 0b011,
C_SRLI = 0b100,
C_2_SRLI = 0b00,
C_2_SRAI = 0b01,
C_2_ANDI = 0b10,
C_2_SUB = 0b11,
C_3_SUB = 0b00,
C_3_XOR = 0b01,
C_3_OR = 0b10,
C_3_AND = 0b11,
C_J = 0b101,
C_BEQZ = 0b110,
C_BNEZ = 0b111,
typedef enum {
C_ADDI4SPN = 0b000,
C_FLD = 0b001,
C_LW = 0b010,
C_FLW = 0b011,
C_FSD = 0b101,
C_SW = 0b110,
C_FSW = 0b111,
C_SLLI = 0b000,
C_FLDSP = 0b001,
C_LWSP = 0b010,
C_FLWSP = 0b011,
C_JR = 0b100,
C_FDSP = 0b101,
C_SWSP = 0b110,
C_FWWSP = 0b111,
} C_Codes;
C_ADDI = 0b000,
C_JAL = 0b001,
C_LI = 0b010,
C_ADDI16SP = 0b011,
C_SRLI = 0b100,
C_2_SRLI = 0b00,
C_2_SRAI = 0b01,
C_2_ANDI = 0b10,
C_2_SUB = 0b11,
C_3_SUB = 0b00,
C_3_XOR = 0b01,
C_3_OR = 0b10,
C_3_AND = 0b11,
C_J = 0b101,
C_BEQZ = 0b110,
C_BNEZ = 0b111,
C_SLLI = 0b000,
C_FLDSP = 0b001,
C_LWSP = 0b010,
C_FLWSP = 0b011,
C_JR = 0b100,
C_FDSP = 0b101,
C_SWSP = 0b110,
C_FWWSP = 0b111,
} C_Codes;
/**
* @brief Instruction decoding and fields access
*/
class C_extension: public extension_base {
public:
/**
* @brief Constructor, same as base clase
*/
using extension_base::extension_base;
/**
* @brief Access to opcode field
* @return return opcode field
*/
inline std::int32_t opcode() const override {
return static_cast<std::int32_t>(m_instr.range(1, 0));
}
inline std::int32_t get_rdp() const {
return static_cast<std::int32_t>(m_instr.range(4, 2) + 8);
}
/**
* @brief Access to rs1 field
* @return rs1 field
*/
inline std::int32_t get_rs1() const override {
return static_cast<std::int32_t>(m_instr.range(11, 7));
}
inline void set_rs1(std::int32_t value) override {
m_instr.range(11, 7) = value;
}
inline std::int32_t get_rs1p() const {
return static_cast<std::int32_t>(m_instr.range(9, 7) + 8);
}
/**
* @brief Access to rs2 field
* @return rs2 field
*/
inline std::int32_t get_rs2() const override {
return static_cast<std::int32_t>(m_instr.range(6, 2));
}
inline void set_rs2(std::int32_t value) override {
m_instr.range(6, 2) = value;
}
inline std::int32_t get_rs2p() const {
return static_cast<std::int32_t>(m_instr.range(4, 2) + 8);
}
inline std::int32_t get_funct3() const override {
return static_cast<std::int32_t>(m_instr.range(15, 13));
}
inline void set_funct3(std::int32_t value) override {
m_instr.range(15, 13) = value;
}
/**
* @brief Access to immediate field for I-type
* @return immediate_I field
*/
inline std::int32_t get_imm_I() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(31, 20));
/* sign extension (optimize) */
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
inline void set_imm_I(std::int32_t value) {
m_instr.range(31, 20) = value;
}
/**
* @brief Access to immediate field for S-type
* @return immediate_S field
*/
inline std::int32_t get_imm_S() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(31, 25) << 5);
aux |= static_cast<std::int32_t>(m_instr.range(11, 7));
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
inline void set_imm_S(std::int32_t value) {
sc_dt::sc_uint<32> aux = value;
m_instr.range(31, 25) = aux.range(11, 5);
m_instr.range(11, 7) = aux.range(4, 0);
}
/**
* @brief Access to immediate field for U-type
* @return immediate_U field
*/
inline std::int32_t get_imm_U() const {
return static_cast<std::int32_t>(m_instr.range(31, 12));
}
inline void set_imm_U(std::int32_t value) {
m_instr.range(31, 12) = (value << 12);
}
/**
* @brief Access to immediate field for B-type
* @return immediate_B field
*/
inline std::int32_t get_imm_B() const {
std::int32_t aux = 0;
aux |= static_cast<std::int32_t>(m_instr[7] << 11);
aux |= static_cast<std::int32_t>(m_instr.range(30, 25) << 5);
aux |= static_cast<std::int32_t>(m_instr[31] << 12);
aux |= static_cast<std::int32_t>(m_instr.range(11, 8) << 1);
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
inline void set_imm_B(std::int32_t value) {
sc_dt::sc_uint<32> aux = value;
m_instr[31] = aux[12];
m_instr.range(30, 25) = aux.range(10, 5);
m_instr.range(11, 7) = aux.range(4, 1);
m_instr[6] = aux[11];
}
/**
* @brief Access to immediate field for J-type
* @return immediate_J field
*/
inline std::int32_t get_imm_J() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 11);
aux |= static_cast<std::int32_t>(m_instr[11] << 4);
aux |= static_cast<std::int32_t>(m_instr[10] << 9);
aux |= static_cast<std::int32_t>(m_instr[9] << 8);
aux |= static_cast<std::int32_t>(m_instr[8] << 10);
aux |= static_cast<std::int32_t>(m_instr[7] << 6);
aux |= static_cast<std::int32_t>(m_instr[6] << 7);
aux |= static_cast<std::int32_t>(m_instr.range(5, 3) << 1);
aux |= static_cast<std::int32_t>(m_instr[2] << 5);
if (m_instr[12] == 1) {
aux |= 0b11111111111111111111 << 12;
}
return aux;
}
inline void set_imm_J(std::int32_t value) {
sc_dt::sc_uint<32> aux = (value << 20);
m_instr[31] = aux[20];
m_instr.range(30, 21) = aux.range(10, 1);
m_instr[20] = aux[11];
m_instr.range(19, 12) = aux.range(19, 12);
}
inline std::int32_t get_imm_L() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(12, 10) << 3);
aux |= static_cast<std::int32_t>(m_instr[6] << 2);
aux |= static_cast<std::int32_t>(m_instr[5] << 6);
return aux;
}
inline std::int32_t get_imm_LWSP() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 5);
aux |= static_cast<std::int32_t>(m_instr.range(6, 4) << 2);
aux |= static_cast<std::int32_t>(m_instr.range(3, 2) << 6);
return aux;
}
inline std::int32_t get_imm_ADDI () const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 5);
aux |= static_cast<std::int32_t>(m_instr.range(6, 2));
if (m_instr[12] == 1) {
aux |= 0b11111111111111111111111111 << 6;
}
return aux;
}
inline std::int32_t get_imm_ADDI4SPN() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(12, 11) << 4);
aux |= static_cast<std::int32_t>(m_instr.range(10, 7) << 6);
aux |= static_cast<std::int32_t>(m_instr[6] << 2);
aux |= static_cast<std::int32_t>(m_instr[5] << 3);
return aux;
}
inline std::int32_t get_imm_ADDI16SP() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 9);
aux |= static_cast<std::int32_t>(m_instr[6] << 4);
aux |= static_cast<std::int32_t>(m_instr[5] << 6);
aux |= static_cast<std::int32_t>(m_instr[4] << 8);
aux |= static_cast<std::int32_t>(m_instr[3] << 7);
aux |= static_cast<std::int32_t>(m_instr[2] << 5);
if (m_instr[12] == 1) {
aux |= 0b1111111111111111111111 << 10;
}
return aux;
}
inline std::int32_t get_imm_CSS() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(12, 9) << 2);
aux |= static_cast<std::int32_t>(m_instr.range(8, 7) << 6);
return aux;
}
inline std::int32_t get_imm_CB() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 8);
aux |= static_cast<std::int32_t>(m_instr[11] << 4);
aux |= static_cast<std::int32_t>(m_instr[10] << 3);
aux |= static_cast<std::int32_t>(m_instr[6] << 7);
aux |= static_cast<std::int32_t>(m_instr[5] << 6);
aux |= static_cast<std::int32_t>(m_instr[4] << 2);
aux |= static_cast<std::int32_t>(m_instr[3] << 1);
aux |= static_cast<std::int32_t>(m_instr[2] << 5);
if (m_instr[12] == 1) {
aux |= 0b11111111111111111111111 << 9;
}
return aux;
}
inline std::int32_t get_imm_LUI() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 17);
aux |= static_cast<std::int32_t>(m_instr.range(6, 2) << 12);
if (m_instr[12] == 1) {
aux |= 0b111111111111111 << 17;
}
return aux;
}
inline std::int32_t get_csr() const {
return get_imm_I();
}
/**
* @brief Decodes opcode of instruction
* @return opcode of instruction
*/
op_C_Codes decode() const;
bool Exec_C_JR();
bool Exec_C_MV();
bool Exec_C_LWSP();
bool Exec_C_ADDI4SPN();
bool Exec_C_SLLI();
bool Exec_C_ADDI16SP();
bool Exec_C_SWSP();
bool Exec_C_BEQZ();
bool Exec_C_BNEZ();
bool Exec_C_LI();
bool Exec_C_SRLI();
bool Exec_C_SRAI();
bool Exec_C_ANDI();
bool Exec_C_ADD();
bool Exec_C_SUB();
bool Exec_C_XOR();
bool Exec_C_OR();
bool Exec_C_AND();
bool Exec_C_ADDI() const;
bool Exec_C_JALR();
bool Exec_C_LW();
bool Exec_C_SW();
bool Exec_C_JAL(int m_rd);
bool Exec_C_EBREAK();
bool process_instruction(Instruction &inst, bool *breakpoint = nullptr);
};
class C_extension : public extension_base {
public:
/**
* @brief Constructor, same as base clase
*/
using extension_base::extension_base;
/**
* @brief Access to opcode field
* @return return opcode field
*/
inline std::int32_t opcode() const override {
return static_cast<std::int32_t>(m_instr.range(1, 0));
}
inline std::int32_t get_rdp() const {
return static_cast<std::int32_t>(m_instr.range(4, 2) + 8);
}
/**
* @brief Access to rs1 field
* @return rs1 field
*/
inline std::int32_t get_rs1() const override {
return static_cast<std::int32_t>(m_instr.range(11, 7));
}
inline void set_rs1(std::int32_t value) override {
m_instr.range(11, 7) = value;
}
inline std::int32_t get_rs1p() const {
return static_cast<std::int32_t>(m_instr.range(9, 7) + 8);
}
/**
* @brief Access to rs2 field
* @return rs2 field
*/
inline std::int32_t get_rs2() const override {
return static_cast<std::int32_t>(m_instr.range(6, 2));
}
inline void set_rs2(std::int32_t value) override {
m_instr.range(6, 2) = value;
}
inline std::int32_t get_rs2p() const {
return static_cast<std::int32_t>(m_instr.range(4, 2) + 8);
}
inline std::int32_t get_funct3() const override {
return static_cast<std::int32_t>(m_instr.range(15, 13));
}
inline void set_funct3(std::int32_t value) override {
m_instr.range(15, 13) = value;
}
/**
* @brief Access to immediate field for I-type
* @return immediate_I field
*/
inline std::int32_t get_imm_I() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(31, 20));
/* sign extension (optimize) */
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
inline void set_imm_I(std::int32_t value) {
m_instr.range(31, 20) = value;
}
/**
* @brief Access to immediate field for S-type
* @return immediate_S field
*/
inline std::int32_t get_imm_S() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(31, 25) << 5);
aux |= static_cast<std::int32_t>(m_instr.range(11, 7));
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
inline void set_imm_S(std::int32_t value) {
sc_dt::sc_uint<32> aux = value;
m_instr.range(31, 25) = aux.range(11, 5);
m_instr.range(11, 7) = aux.range(4, 0);
}
/**
* @brief Access to immediate field for U-type
* @return immediate_U field
*/
inline std::int32_t get_imm_U() const {
return static_cast<std::int32_t>(m_instr.range(31, 12));
}
inline void set_imm_U(std::int32_t value) {
m_instr.range(31, 12) = (value << 12);
}
/**
* @brief Access to immediate field for B-type
* @return immediate_B field
*/
inline std::int32_t get_imm_B() const {
std::int32_t aux = 0;
aux |= static_cast<std::int32_t>(m_instr[7] << 11);
aux |= static_cast<std::int32_t>(m_instr.range(30, 25) << 5);
aux |= static_cast<std::int32_t>(m_instr[31] << 12);
aux |= static_cast<std::int32_t>(m_instr.range(11, 8) << 1);
if (m_instr[31] == 1) {
aux |= (0b11111111111111111111) << 12;
}
return aux;
}
inline void set_imm_B(std::int32_t value) {
sc_dt::sc_uint<32> aux = value;
m_instr[31] = aux[12];
m_instr.range(30, 25) = aux.range(10, 5);
m_instr.range(11, 7) = aux.range(4, 1);
m_instr[6] = aux[11];
}
/**
* @brief Access to immediate field for J-type
* @return immediate_J field
*/
inline std::int32_t get_imm_J() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 11);
aux |= static_cast<std::int32_t>(m_instr[11] << 4);
aux |= static_cast<std::int32_t>(m_instr[10] << 9);
aux |= static_cast<std::int32_t>(m_instr[9] << 8);
aux |= static_cast<std::int32_t>(m_instr[8] << 10);
aux |= static_cast<std::int32_t>(m_instr[7] << 6);
aux |= static_cast<std::int32_t>(m_instr[6] << 7);
aux |= static_cast<std::int32_t>(m_instr.range(5, 3) << 1);
aux |= static_cast<std::int32_t>(m_instr[2] << 5);
if (m_instr[12] == 1) {
aux |= 0b11111111111111111111 << 12;
}
return aux;
}
inline void set_imm_J(std::int32_t value) {
sc_dt::sc_uint<32> aux = (value << 20);
m_instr[31] = aux[20];
m_instr.range(30, 21) = aux.range(10, 1);
m_instr[20] = aux[11];
m_instr.range(19, 12) = aux.range(19, 12);
}
inline std::int32_t get_imm_L() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(12, 10) << 3);
aux |= static_cast<std::int32_t>(m_instr[6] << 2);
aux |= static_cast<std::int32_t>(m_instr[5] << 6);
return aux;
}
inline std::int32_t get_imm_LWSP() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 5);
aux |= static_cast<std::int32_t>(m_instr.range(6, 4) << 2);
aux |= static_cast<std::int32_t>(m_instr.range(3, 2) << 6);
return aux;
}
inline std::int32_t get_imm_ADDI() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 5);
aux |= static_cast<std::int32_t>(m_instr.range(6, 2));
if (m_instr[12] == 1) {
aux |= 0b11111111111111111111111111 << 6;
}
return aux;
}
inline std::int32_t get_imm_ADDI4SPN() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(12, 11) << 4);
aux |= static_cast<std::int32_t>(m_instr.range(10, 7) << 6);
aux |= static_cast<std::int32_t>(m_instr[6] << 2);
aux |= static_cast<std::int32_t>(m_instr[5] << 3);
return aux;
}
inline std::int32_t get_imm_ADDI16SP() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 9);
aux |= static_cast<std::int32_t>(m_instr[6] << 4);
aux |= static_cast<std::int32_t>(m_instr[5] << 6);
aux |= static_cast<std::int32_t>(m_instr[4] << 8);
aux |= static_cast<std::int32_t>(m_instr[3] << 7);
aux |= static_cast<std::int32_t>(m_instr[2] << 5);
if (m_instr[12] == 1) {
aux |= 0b1111111111111111111111 << 10;
}
return aux;
}
inline std::int32_t get_imm_CSS() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr.range(12, 9) << 2);
aux |= static_cast<std::int32_t>(m_instr.range(8, 7) << 6);
return aux;
}
inline std::int32_t get_imm_CB() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 8);
aux |= static_cast<std::int32_t>(m_instr[11] << 4);
aux |= static_cast<std::int32_t>(m_instr[10] << 3);
aux |= static_cast<std::int32_t>(m_instr[6] << 7);
aux |= static_cast<std::int32_t>(m_instr[5] << 6);
aux |= static_cast<std::int32_t>(m_instr[4] << 2);
aux |= static_cast<std::int32_t>(m_instr[3] << 1);
aux |= static_cast<std::int32_t>(m_instr[2] << 5);
if (m_instr[12] == 1) {
aux |= 0b11111111111111111111111 << 9;
}
return aux;
}
inline std::int32_t get_imm_LUI() const {
std::int32_t aux = 0;
aux = static_cast<std::int32_t>(m_instr[12] << 17);
aux |= static_cast<std::int32_t>(m_instr.range(6, 2) << 12);
if (m_instr[12] == 1) {
aux |= 0b111111111111111 << 17;
}
return aux;
}
inline std::int32_t get_csr() const {
return get_imm_I();
}
/**
* @brief Decodes opcode of instruction
* @return opcode of instruction
*/
op_C_Codes decode() const;
bool Exec_C_JR();
bool Exec_C_MV();
bool Exec_C_LWSP();
bool Exec_C_ADDI4SPN();
bool Exec_C_SLLI();
bool Exec_C_ADDI16SP();
bool Exec_C_SWSP();
bool Exec_C_BEQZ();
bool Exec_C_BNEZ();
bool Exec_C_LI();
bool Exec_C_SRLI();
bool Exec_C_SRAI();
bool Exec_C_ANDI();
bool Exec_C_ADD();
bool Exec_C_SUB();
bool Exec_C_XOR();
bool Exec_C_OR();
bool Exec_C_AND();
bool Exec_C_ADDI() const;
bool Exec_C_JALR();
bool Exec_C_LW();
bool Exec_C_SW();
bool Exec_C_JAL(int m_rd);
bool Exec_C_EBREAK();
bool process_instruction(Instruction &inst, bool *breakpoint = nullptr);
};
}
#endif

84
inc/Instruction.h
View File

@ -12,54 +12,58 @@
#include "systemc"
#include "extension_base.h"
typedef enum {
BASE_EXTENSION,
M_EXTENSION,
A_EXTENSION,
F_EXTENSION,
D_EXTENSION,
Q_EXTENSION,
L_EXTENSION,
C_EXTENSION,
R_EXTENSION,
J_EXTENSION,
P_EXTENSION,
V_EXTENSION,
N_EXTENSION,
UNKNOWN_EXTENSION
} extension_t;
namespace riscv_tlm {
typedef enum {
BASE_EXTENSION,
M_EXTENSION,
A_EXTENSION,
F_EXTENSION,
D_EXTENSION,
Q_EXTENSION,
L_EXTENSION,
C_EXTENSION,
R_EXTENSION,
J_EXTENSION,
P_EXTENSION,
V_EXTENSION,
N_EXTENSION,
UNKNOWN_EXTENSION
} extension_t;
/**
* @brief Instruction decoding and fields access
*/
class Instruction {
public:
class Instruction {
public:
Instruction(std::uint32_t instr);
Instruction(std::uint32_t instr);
/**
* @brief returns what instruction extension
* @return extension
*/
extension_t check_extension() const;
/**
* @brief returns what instruction extension
* @return extension
*/
extension_t check_extension() const;
void setInstr(std::uint32_t p_instr) {
m_instr = p_instr;
}
/**
* @brief return instruction
* @return all instruction bits (31:0)
*/
std::uint32_t getInstr() {
return m_instr;
}
void setInstr(std::uint32_t p_instr) {
m_instr = p_instr;
}
inline void dump() {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
}
/**
* @brief return instruction
* @return all instruction bits (31:0)
*/
std::uint32_t getInstr() {
return m_instr;
}
private:
std::uint32_t m_instr;
};
inline void dump() {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
}
private:
std::uint32_t m_instr;
};
}
#endif

116
inc/M_extension.h
View File

@ -14,72 +14,82 @@
#include "extension_base.h"
#include "Registers.h"
typedef enum {
OP_M_MUL,
OP_M_MULH,
OP_M_MULHSU,
OP_M_MULHU,
OP_M_DIV,
OP_M_DIVU,
OP_M_REM,
OP_M_REMU,
namespace riscv_tlm {
OP_M_ERROR
} op_M_Codes;
typedef enum {
OP_M_MUL,
OP_M_MULH,
OP_M_MULHSU,
OP_M_MULHU,
OP_M_DIV,
OP_M_DIVU,
OP_M_REM,
OP_M_REMU,
typedef enum {
M_MUL = 0b000,
M_MULH = 0b001,
M_MULHSU = 0b010,
M_MULHU = 0b011,
M_DIV = 0b100,
M_DIVU = 0b101,
M_REM = 0b110,
M_REMU = 0b111,
} M_Codes;
OP_M_ERROR
} op_M_Codes;
typedef enum {
M_MUL = 0b000,
M_MULH = 0b001,
M_MULHSU = 0b010,
M_MULHU = 0b011,
M_DIV = 0b100,
M_DIVU = 0b101,
M_REM = 0b110,
M_REMU = 0b111,
} M_Codes;
/**
* @brief Instruction decoding and fields access
*/
class M_extension: public extension_base {
public:
class M_extension : public extension_base {
public:
/**
* @brief Constructor, same as base clase
*/
using extension_base::extension_base;
/**
* @brief Constructor, same as base clase
*/
using extension_base::extension_base;
/**
* @brief Decodes opcode of instruction
* @return opcode of instruction
*/
op_M_Codes decode() const;
/**
* @brief Decodes opcode of instruction
* @return opcode of instruction
*/
op_M_Codes decode() const;
inline void dump() const override {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
}
inline void dump() const override {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
}
bool Exec_M_MUL() const;
bool Exec_M_MULH() const;
bool Exec_M_MULHSU() const;
bool Exec_M_MULHU() const;
bool Exec_M_DIV() const;
bool Exec_M_DIVU() const;
bool Exec_M_REM() const;
bool Exec_M_REMU() const;
bool Exec_M_MUL() const;
bool process_instruction(Instruction &inst);
bool Exec_M_MULH() const;
private:
bool Exec_M_MULHSU() const;
/**
* @brief Access to opcode field
* @return return opcode field
*/
inline std::int32_t opcode() const override {
return static_cast<std::int32_t>(m_instr.range(14, 12));
}
bool Exec_M_MULHU() const;
};
bool Exec_M_DIV() const;
bool Exec_M_DIVU() const;
bool Exec_M_REM() const;
bool Exec_M_REMU() const;
bool process_instruction(Instruction &inst);
private:
/**
* @brief Access to opcode field
* @return return opcode field
*/
inline std::int32_t opcode() const override {
return static_cast<std::int32_t>(m_instr.range(14, 12));
}
};
}
#endif

108
inc/Memory.h
View File

@ -21,72 +21,76 @@
#include "spdlog/spdlog.h"
#include "spdlog/sinks/basic_file_sink.h"
namespace riscv_tlm {
/**
* @brief Basic TLM-2 memory
*/
class Memory: sc_core::sc_module {
public:
// TLM-2 socket, defaults to 32-bits wide, base protocol
tlm_utils::simple_target_socket<Memory> socket;
class Memory : sc_core::sc_module {
public:
// TLM-2 socket, defaults to 32-bits wide, base protocol
tlm_utils::simple_target_socket<Memory> socket;
/* 16 MBytes */
enum {
SIZE = 0x1000000
};
const sc_core::sc_time LATENCY;
/* 16 MBytes */
enum {
SIZE = 0x1000000
};
const sc_core::sc_time LATENCY;
Memory(sc_core::sc_module_name const &name, std::string const &filename);
explicit Memory(const sc_core::sc_module_name& name);
Memory(sc_core::sc_module_name const &name, std::string const &filename);
~Memory() override;
explicit Memory(const sc_core::sc_module_name &name);
/**
* @brief Returns Program Counter read from hexfile
* @return Initial PC
*/
virtual std::uint32_t getPCfromHEX();
~Memory() override;
// TLM-2 blocking transport method
virtual void b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
/**
* @brief Returns Program Counter read from hexfile
* @return Initial PC
*/
virtual std::uint32_t getPCfromHEX();
// *********************************************
// TLM-2 forward DMI method
// *********************************************
virtual bool get_direct_mem_ptr(tlm::tlm_generic_payload &trans,
tlm::tlm_dmi &dmi_data);
// TLM-2 blocking transport method
virtual void b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
// *********************************************
// TLM-2 debug transport method
// *********************************************
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans);
// *********************************************
// TLM-2 forward DMI method
// *********************************************
virtual bool get_direct_mem_ptr(tlm::tlm_generic_payload &trans,
tlm::tlm_dmi &dmi_data);
private:
// *********************************************
// TLM-2 debug transport method
// *********************************************
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans);
/**
* @brief Memory array in bytes
*/
std::array<uint8_t, Memory::SIZE> mem{};
private:
/**
* @brief Log class
*/
std::shared_ptr<spdlog::logger> logger;
/**
* @brief Memory array in bytes
*/
std::array<uint8_t, Memory::SIZE> mem{};
/**
* @brief Program counter (PC) read from hex file
*/
std::uint32_t program_counter;
/**
* @brief Log class
*/
std::shared_ptr<spdlog::logger> logger;
/**
* @brief DMI can be used?
*/
bool dmi_allowed;
/**
* @brief Program counter (PC) read from hex file
*/
std::uint32_t program_counter;
/**
* @brief Read Intel hex file
* @param filename file name to read
*/
void readHexFile(const std::string& filename);
};
/**
* @brief DMI can be used?
*/
bool dmi_allowed;
/**
* @brief Read Intel hex file
* @param filename file name to read
*/
void readHexFile(const std::string &filename);
};
}
#endif /* __MEMORY_H__ */

18
inc/MemoryInterface.h
View File

@ -17,17 +17,21 @@
#include "memory.h"
namespace riscv_tlm {
/**
* @brief Memory Interface
*/
class MemoryInterface {
public:
class MemoryInterface {
public:
tlm_utils::simple_initiator_socket<MemoryInterface> data_bus;
tlm_utils::simple_initiator_socket<MemoryInterface> data_bus;
MemoryInterface();
std::uint32_t readDataMem(std::uint32_t addr, int size);
void writeDataMem(std::uint32_t addr, std::uint32_t data, int size);
};
MemoryInterface();
std::uint32_t readDataMem(std::uint32_t addr, int size);
void writeDataMem(std::uint32_t addr, std::uint32_t data, int size);
};
}
#endif /* INC_MEMORYINTERFACE_H_ */

280
inc/Registers.h
View File

@ -19,6 +19,8 @@
#include "Performance.h"
#include "Memory.h"
namespace riscv_tlm {
#define MISA_A_EXTENSION (1 << 0)
#define MISA_B_EXTENSION (1 << 1)
#define MISA_C_EXTENSION (1 << 2)
@ -76,7 +78,7 @@
#define MSTATUS_SPP (1 << 8)
#define MSTATUS_MPP (1 << 11)
#define MSTATUS_FS (1 << 13)
#define MSTATUS_XS (1 << 15)
#define MSTATUS_XS (1 << 15)
#define MSTATUS_MPRV (1 << 17)
#define MSTATUS_SUM (1 << 18)
#define MSTATUS_MXR (1 << 19)
@ -110,156 +112,158 @@
/**
* @brief Register file implementation
*/
class Registers {
public:
class Registers {
public:
enum {
x0 = 0,
x1 = 1,
x2,
x3,
x4,
x5,
x6,
x7,
x8,
x9,
x10,
x11,
x12,
x13,
x14,
x15,
x16,
x17,
x18,
x19,
x20,
x21,
x22,
x23,
x24,
x25,
x26,
x27,
x28,
x29,
x30,
x31,
zero = x0,
ra = x1,
sp = x2,
gp = x3,
tp = x4,
t0 = x5,
t1 = x6,
t2 = x7,
s0 = x8,
fp = x8,
s1 = x9,
a0 = x10,
a1 = x11,
a2 = x12,
a3 = x13,
a4 = x14,
a5 = x15,
a6 = x16,
a7 = x17,
s2 = x18,
s3 = x19,
s4 = x20,
s5 = x21,
s6 = x22,
s7 = x23,
s8 = x24,
s9 = x25,
s10 = x26,
s11 = x27,
t3 = x28,
t4 = x29,
t5 = x30,
t6 = x31
};
/**
* Default constructor
*/
Registers();
enum {
x0 = 0,
x1 = 1,
x2,
x3,
x4,
x5,
x6,
x7,
x8,
x9,
x10,
x11,
x12,
x13,
x14,
x15,
x16,
x17,
x18,
x19,
x20,
x21,
x22,
x23,
x24,
x25,
x26,
x27,
x28,
x29,
x30,
x31,
zero = x0,
ra = x1,
sp = x2,
gp = x3,
tp = x4,
t0 = x5,
t1 = x6,
t2 = x7,
s0 = x8,
fp = x8,
s1 = x9,
a0 = x10,
a1 = x11,
a2 = x12,
a3 = x13,
a4 = x14,
a5 = x15,
a6 = x16,
a7 = x17,
s2 = x18,
s3 = x19,
s4 = x20,
s5 = x21,
s6 = x22,
s7 = x23,
s8 = x24,
s9 = x25,
s10 = x26,
s11 = x27,
t3 = x28,
t4 = x29,
t5 = x30,
t6 = x31
};
/**
* Set value for a register
* @param reg_num register number
* @param value register value
*/
void setValue(int reg_num, std::int32_t value);
/**
* Default constructor
*/
Registers();
/**
* Returns register value
* @param reg_num register number
* @return register value
*/
std::uint32_t getValue(int reg_num) const;
/**
* Set value for a register
* @param reg_num register number
* @param value register value
*/
void setValue(int reg_num, std::int32_t value);
/**
* Returns PC value
* @return PC value
*/
std::uint32_t getPC() const;
/**
* Returns register value
* @param reg_num register number
* @return register value
*/
std::uint32_t getValue(int reg_num) const;
/**
* Sets arbitraty value to PC
* @param new_pc new address to PC
*/
void setPC(std::uint32_t new_pc);
/**
* Returns PC value
* @return PC value
*/
std::uint32_t getPC() const;
/**
* Increments PC couunter to next address
*/
inline void incPC() {
register_PC += 4;
}
/**
* Sets arbitraty value to PC
* @param new_pc new address to PC
*/
void setPC(std::uint32_t new_pc);
inline void incPCby2() {
register_PC += 2;
}
/**
* Increments PC couunter to next address
*/
inline void incPC() {
register_PC += 4;
}
/**
* @brief Get CSR value
* @param csr CSR number to access
* @return CSR value
*/
std::uint32_t getCSR(int csr);
inline void incPCby2() {
register_PC += 2;
}
/**
* @brief Set CSR value
* @param csr CSR number to access
* @param value new value to register
*/
void setCSR(int csr, std::uint32_t value);
/**
* @brief Get CSR value
* @param csr CSR number to access
* @return CSR value
*/
std::uint32_t getCSR(int csr);
/**
* Dump register data to console
*/
void dump();
private:
/**
* bank of registers (32 regs of 32bits each)
*/
std::array<std::uint32_t, 32> register_bank = { {0} };
/**
* @brief Set CSR value
* @param csr CSR number to access
* @param value new value to register
*/
void setCSR(int csr, std::uint32_t value);
/**
* Program counter (32 bits width)
*/
std::uint32_t register_PC;
/**
* Dump register data to console
*/
void dump();
/**
* CSR registers (4096 maximum)
*/
std::unordered_map<std::uint32_t, unsigned int> CSR;
private:
/**
* bank of registers (32 regs of 32bits each)
*/
std::array<std::uint32_t, 32> register_bank = {{0}};
/**
* Program counter (32 bits width)
*/
std::uint32_t register_PC;
/**
* CSR registers (4096 maximum)
*/
std::unordered_map<std::uint32_t, unsigned int> CSR;
Performance *perf;
void initCSR();
};
Performance *perf;
void initCSR();
};
}
#endif

71
inc/Timer.h
View File

@ -21,50 +21,51 @@
#include "BusCtrl.h"
namespace riscv_tlm::peripherals {
/**
* @brief Simple timer peripheral
*
* It runs a 1 ns (nanoseconds) pace
*
*/
class Timer: sc_core::sc_module {
public:
// TLM-2 socket, defaults to 32-bits wide, base protocol
tlm_utils::simple_target_socket<Timer> socket;
class Timer : sc_core::sc_module {
public:
// TLM-2 socket, defaults to 32-bits wide, base protocol
tlm_utils::simple_target_socket<Timer> socket;
tlm_utils::simple_initiator_socket<Timer> irq_line;
tlm_utils::simple_initiator_socket<Timer> irq_line;
/**
*
* @brief Constructor
* @param name module name
*/
explicit Timer(sc_core::sc_module_name const &name);
/**
*
* @brief Constructor
* @param name module name
*/
explicit Timer(sc_core::sc_module_name const &name);
/**
* @brief Waits for event timer_event and triggers an IRQ
*
* Waits for event timer_event and triggers an IRQ (if it is not already
* triggered).
* After that, it posts the timer_event to 20 ns in the future to clear the IRQ
* line.
*
*/
[[noreturn]] void run();
/**
* @brief Waits for event timer_event and triggers an IRQ
*
* Waits for event timer_event and triggers an IRQ (if it is not already
* triggered).
* After that, it posts the timer_event to 20 ns in the future to clear the IRQ
* line.
*
*/
[[noreturn]] void run();
/**
*
* @brief TLM-2.0 socket implementation
* @param trans TLM-2.0 transaction
* @param delay transaction delay time
*/
virtual void b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
private:
sc_dt::sc_uint<64> m_mtime; /**< mtime register */
sc_dt::sc_uint<64> m_mtimecmp; /**< mtimecmp register */
sc_core::sc_event timer_event; /**< event */
};
/**
*
* @brief TLM-2.0 socket implementation
* @param trans TLM-2.0 transaction
* @param delay transaction delay time
*/
virtual void b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
private:
sc_dt::sc_uint<64> m_mtime; /**< mtime register */
sc_dt::sc_uint<64> m_mtimecmp; /**< mtimecmp register */
sc_core::sc_event timer_event; /**< event */
};
}
#endif

55
inc/Trace.h
View File

@ -19,43 +19,46 @@
#include "tlm.h"
#include "tlm_utils/simple_target_socket.h"
namespace riscv_tlm::peripherals {
/**
* @brief Simple trace peripheral
*
* This peripheral outputs to cout any character written to its unique register
*/
class Trace: sc_core::sc_module {
public:
class Trace : sc_core::sc_module {
public:
/**
* @brief Bus socket
*/
tlm_utils::simple_target_socket<Trace> socket;
/**
* @brief Bus socket
*/
tlm_utils::simple_target_socket<Trace> socket;
/**
* @brief Constructor
* @param name Module name
*/
explicit Trace(sc_core::sc_module_name const &name);
/**
* @brief Constructor
* @param name Module name
*/
explicit Trace(sc_core::sc_module_name const &name);
/**
* @brief Destructor
*/
~Trace() override;
/**
* @brief Destructor
*/
~Trace() override;
private:
private:
// TLM-2 blocking transport method
virtual void b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
// TLM-2 blocking transport method
virtual void b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay);
void xtermLaunch(char *slaveName) const;
void xtermKill();
void xtermSetup();
void xtermLaunch(char *slaveName) const;
int ptSlave{};
int ptMaster{};
int xtermPid{};
};
void xtermKill();
void xtermSetup();
int ptSlave{};
int ptMaster{};
int xtermPid{};
};
}
#endif

90
inc/extension_base.h
View File

@ -26,60 +26,66 @@
#define EXCEPTION_CAUSE_LOAD_ADDR_MISALIGN 4
#define EXCEPTION_CAUSE_LOAD_ACCESS_FAULT 5
class extension_base {
namespace riscv_tlm {
public:
extension_base(const sc_dt::sc_uint<32> & instr, Registers *register_bank,
MemoryInterface *mem_interface);
virtual ~extension_base() = 0;
class extension_base {
void setInstr(std::uint32_t p_instr);
void RaiseException(std::uint32_t cause, std::uint32_t inst);
bool NOP();
public:
extension_base(const sc_dt::sc_uint<32> &instr, Registers *register_bank,
MemoryInterface *mem_interface);
/* pure virtual functions */
virtual std::int32_t opcode() const = 0;
virtual ~extension_base() = 0;
virtual std::int32_t get_rd() const {
return m_instr.range(11, 7);
}
void setInstr(std::uint32_t p_instr);
virtual void set_rd(std::int32_t value) {
m_instr.range(11, 7) = value;
}
void RaiseException(std::uint32_t cause, std::uint32_t inst);
virtual std::int32_t get_rs1() const {
return m_instr.range(19, 15);
}
bool NOP();
virtual void set_rs1(std::int32_t value) {
m_instr.range(19, 15) = value;
}
/* pure virtual functions */
virtual std::int32_t opcode() const = 0;
virtual std::int32_t get_rs2() const {
return m_instr.range(24, 20);
}
virtual std::int32_t get_rd() const {
return m_instr.range(11, 7);
}
virtual void set_rs2(std::int32_t value) {
m_instr.range(24, 20) = value;
}
virtual void set_rd(std::int32_t value) {
m_instr.range(11, 7) = value;
}
virtual std::int32_t get_funct3() const {
return m_instr.range(14, 12);
}
virtual std::int32_t get_rs1() const {
return m_instr.range(19, 15);
}
virtual void set_funct3(std::int32_t value) {
m_instr.range(14, 12) = value;
}
virtual void set_rs1(std::int32_t value) {
m_instr.range(19, 15) = value;
}
virtual void dump() const;
virtual std::int32_t get_rs2() const {
return m_instr.range(24, 20);
}
protected:
sc_dt::sc_uint<32> m_instr;
Registers *regs;
Performance *perf;
MemoryInterface *mem_intf;
std::shared_ptr<spdlog::logger> logger;
};
virtual void set_rs2(std::int32_t value) {
m_instr.range(24, 20) = value;
}
virtual std::int32_t get_funct3() const {
return m_instr.range(14, 12);
}
virtual void set_funct3(std::int32_t value) {
m_instr.range(14, 12) = value;
}
virtual void dump() const;
protected:
sc_dt::sc_uint<32> m_instr;
Registers *regs;
Performance *perf;
MemoryInterface *mem_intf;
std::shared_ptr<spdlog::logger> logger;
};
}
#endif /* INC_EXTENSION_BASE_H_ */

853
src/A_extension.cpp
View File

@ -8,429 +8,438 @@
#include "A_extension.h"
op_A_Codes A_extension::decode() const {
namespace riscv_tlm {
switch (opcode()) {
case A_LR:
return OP_A_LR;
break;
case A_SC:
return OP_A_SC;
break;
case A_AMOSWAP:
return OP_A_AMOSWAP;
break;
case A_AMOADD:
return OP_A_AMOADD;
break;
case A_AMOXOR:
return OP_A_AMOXOR;
break;
case A_AMOAND:
return OP_A_AMOAND;
break;
case A_AMOOR:
return OP_A_AMOOR;
break;
case A_AMOMIN:
return OP_A_AMOMIN;
break;
case A_AMOMAX:
return OP_A_AMOMAX;
break;
case A_AMOMINU:
return OP_A_AMOMINU;
break;
case A_AMOMAXU:
return OP_A_AMOMAXU;
break;
[[unlikely]] default:
return OP_A_ERROR;
break;
op_A_Codes A_extension::decode() const {
}
switch (opcode()) {
case A_LR:
return OP_A_LR;
break;
case A_SC:
return OP_A_SC;
break;
case A_AMOSWAP:
return OP_A_AMOSWAP;
break;
case A_AMOADD:
return OP_A_AMOADD;
break;
case A_AMOXOR:
return OP_A_AMOXOR;
break;
case A_AMOAND:
return OP_A_AMOAND;
break;
case A_AMOOR:
return OP_A_AMOOR;
break;
case A_AMOMIN:
return OP_A_AMOMIN;
break;
case A_AMOMAX:
return OP_A_AMOMAX;
break;
case A_AMOMINU:
return OP_A_AMOMINU;
break;
case A_AMOMAXU:
return OP_A_AMOMAXU;
break;
[[unlikely]] default:
return OP_A_ERROR;
break;
return OP_A_ERROR;
}
bool A_extension::Exec_A_LR() {
std::uint32_t mem_addr = 0;
int rd, rs1, rs2;
std::uint32_t data;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
if (rs2 != 0) {
std::cout << "ILEGAL INSTRUCTION, LR.W: rs2 != 0" << std::endl;
RaiseException(EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION, m_instr);
return false;
}
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
TLB_reserve(mem_addr);
logger->debug("{} ns. PC: 0x{:x}. A.LR.W: x{:d}(0x{:x}) -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, mem_addr, rd, data);
return true;
}
bool A_extension::Exec_A_SC() {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = regs->getValue(rs2);
if (TLB_reserved(mem_addr)) {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
regs->setValue(rd, 0); // SC writes 0 to rd on success
} else {
regs->setValue(rd, 1); // SC writes nonzero on failure
}
logger->debug("{} ns. PC: 0x{:x}. A.SC.W: (0x{:x}) <- x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(), regs->getPC(),
mem_addr, rs2, data);
return true;
}
bool A_extension::Exec_A_AMOSWAP() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// swap
aux = regs->getValue(rs2);
regs->setValue(rs2, static_cast<int32_t>(data));
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOSWAP");
return true;
}
bool A_extension::Exec_A_AMOADD() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// add
data = data + regs->getValue(rs2);
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOADD");
return true;
}
bool A_extension::Exec_A_AMOXOR() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// add
data = data ^ regs->getValue(rs2);
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOXOR");
return true;
}
bool A_extension::Exec_A_AMOAND() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// add
data = data & regs->getValue(rs2);
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOAND");
return true;
}
bool A_extension::Exec_A_AMOOR() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// add
data = data | regs->getValue(rs2);
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOOR");
return true;
}
bool A_extension::Exec_A_AMOMIN() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// min
aux = regs->getValue(rs2);
if ((int32_t) data < (int32_t) aux) {
aux = data;
}
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOMIN");
return true;
}
bool A_extension::Exec_A_AMOMAX() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// >
aux = regs->getValue(rs2);
if ((int32_t) data > (int32_t) aux) {
aux = data;
}
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOMAX");
return true;
}
bool A_extension::Exec_A_AMOMINU() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// min
aux = regs->getValue(rs2);
if (data < aux) {
aux = data;
}
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOMINU");
return true;
}
bool A_extension::Exec_A_AMOMAXU() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// max
aux = regs->getValue(rs2);
if (data > aux) {
aux = data;
}
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOMAXU");
return true;
}
void A_extension::TLB_reserve(std::uint32_t address) {
TLB_A_Entries.insert(address);
}
bool A_extension::TLB_reserved(std::uint32_t address) {
if (TLB_A_Entries.count(address) == 1) {
TLB_A_Entries.erase(address);
return true;
} else {
return false;
}
}
bool A_extension::process_instruction(Instruction &inst) {
bool PC_not_affected = true;
setInstr(inst.getInstr());
switch (decode()) {
case OP_A_LR:
Exec_A_LR();
break;
case OP_A_SC:
Exec_A_SC();
break;
case OP_A_AMOSWAP:
Exec_A_AMOSWAP();
break;
case OP_A_AMOADD:
Exec_A_AMOADD();
break;
case OP_A_AMOXOR:
Exec_A_AMOXOR();
break;
case OP_A_AMOAND:
Exec_A_AMOAND();
break;
case OP_A_AMOOR:
Exec_A_AMOOR();
break;
case OP_A_AMOMIN:
Exec_A_AMOMIN();
break;
case OP_A_AMOMAX:
Exec_A_AMOMAX();
break;
case OP_A_AMOMINU:
Exec_A_AMOMINU();
break;
case OP_A_AMOMAXU:
Exec_A_AMOMAXU();
break;
[[unlikely]] default:
std::cout << "A instruction not implemented yet" << std::endl;
inst.dump();
NOP();
break;
}
return PC_not_affected;
}
return OP_A_ERROR;
}
bool A_extension::Exec_A_LR() {
std::uint32_t mem_addr = 0;
int rd, rs1, rs2;
std::uint32_t data;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
if (rs2 != 0) {
std::cout << "ILEGAL INSTRUCTION, LR.W: rs2 != 0" << std::endl;
RaiseException(EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION, m_instr);
return false;
}
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
TLB_reserve(mem_addr);
logger->debug("{} ns. PC: 0x{:x}. A.LR.W: x{:d}(0x{:x}) -> x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, mem_addr, rd, data);
return true;
}
bool A_extension::Exec_A_SC() {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = regs->getValue(rs2);
if (TLB_reserved(mem_addr)) {
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
regs->setValue(rd, 0); // SC writes 0 to rd on success
} else {
regs->setValue(rd, 1); // SC writes nonzero on failure
}
logger->debug("{} ns. PC: 0x{:x}. A.SC.W: (0x{:x}) <- x{:d}(0x{:x}) ", sc_core::sc_time_stamp().value(),
regs->getPC(),
mem_addr, rs2, data);
return true;
}
bool A_extension::Exec_A_AMOSWAP() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// swap
aux = regs->getValue(rs2);
regs->setValue(rs2, static_cast<int32_t>(data));
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOSWAP");
return true;
}
bool A_extension::Exec_A_AMOADD() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// add
data = data + regs->getValue(rs2);
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOADD");
return true;
}
bool A_extension::Exec_A_AMOXOR() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// add
data = data ^ regs->getValue(rs2);
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOXOR");
return true;
}
bool A_extension::Exec_A_AMOAND() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// add
data = data & regs->getValue(rs2);
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOAND");
return true;
}
bool A_extension::Exec_A_AMOOR() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// add
data = data | regs->getValue(rs2);
mem_intf->writeDataMem(mem_addr, data, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOOR");
return true;
}
bool A_extension::Exec_A_AMOMIN() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// min
aux = regs->getValue(rs2);
if ((int32_t) data < (int32_t) aux) {
aux = data;
}
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOMIN");
return true;
}
bool A_extension::Exec_A_AMOMAX() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// >
aux = regs->getValue(rs2);
if ((int32_t) data > (int32_t) aux) {
aux = data;
}
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOMAX");
return true;
}
bool A_extension::Exec_A_AMOMINU() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// min
aux = regs->getValue(rs2);
if (data < aux) {
aux = data;
}
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOMINU");
return true;
}
bool A_extension::Exec_A_AMOMAXU() const {
std::uint32_t mem_addr;
int rd, rs1, rs2;
std::uint32_t data;
std::uint32_t aux;
/* These instructions must be atomic */
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
mem_addr = regs->getValue(rs1);
data = mem_intf->readDataMem(mem_addr, 4);
perf->dataMemoryRead();
regs->setValue(rd, static_cast<int32_t>(data));
// max
aux = regs->getValue(rs2);
if (data > aux) {
aux = data;
}
mem_intf->writeDataMem(mem_addr, aux, 4);
perf->dataMemoryWrite();
logger->debug("{} ns. PC: 0x{:x}. A.AMOMAXU");
return true;
}
void A_extension::TLB_reserve(std::uint32_t address) {
TLB_A_Entries.insert(address);
}
bool A_extension::TLB_reserved(std::uint32_t address) {
if (TLB_A_Entries.count(address) == 1) {
TLB_A_Entries.erase(address);
return true;
} else {
return false;
}
}
bool A_extension::process_instruction(Instruction &inst) {
bool PC_not_affected = true;
setInstr(inst.getInstr());
switch (decode()) {
case OP_A_LR:
Exec_A_LR();
break;
case OP_A_SC:
Exec_A_SC();
break;
case OP_A_AMOSWAP:
Exec_A_AMOSWAP();
break;
case OP_A_AMOADD:
Exec_A_AMOADD();
break;
case OP_A_AMOXOR:
Exec_A_AMOXOR();
break;
case OP_A_AMOAND:
Exec_A_AMOAND();
break;
case OP_A_AMOOR:
Exec_A_AMOOR();
break;
case OP_A_AMOMIN:
Exec_A_AMOMIN();
break;
case OP_A_AMOMAX:
Exec_A_AMOMAX();
break;
case OP_A_AMOMINU:
Exec_A_AMOMINU();
break;
case OP_A_AMOMAXU:
Exec_A_AMOMAXU();
break;
[[unlikely]] default:
std::cout << "A instruction not implemented yet" << std::endl;
inst.dump();
NOP();
break;
}
return PC_not_affected;
}
}

2441
src/BASE_ISA.cpp
View File

File diff suppressed because it is too large Load Diff

101
src/BusCtrl.cpp
View File

@ -8,64 +8,67 @@
#include "BusCtrl.h"
SC_HAS_PROCESS(BusCtrl);
BusCtrl::BusCtrl(sc_core::sc_module_name const &name) :
sc_module(name), cpu_instr_socket("cpu_instr_socket"), cpu_data_socket(
"cpu_data_socket"), memory_socket("memory_socket"), trace_socket(
"trace_socket") {
cpu_instr_socket.register_b_transport(this, &BusCtrl::b_transport);
cpu_data_socket.register_b_transport(this, &BusCtrl::b_transport);
namespace riscv_tlm {
cpu_instr_socket.register_get_direct_mem_ptr(this,
&BusCtrl::instr_direct_mem_ptr);
memory_socket.register_invalidate_direct_mem_ptr(this,
&BusCtrl::invalidate_direct_mem_ptr);
}
SC_HAS_PROCESS(BusCtrl);
void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
BusCtrl::BusCtrl(sc_core::sc_module_name const &name) :
sc_module(name), cpu_instr_socket("cpu_instr_socket"), cpu_data_socket(
"cpu_data_socket"), memory_socket("memory_socket"), trace_socket(
"trace_socket") {
cpu_instr_socket.register_b_transport(this, &BusCtrl::b_transport);
cpu_data_socket.register_b_transport(this, &BusCtrl::b_transport);
sc_dt::uint64 adr = trans.get_address() / 4;
cpu_instr_socket.register_get_direct_mem_ptr(this,
&BusCtrl::instr_direct_mem_ptr);
memory_socket.register_invalidate_direct_mem_ptr(this,
&BusCtrl::invalidate_direct_mem_ptr);
}
if (adr >= TO_HOST_ADDRESS / 4) {
std::cout << "To host\n" << std::flush;
sc_core::sc_stop();
return;
}
void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
switch (adr) {
case TIMER_MEMORY_ADDRESS_HI / 4:
case TIMER_MEMORY_ADDRESS_LO / 4:
case TIMERCMP_MEMORY_ADDRESS_HI / 4:
case TIMERCMP_MEMORY_ADDRESS_LO / 4:
timer_socket->b_transport(trans, delay);
break;
case TRACE_MEMORY_ADDRESS / 4:
trace_socket->b_transport(trans, delay);
break;
[[likely]] default:
memory_socket->b_transport(trans, delay);
break;
}
sc_dt::uint64 adr = trans.get_address() / 4;
if (adr >= TO_HOST_ADDRESS / 4) {
std::cout << "To host\n" << std::flush;
sc_core::sc_stop();
return;
}
switch (adr) {
case TIMER_MEMORY_ADDRESS_HI / 4:
case TIMER_MEMORY_ADDRESS_LO / 4:
case TIMERCMP_MEMORY_ADDRESS_HI / 4:
case TIMERCMP_MEMORY_ADDRESS_LO / 4:
timer_socket->b_transport(trans, delay);
break;
case TRACE_MEMORY_ADDRESS / 4:
trace_socket->b_transport(trans, delay);
break;
[[likely]] default:
memory_socket->b_transport(trans, delay);
break;
}
#if 0
if (cmd == tlm::TLM_READ_COMMAND) {
log->SC_log(Log::DEBUG) << "RD Address: @0x" << hex << adr << dec << endl;
} else {
log->SC_log(Log::DEBUG) << "WR Address: @0x" << hex << adr << dec << endl;
}
if (cmd == tlm::TLM_READ_COMMAND) {
log->SC_log(Log::DEBUG) << "RD Address: @0x" << hex << adr << dec << endl;
} else {
log->SC_log(Log::DEBUG) << "WR Address: @0x" << hex << adr << dec << endl;
}
#endif
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
bool BusCtrl::instr_direct_mem_ptr(tlm::tlm_generic_payload &gp,
tlm::tlm_dmi &dmi_data) {
return memory_socket->get_direct_mem_ptr(gp, dmi_data);
}
bool BusCtrl::instr_direct_mem_ptr(tlm::tlm_generic_payload &gp,
tlm::tlm_dmi &dmi_data) {
return memory_socket->get_direct_mem_ptr(gp, dmi_data);
}
void BusCtrl::invalidate_direct_mem_ptr(sc_dt::uint64 start,
sc_dt::uint64 end) {
cpu_instr_socket->invalidate_direct_mem_ptr(start, end);
void BusCtrl::invalidate_direct_mem_ptr(sc_dt::uint64 start,
sc_dt::uint64 end) {
cpu_instr_socket->invalidate_direct_mem_ptr(start, end);
}
}

384
src/CPU.cpp
View File

@ -7,222 +7,230 @@
// SPDX-License-Identifier: GPL-3.0-or-later
#include "CPU.h"
SC_HAS_PROCESS(CPU);
CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
sc_module(name), instr_bus("instr_bus"), inst(0), default_time(10,
sc_core::SC_NS), INSTR(0) {
register_bank = new Registers();
mem_intf = new MemoryInterface();
namespace riscv_tlm {
perf = Performance::getInstance();
SC_HAS_PROCESS(CPU);
register_bank->setPC(PC);
register_bank->setValue(Registers::sp, (Memory::SIZE / 4) - 1);
CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
sc_module(name), instr_bus("instr_bus"), inst(0), default_time(10,
sc_core::SC_NS), INSTR(0) {
register_bank = new Registers();
mem_intf = new MemoryInterface();
irq_line_socket.register_b_transport(this, &CPU::call_interrupt);
interrupt = false;
perf = Performance::getInstance();
int_cause = 0;
irq_already_down = false;
register_bank->setPC(PC);
register_bank->setValue(Registers::sp, (Memory::SIZE / 4) - 1);
dmi_ptr_valid = false;
instr_bus.register_invalidate_direct_mem_ptr(this,
&CPU::invalidate_direct_mem_ptr);
irq_line_socket.register_b_transport(this, &CPU::call_interrupt);
interrupt = false;
exec = new BASE_ISA(0, register_bank, mem_intf);
c_inst = new C_extension(0, register_bank, mem_intf);
m_inst = new M_extension(0, register_bank, mem_intf);
a_inst = new A_extension(0, register_bank, mem_intf);
int_cause = 0;
irq_already_down = false;
m_qk = new tlm_utils::tlm_quantumkeeper();
m_qk->reset();
dmi_ptr_valid = false;
instr_bus.register_invalidate_direct_mem_ptr(this,
&CPU::invalidate_direct_mem_ptr);
trans.set_command(tlm::TLM_READ_COMMAND);
trans.set_data_ptr(reinterpret_cast<unsigned char*>(&INSTR));
trans.set_data_length(4);
trans.set_streaming_width(4); // = data_length to indicate no streaming
trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
trans.set_dmi_allowed(false); // Mandatory initial value
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
exec = new BASE_ISA(0, register_bank, mem_intf);
c_inst = new C_extension(0, register_bank, mem_intf);
m_inst = new M_extension(0, register_bank, mem_intf);
a_inst = new A_extension(0, register_bank, mem_intf);
if (!debug) {
SC_THREAD(CPU_thread);
}
m_qk = new tlm_utils::tlm_quantumkeeper();
m_qk->reset();
logger = spdlog::get("my_logger");
}
trans.set_command(tlm::TLM_READ_COMMAND);
trans.set_data_ptr(reinterpret_cast<unsigned char *>(&INSTR));
trans.set_data_length(4);
trans.set_streaming_width(4); // = data_length to indicate no streaming
trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
trans.set_dmi_allowed(false); // Mandatory initial value
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
CPU::~CPU() {
delete register_bank;
delete mem_intf;
delete exec;
delete c_inst;
delete m_inst;
delete a_inst;
delete m_qk;
}
bool CPU::cpu_process_IRQ() {
std::uint32_t csr_temp;
bool ret_value = false;
if (interrupt) {
csr_temp = register_bank->getCSR(CSR_MSTATUS);
if ((csr_temp & MSTATUS_MIE) == 0) {
logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(), register_bank->getPC());
return ret_value;
}
csr_temp = register_bank->getCSR(CSR_MIP);
if ((csr_temp & MIP_MEIP) == 0) {
csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
register_bank->setCSR(CSR_MIP, csr_temp);
logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(), register_bank->getPC());
/* updated MEPC register */
std::uint32_t old_pc = register_bank->getPC();
register_bank->setCSR(CSR_MEPC, old_pc);
logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(), register_bank->getPC(),
old_pc);
/* update MCAUSE register */
register_bank->setCSR(CSR_MCAUSE, 0x80000000);
/* set new PC address */
std::uint32_t new_pc = register_bank->getCSR(CSR_MTVEC);
//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(), register_bank->getPC(),
new_pc);
register_bank->setPC(new_pc);
ret_value = true;
interrupt = false;
irq_already_down = false;
}
} else {
if (!irq_already_down) {
csr_temp = register_bank->getCSR(CSR_MIP);
csr_temp &= ~MIP_MEIP;
register_bank->setCSR(CSR_MIP, csr_temp);
irq_already_down = true;
}
}
return ret_value;
}
bool CPU::CPU_step() {
bool PC_not_affected = false;
/* Get new PC value */
if (dmi_ptr_valid) {
/* if memory_offset at Memory module is set, this won't work */
std::memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
} else {
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
tlm::tlm_dmi dmi_data;
trans.set_address(register_bank->getPC());
instr_bus->b_transport(trans, delay);
if (trans.is_response_error()) {
SC_REPORT_ERROR("CPU base", "Read memory");
}
if (trans.is_dmi_allowed()) {
dmi_ptr_valid = instr_bus->get_direct_mem_ptr(trans, dmi_data);
if (dmi_ptr_valid) {
std::cout << "Get DMI_PTR " << std::endl;
dmi_ptr = dmi_data.get_dmi_ptr();
}
}
}
perf->codeMemoryRead();
inst.setInstr(INSTR);
bool breakpoint = false;
/* check what type of instruction is and execute it */
switch (inst.check_extension()) {
[[likely]] case BASE_EXTENSION:
PC_not_affected = exec->process_instruction(inst, &breakpoint);
if (PC_not_affected) {
register_bank->incPC();
if (!debug) {
SC_THREAD(CPU_thread);
}
break;
case C_EXTENSION:
PC_not_affected = c_inst->process_instruction(inst, &breakpoint);
if (PC_not_affected) {
register_bank->incPCby2();
logger = spdlog::get("my_logger");
}
CPU::~CPU() {
delete register_bank;
delete mem_intf;
delete exec;
delete c_inst;
delete m_inst;
delete a_inst;
delete m_qk;
}
bool CPU::cpu_process_IRQ() {
std::uint32_t csr_temp;
bool ret_value = false;
if (interrupt) {
csr_temp = register_bank->getCSR(CSR_MSTATUS);
if ((csr_temp & MSTATUS_MIE) == 0) {
logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(),
register_bank->getPC());
return ret_value;
}
csr_temp = register_bank->getCSR(CSR_MIP);
if ((csr_temp & MIP_MEIP) == 0) {
csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
register_bank->setCSR(CSR_MIP, csr_temp);
logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(),
register_bank->getPC());
/* updated MEPC register */
std::uint32_t old_pc = register_bank->getPC();
register_bank->setCSR(CSR_MEPC, old_pc);
logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
register_bank->getPC(),
old_pc);
/* update MCAUSE register */
register_bank->setCSR(CSR_MCAUSE, 0x80000000);
/* set new PC address */
std::uint32_t new_pc = register_bank->getCSR(CSR_MTVEC);
//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
register_bank->getPC(),
new_pc);
register_bank->setPC(new_pc);
ret_value = true;
interrupt = false;
irq_already_down = false;
}
} else {
if (!irq_already_down) {
csr_temp = register_bank->getCSR(CSR_MIP);
csr_temp &= ~MIP_MEIP;
register_bank->setCSR(CSR_MIP, csr_temp);
irq_already_down = true;
}
}
break;
case M_EXTENSION:
PC_not_affected = m_inst->process_instruction(inst);
if (PC_not_affected) {
register_bank->incPC();
return ret_value;
}
bool CPU::CPU_step() {
bool PC_not_affected = false;
/* Get new PC value */
if (dmi_ptr_valid) {
/* if memory_offset at Memory module is set, this won't work */
std::memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
} else {
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
tlm::tlm_dmi dmi_data;
trans.set_address(register_bank->getPC());
instr_bus->b_transport(trans, delay);
if (trans.is_response_error()) {
SC_REPORT_ERROR("CPU base", "Read memory");
}
if (trans.is_dmi_allowed()) {
dmi_ptr_valid = instr_bus->get_direct_mem_ptr(trans, dmi_data);
if (dmi_ptr_valid) {
std::cout << "Get DMI_PTR " << std::endl;
dmi_ptr = dmi_data.get_dmi_ptr();
}
}
}
break;
case A_EXTENSION:
PC_not_affected = a_inst->process_instruction(inst);
if (PC_not_affected) {
register_bank->incPC();
perf->codeMemoryRead();
inst.setInstr(INSTR);
bool breakpoint = false;
/* check what type of instruction is and execute it */
switch (inst.check_extension()) {
[[likely]] case BASE_EXTENSION:
PC_not_affected = exec->process_instruction(inst, &breakpoint);
if (PC_not_affected) {
register_bank->incPC();
}
break;
case C_EXTENSION:
PC_not_affected = c_inst->process_instruction(inst, &breakpoint);
if (PC_not_affected) {
register_bank->incPCby2();
}
break;
case M_EXTENSION:
PC_not_affected = m_inst->process_instruction(inst);
if (PC_not_affected) {
register_bank->incPC();
}
break;
case A_EXTENSION:
PC_not_affected = a_inst->process_instruction(inst);
if (PC_not_affected) {
register_bank->incPC();
}
break;
[[unlikely]] default:
std::cout << "Extension not implemented yet" << std::endl;
inst.dump();
exec->NOP();
}
break;
[[unlikely]] default:
std::cout << "Extension not implemented yet" << std::endl;
inst.dump();
exec->NOP();
}
if (breakpoint) {
std::cout << "Breakpoint set to true\n";
}
if (breakpoint) {
std::cout << "Breakpoint set to true\n";
}
perf->instructionsInc();
perf->instructionsInc();
return breakpoint;
}
return breakpoint;
}
[[noreturn]] void CPU::CPU_thread() {
[[noreturn]] void CPU::CPU_thread() {
sc_core::sc_time instr_time = default_time;
sc_core::sc_time instr_time = default_time;
while (true) {
while (true) {
/* Process one instruction */
CPU_step();
/* Process one instruction */
CPU_step();
/* Process IRQ (if any) */
cpu_process_IRQ();
/* Process IRQ (if any) */
cpu_process_IRQ();
/* Fixed instruction time to 10 ns (i.e. 100 MHz) */
/* Fixed instruction time to 10 ns (i.e. 100 MHz) */
//#define USE_QK
#ifdef USE_QK
// Model time used for additional processing
m_qk->inc(default_time);
if (m_qk->need_sync()) {
m_qk->sync();
}
// Model time used for additional processing
m_qk->inc(default_time);
if (m_qk->need_sync()) {
m_qk->sync();
}
#else
sc_core::wait(instr_time);
sc_core::wait(instr_time);
#endif
} // while(1)
} // CPU_thread
} // while(1)
} // CPU_thread
void CPU::call_interrupt(tlm::tlm_generic_payload &m_trans,
sc_core::sc_time &delay) {
interrupt = true;
/* Socket caller send a cause (its id) */
memcpy(&int_cause, m_trans.get_data_ptr(), sizeof(std::uint32_t));
delay = sc_core::SC_ZERO_TIME;
}
void CPU::call_interrupt(tlm::tlm_generic_payload &m_trans,
sc_core::sc_time &delay) {
interrupt = true;
/* Socket caller send a cause (its id) */
memcpy(&int_cause, m_trans.get_data_ptr(), sizeof(std::uint32_t));
delay = sc_core::SC_ZERO_TIME;
}
void CPU::invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end) {
(void) start;
(void) end;
dmi_ptr_valid = false;
void CPU::invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end) {
(void) start;
(void) end;
dmi_ptr_valid = false;
}
}

1448
src/C_extension.cpp
View File

File diff suppressed because it is too large Load Diff

446
src/Debug.cpp
View File

@ -18,234 +18,238 @@
#include "Debug.h"
constexpr char nibble_to_hex[16] = { '0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', 'a', 'b', 'c', 'd', 'e', 'f' };
namespace riscv_tlm {
Debug::Debug(CPU *cpu, Memory* mem): sc_module(sc_core::sc_module_name("Debug")) {
dbg_cpu = cpu;
dbg_mem = mem;
constexpr char nibble_to_hex[16] = {'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', 'a', 'b', 'c', 'd', 'e', 'f'};
int sock = socket(AF_INET, SOCK_STREAM, 0);
Debug::Debug(riscv_tlm::CPU *cpu, Memory *mem) : sc_module(sc_core::sc_module_name("Debug")) {
dbg_cpu = cpu;
dbg_mem = mem;
int optval = 1;
setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, &optval,
sizeof(optval));
int sock = socket(AF_INET, SOCK_STREAM, 0);
sockaddr_in addr;
addr.sin_family = AF_INET;
addr.sin_addr.s_addr = INADDR_ANY;
addr.sin_port = htons(1234);
int optval = 1;
setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, &optval,
sizeof(optval));
bind(sock, (struct sockaddr *) &addr, sizeof(addr));
listen(sock, 1);
sockaddr_in addr;
addr.sin_family = AF_INET;
addr.sin_addr.s_addr = INADDR_ANY;
addr.sin_port = htons(1234);
socklen_t len = sizeof(addr);
conn = accept(sock, (struct sockaddr *) &addr, &len);
bind(sock, (struct sockaddr *) &addr, sizeof(addr));
listen(sock, 1);
handle_gdb_loop();
}
socklen_t len = sizeof(addr);
conn = accept(sock, (struct sockaddr *) &addr, &len);
Debug::~Debug() {
handle_gdb_loop();
}
Debug::~Debug() {
}
void Debug::send_packet(int conn, const std::string &msg) {
std::string frame = "+$" + msg + "#" + compute_checksum_string(msg);
memcpy(iobuf, frame.c_str(), frame.size());
::send(conn, iobuf, frame.size(), 0);
}
std::string Debug::receive_packet() {
int nbytes = ::recv(conn, iobuf, bufsize, 0);
if (nbytes == 0) {
return "";
} else if (nbytes == 1) {
return std::string("+");
} else {
char *start = strchr(iobuf, '$');
char *end = strchr(iobuf, '#');
std::string message(start + 1, end - (start + 1));
return message;
}
}
void Debug::handle_gdb_loop() {
std::cout << "Handle_GDB_Loop\n";
Registers *register_bank = dbg_cpu->getRegisterBank();
while (true) {
std::string msg = receive_packet();
if (msg.size() == 0) {
std::cout << "remote connection seems to be closed, terminating ..."
<< std::endl;
break;
} else if (msg == "+") {
// NOTE: just ignore this message, nothing to do in this case
} else if (boost::starts_with(msg, "qSupported")) {
send_packet(conn, "PacketSize=256;swbreak+;hwbreak+;vContSupported+;multiprocess-");
} else if (msg == "vMustReplyEmpty") {
send_packet(conn, "");
} else if (msg == "Hg0") {
send_packet(conn, "OK");
} else if (msg == "Hc0") {
send_packet(conn, "");
} else if (msg == "qTStatus") {
send_packet(conn, "");
} else if (msg == "?") {
send_packet(conn, "S05");
} else if (msg == "qfThreadInfo") {
send_packet(conn, "");
} else if (boost::starts_with(msg, "qL")) {
send_packet(conn, "");
} else if (msg == "Hc-1") {
send_packet(conn, "OK");
} else if (msg == "qC") {
send_packet(conn, "-1");
} else if (msg == "qAttached") {
send_packet(conn, "0"); // 0 process started, 1 attached to process
} else if (msg == "g") {
std::stringstream stream;
stream << std::setfill('0') << std::hex;
for (int i = 1; i < 32; i++) {
stream << std::setw(8) << register_bank->getValue(i);
}
send_packet(conn, stream.str());
} else if (boost::starts_with(msg, "p")) {
long n = strtol(msg.c_str() + 1, 0, 16);
int reg_value;
if (n < 32) {
reg_value = register_bank->getValue(n);
} else if (n == 32) {
reg_value = register_bank->getPC();
} else {
// see: https://github.com/riscv/riscv-gnu-toolchain/issues/217
// risc-v register 834
reg_value = register_bank->getCSR(n - 65);
}
std::stringstream stream;
stream << std::setfill('0') << std::hex;
stream << std::setw(8) << htonl(reg_value);
send_packet(conn, stream.str());
} else if (boost::starts_with(msg, "P")) {
char *pEnd;
long reg = strtol(msg.c_str() + 1, &pEnd, 16);
int val = strtol(pEnd + 1, 0, 16);
register_bank->setValue(reg + 1, val);
send_packet(conn, "OK");
} else if (boost::starts_with(msg, "m")) {
char *pEnd;
long addr = strtol(msg.c_str() + 1, &pEnd, 16);;
int len = strtol(pEnd + 1, &pEnd, 16);
dbg_trans.set_data_ptr(pyld_array);
dbg_trans.set_command(tlm::TLM_READ_COMMAND);
dbg_trans.set_address(addr);
dbg_trans.set_data_length(len);
dbg_mem->transport_dbg(dbg_trans);
std::stringstream stream;
stream << std::setfill('0') << std::hex;
for (auto &c: pyld_array) {
stream << std::setw(2) << (0xFF & c);
}
send_packet(conn, stream.str());
} else if (boost::starts_with(msg, "M")) {
printf("M TBD\n");
send_packet(conn, "OK");
} else if (boost::starts_with(msg, "X")) {
send_packet(conn, ""); // binary data unsupported
} else if (msg == "qOffsets") {
send_packet(conn, "Text=0;Data=0;Bss=0");
} else if (msg == "qSymbol::") {
send_packet(conn, "OK");
} else if (msg == "vCont?") {
send_packet(conn, "vCont;cs");
} else if (msg == "c") {
bool breakpoint_hit = false;
bool bkpt = false;
do {
bkpt = dbg_cpu->CPU_step();
uint32_t currentPC = register_bank->getPC();
auto search = breakpoints.find(currentPC);
if (search != breakpoints.end()) {
breakpoint_hit = true;
}
} while ((breakpoint_hit == false) && (bkpt == false));
std::cout << "Breakpoint hit at 0x" << std::hex << register_bank->getPC() << std::endl;
send_packet(conn, "S05");
} else if (msg == "s") {
bool breakpoint;
dbg_cpu->CPU_step();
uint32_t currentPC = register_bank->getPC();
auto search = breakpoints.find(currentPC);
if (search != breakpoints.end()) {
breakpoint = true;
} else {
breakpoint = false;
}
if (breakpoint) {
send_packet(conn, "S03");
} else {
send_packet(conn, "S05");
}
} else if (boost::starts_with(msg, "vKill")) {
send_packet(conn, "OK");
break;
} else if (boost::starts_with(msg, "Z1")) {
char *pEnd;
long addr = strtol(msg.c_str() + 3, &pEnd, 16);;
breakpoints.insert(addr);
std::cout << "Breakpoint set to address 0x" << std::hex << addr << std::endl;
send_packet(conn, "OK");
} else if (boost::starts_with(msg, "z1")) {
char *pEnd;
long addr = strtol(msg.c_str() + 3, &pEnd, 16);;
breakpoints.erase(addr);
send_packet(conn, "OK");
} else if (boost::starts_with(msg, "z0")) {
char *pEnd;
long addr = strtol(msg.c_str() + 3, &pEnd, 16);;
breakpoints.erase(addr);
send_packet(conn, "");
} else if (boost::starts_with(msg, "Z0")) {
char *pEnd;
long addr = strtol(msg.c_str() + 3, &pEnd, 16);;
breakpoints.insert(addr);
std::cout << "Breakpoint set to address 0x" << std::hex << addr << std::endl;
send_packet(conn, "OK");
} else {
std::cout << "unsupported message '" << msg
<< "' detected, terminating ..." << std::endl;
break;
}
}
}
std::string Debug::compute_checksum_string(const std::string &msg) {
unsigned sum = 0;
for (auto c: msg) {
sum += unsigned(c);
}
sum = sum % 256;
char low = nibble_to_hex[sum & 0xf];
char high = nibble_to_hex[(sum & (0xf << 4)) >> 4];
return {high, low};
}
}
void Debug::send_packet(int conn, const std::string &msg) {
std::string frame = "+$" + msg + "#" + compute_checksum_string(msg);
memcpy(iobuf, frame.c_str(), frame.size());
::send(conn, iobuf, frame.size(), 0);
}
std::string Debug::receive_packet() {
int nbytes = ::recv(conn, iobuf, bufsize, 0);
if (nbytes == 0) {
return "";
} else if (nbytes == 1) {
return std::string("+");
} else {
char *start = strchr(iobuf, '$');
char *end = strchr(iobuf, '#');
std::string message(start + 1, end - (start + 1));
return message;
}
}
void Debug::handle_gdb_loop() {
std::cout << "Handle_GDB_Loop\n";
Registers *register_bank = dbg_cpu->getRegisterBank();
while (true) {
std::string msg = receive_packet();
if (msg.size() == 0) {
std::cout << "remote connection seems to be closed, terminating ..."
<< std::endl;
break;
} else if (msg == "+") {
// NOTE: just ignore this message, nothing to do in this case
} else if (boost::starts_with(msg, "qSupported")) {
send_packet(conn, "PacketSize=256;swbreak+;hwbreak+;vContSupported+;multiprocess-");
} else if (msg == "vMustReplyEmpty") {
send_packet(conn, "");
} else if (msg == "Hg0") {
send_packet(conn, "OK");
} else if (msg == "Hc0") {
send_packet(conn, "");
} else if (msg == "qTStatus") {
send_packet(conn, "");
} else if (msg == "?") {
send_packet(conn, "S05");
} else if (msg == "qfThreadInfo") {
send_packet(conn, "");
} else if (boost::starts_with(msg, "qL")) {
send_packet(conn, "");
} else if (msg == "Hc-1") {
send_packet(conn, "OK");
} else if (msg == "qC") {
send_packet(conn, "-1");
} else if (msg == "qAttached") {
send_packet(conn, "0"); // 0 process started, 1 attached to process
} else if (msg == "g") {
std::stringstream stream;
stream << std::setfill('0') << std::hex;
for (int i = 1; i < 32; i++) {
stream << std::setw(8) << register_bank->getValue(i);
}
send_packet(conn, stream.str());
} else if (boost::starts_with(msg, "p")) {
long n = strtol(msg.c_str() + 1, 0, 16);
int reg_value;
if (n < 32) {
reg_value = register_bank->getValue(n);
} else if (n == 32) {
reg_value = register_bank->getPC();
} else {
// see: https://github.com/riscv/riscv-gnu-toolchain/issues/217
// risc-v register 834
reg_value = register_bank->getCSR(n - 65);
}
std::stringstream stream;
stream << std::setfill('0') << std::hex;
stream << std::setw(8) << htonl(reg_value);
send_packet(conn, stream.str());
} else if (boost::starts_with(msg, "P")) {
char * pEnd;
long reg = strtol(msg.c_str() + 1, &pEnd, 16);
int val = strtol(pEnd + 1, 0, 16);
register_bank->setValue(reg + 1, val);
send_packet(conn, "OK");
} else if (boost::starts_with(msg, "m")) {
char * pEnd;
long addr = strtol(msg.c_str() + 1, &pEnd, 16);;
int len = strtol(pEnd + 1, &pEnd, 16);
dbg_trans.set_data_ptr(pyld_array);
dbg_trans.set_command(tlm::TLM_READ_COMMAND);
dbg_trans.set_address(addr);
dbg_trans.set_data_length(len);
dbg_mem->transport_dbg(dbg_trans);
std::stringstream stream;
stream << std::setfill('0') << std::hex;
for (auto &c : pyld_array) {
stream << std::setw(2) << (0xFF & c);
}
send_packet(conn, stream.str());
} else if (boost::starts_with(msg, "M")) {
printf("M TBD\n");
send_packet(conn, "OK");
} else if (boost::starts_with(msg, "X")) {
send_packet(conn, ""); // binary data unsupported
} else if (msg == "qOffsets") {
send_packet(conn, "Text=0;Data=0;Bss=0");
} else if (msg == "qSymbol::") {
send_packet(conn, "OK");
} else if (msg == "vCont?") {
send_packet(conn, "vCont;cs");
} else if (msg == "c") {
bool breakpoint_hit = false;
bool bkpt = false;
do {
bkpt = dbg_cpu->CPU_step();
uint32_t currentPC = register_bank->getPC();
auto search = breakpoints.find(currentPC);
if (search != breakpoints.end()) {
breakpoint_hit = true;
}
} while ((breakpoint_hit == false) && (bkpt == false));
std::cout << "Breakpoint hit at 0x" << std::hex << register_bank->getPC() << std::endl;
send_packet(conn, "S05");
} else if (msg == "s") {
bool breakpoint;
dbg_cpu->CPU_step();
uint32_t currentPC = register_bank->getPC();
auto search = breakpoints.find(currentPC);
if (search != breakpoints.end()) {
breakpoint = true;
} else {
breakpoint = false;
}
if (breakpoint) {
send_packet(conn, "S03");
} else {
send_packet(conn, "S05");
}
} else if (boost::starts_with(msg, "vKill")) {
send_packet(conn, "OK");
break;
} else if (boost::starts_with(msg, "Z1")) {
char * pEnd;
long addr = strtol(msg.c_str() + 3, &pEnd, 16);;
breakpoints.insert(addr);
std::cout << "Breakpoint set to address 0x"<< std::hex << addr << std::endl;
send_packet(conn, "OK");
} else if (boost::starts_with(msg, "z1")) {
char * pEnd;
long addr = strtol(msg.c_str() + 3, &pEnd, 16);;
breakpoints.erase(addr);
send_packet(conn, "OK");
} else if (boost::starts_with(msg, "z0")) {
char * pEnd;
long addr = strtol(msg.c_str() + 3, &pEnd, 16);;
breakpoints.erase(addr);
send_packet(conn, "");
} else if (boost::starts_with(msg, "Z0")) {
char * pEnd;
long addr = strtol(msg.c_str() + 3, &pEnd, 16);;
breakpoints.insert(addr);
std::cout << "Breakpoint set to address 0x"<< std::hex << addr << std::endl;
send_packet(conn, "OK");
} else {
std::cout << "unsupported message '" << msg
<< "' detected, terminating ..." << std::endl;
break;
}
}
}
std::string Debug::compute_checksum_string(const std::string &msg) {
unsigned sum = 0;
for (auto c : msg) {
sum += unsigned(c);
}
sum = sum % 256;
char low = nibble_to_hex[sum & 0xf];
char high = nibble_to_hex[(sum & (0xf << 4)) >> 4];
return {high, low};
}

44
src/Instruction.cpp
View File

@ -8,26 +8,28 @@
#include "Instruction.h"
Instruction::Instruction(std::uint32_t instr) {
m_instr = instr;
namespace riscv_tlm {
Instruction::Instruction(std::uint32_t instr) {
m_instr = instr;
}
extension_t Instruction::check_extension() const {
if (((m_instr & 0x0000007F) == 0b0110011)
&& (((m_instr & 0x7F000000) >> 25) == 0b0000001)) {
return M_EXTENSION;
} else if ((m_instr & 0x0000007F) == 0b0101111) {
return A_EXTENSION;
} else if ((m_instr & 0x00000003) == 0b00) {
return C_EXTENSION;
} else if ((m_instr & 0x00000003) == 0b01) {
return C_EXTENSION;
} else if ((m_instr & 0x00000003) == 0b10) {
return C_EXTENSION;
} else {
return BASE_EXTENSION;
}
}
}
extension_t Instruction::check_extension() const {
if (((m_instr & 0x0000007F) == 0b0110011)
&& ( ((m_instr & 0x7F000000) >> 25) == 0b0000001)) {
return M_EXTENSION;
} else if ((m_instr & 0x0000007F) == 0b0101111) {
return A_EXTENSION;
} else if ((m_instr & 0x00000003) == 0b00) {
return C_EXTENSION;
} else if ((m_instr & 0x00000003) == 0b01) {
return C_EXTENSION;
} else if ((m_instr & 0x00000003) == 0b10) {
return C_EXTENSION;
} else {
return BASE_EXTENSION;
}
}

560
src/M_extension.cpp
View File

@ -8,280 +8,292 @@
#include "M_extension.h"
op_M_Codes M_extension::decode() const {
namespace riscv_tlm {
switch (opcode()) {
case M_MUL:
return OP_M_MUL;
break;
case M_MULH:
return OP_M_MULH;
break;
case M_MULHSU:
return OP_M_MULHSU;
break;
case M_MULHU:
return OP_M_MULHU;
break;
case M_DIV:
return OP_M_DIV;
break;
case M_DIVU:
return OP_M_DIVU;
break;
case M_REM:
return OP_M_REM;
break;
case M_REMU:
return OP_M_REMU;
break;
[[unlikely]] default:
return OP_M_ERROR;
break;
}
op_M_Codes M_extension::decode() const {
switch (opcode()) {
case M_MUL:
return OP_M_MUL;
break;
case M_MULH:
return OP_M_MULH;
break;
case M_MULHSU:
return OP_M_MULHSU;
break;
case M_MULHU:
return OP_M_MULHU;
break;
case M_DIV:
return OP_M_DIV;
break;
case M_DIVU:
return OP_M_DIVU;
break;
case M_REM:
return OP_M_REM;
break;
case M_REMU:
return OP_M_REMU;
break;
[[unlikely]] default:
return OP_M_ERROR;
break;
}
return OP_M_ERROR;
}
bool M_extension::Exec_M_MUL() const {
int rd, rs1, rs2;
std::int32_t multiplier, multiplicand;
std::int64_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
multiplier = static_cast<std::int32_t>(regs->getValue(rs1));
multiplicand = static_cast<std::int32_t>(regs->getValue(rs2));
result = static_cast<std::int64_t>(multiplier * multiplicand);
result = result & 0x00000000FFFFFFFF;
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.MUL: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_MULH() const {
int rd, rs1, rs2;
std::int32_t multiplier, multiplicand;
std::int64_t result;
std::int32_t ret_value;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
multiplier = static_cast<std::int32_t>(regs->getValue(rs1));
multiplicand = static_cast<std::int32_t>(regs->getValue(rs2));
result = static_cast<std::int64_t>(multiplier) * static_cast<std::int64_t>(multiplicand);
ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value);
logger->debug("{} ns. PC: 0x{:x}. M.MULH: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_MULHSU() const {
int rd, rs1, rs2;
std::int32_t multiplier;
std::uint32_t multiplicand;
std::int64_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
multiplier = static_cast<std::int32_t>(regs->getValue(rs1));
multiplicand = regs->getValue(rs2);
result = static_cast<std::int64_t>(multiplier * static_cast<std::uint64_t>(multiplicand));
result = (result >> 32) & 0x00000000FFFFFFFF;
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.MULHSU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_MULHU() const {
int rd, rs1, rs2;
std::uint32_t multiplier, multiplicand;
std::uint64_t result;
std::int32_t ret_value;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
multiplier = static_cast<std::int32_t>(regs->getValue(rs1));
multiplicand = static_cast<std::int32_t>(regs->getValue(rs2));
result = static_cast<std::uint64_t>(multiplier) * static_cast<std::uint64_t>(multiplicand);
ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value);
logger->debug("{} ns. PC: 0x{:x}. M.MULHU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_DIV() const {
int rd, rs1, rs2;
std::int32_t divisor, dividend;
std::int64_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
dividend = static_cast<std::int32_t>(regs->getValue(rs1));
divisor = static_cast<std::int32_t>(regs->getValue(rs2));
if (divisor == 0) {
result = -1;
} else if ((divisor == -1) && (dividend == static_cast<std::int32_t>(0x80000000))) {
result = 0x0000000080000000;
} else {
result = dividend / divisor;
result = result & 0x00000000FFFFFFFF;
}
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.DIV: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_DIVU() const {
int rd, rs1, rs2;
std::uint32_t divisor, dividend;
std::uint64_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
dividend = regs->getValue(rs1);
divisor = regs->getValue(rs2);
if (divisor == 0) {
result = -1;
} else {
result = dividend / divisor;
result = result & 0x00000000FFFFFFFF;
}
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.DIVU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_REM() const {
int rd, rs1, rs2;
std::int32_t divisor, dividend;
std::int32_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
dividend = static_cast<std::int32_t>(regs->getValue(rs1));
divisor = static_cast<std::int32_t>(regs->getValue(rs2));
if (divisor == 0) {
result = dividend;
} else if ((divisor == -1) && (dividend == static_cast<std::int32_t>(0x80000000))) {
result = 0;
} else {
result = dividend % divisor;
}
regs->setValue(rd, result);
logger->debug("{} ns. PC: 0x{:x}. M.REM: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_REMU() const {
int rd, rs1, rs2;
std::uint32_t divisor, dividend;
std::uint32_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
dividend = static_cast<std::int32_t>(regs->getValue(rs1));
divisor = static_cast<std::int32_t>(regs->getValue(rs2));
if (divisor == 0) {
result = dividend;
} else {
result = dividend % divisor;
}
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.REMU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(),
regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::process_instruction(Instruction &inst) {
bool PC_not_affected = true;
setInstr(inst.getInstr());
switch (decode()) {
case OP_M_MUL:
Exec_M_MUL();
break;
case OP_M_MULH:
Exec_M_MULH();
break;
case OP_M_MULHSU:
Exec_M_MULHSU();
break;
case OP_M_MULHU:
Exec_M_MULHU();
break;
case OP_M_DIV:
Exec_M_DIV();
break;
case OP_M_DIVU:
Exec_M_DIVU();
break;
case OP_M_REM:
Exec_M_REM();
break;
case OP_M_REMU:
Exec_M_REMU();
break;
[[unlikely]] default:
std::cout << "M instruction not implemented yet" << "\n";
inst.dump();
//NOP(inst);
sc_core::sc_stop();
break;
}
return PC_not_affected;
}
return OP_M_ERROR;
}
bool M_extension::Exec_M_MUL() const {
int rd, rs1, rs2;
std::int32_t multiplier, multiplicand;
std::int64_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
multiplier = static_cast<std::int32_t>(regs->getValue(rs1));
multiplicand = static_cast<std::int32_t>(regs->getValue(rs2));
result = static_cast<std::int64_t>(multiplier * multiplicand);
result = result & 0x00000000FFFFFFFF;
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.MUL: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_MULH() const {
int rd, rs1, rs2;
std::int32_t multiplier, multiplicand;
std::int64_t result;
std::int32_t ret_value;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
multiplier = static_cast<std::int32_t>(regs->getValue(rs1));
multiplicand = static_cast<std::int32_t>(regs->getValue(rs2));
result = static_cast<std::int64_t>(multiplier) * static_cast<std::int64_t>(multiplicand);
ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value);
logger->debug("{} ns. PC: 0x{:x}. M.MULH: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_MULHSU() const {
int rd, rs1, rs2;
std::int32_t multiplier;
std::uint32_t multiplicand;
std::int64_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
multiplier = static_cast<std::int32_t>(regs->getValue(rs1));
multiplicand = regs->getValue(rs2);
result = static_cast<std::int64_t>(multiplier * static_cast<std::uint64_t>(multiplicand));
result = (result >> 32) & 0x00000000FFFFFFFF;
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.MULHSU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_MULHU() const {
int rd, rs1, rs2;
std::uint32_t multiplier, multiplicand;
std::uint64_t result;
std::int32_t ret_value;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
multiplier = static_cast<std::int32_t>(regs->getValue(rs1));
multiplicand = static_cast<std::int32_t>(regs->getValue(rs2));
result = static_cast<std::uint64_t>(multiplier) * static_cast<std::uint64_t>(multiplicand);
ret_value = static_cast<std::int32_t>((result >> 32) & 0x00000000FFFFFFFF);
regs->setValue(rd, ret_value);
logger->debug("{} ns. PC: 0x{:x}. M.MULHU: x{:d} * x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_DIV() const {
int rd, rs1, rs2;
std::int32_t divisor, dividend;
std::int64_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
dividend = static_cast<std::int32_t>(regs->getValue(rs1));
divisor = static_cast<std::int32_t>(regs->getValue(rs2));
if (divisor == 0) {
result = -1;
} else if ((divisor == -1) && (dividend == static_cast<std::int32_t>(0x80000000)) ) {
result = 0x0000000080000000;
} else {
result = dividend / divisor;
result = result & 0x00000000FFFFFFFF;
}
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.DIV: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_DIVU() const {
int rd, rs1, rs2;
std::uint32_t divisor, dividend;
std::uint64_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
dividend = regs->getValue(rs1);
divisor = regs->getValue(rs2);
if (divisor == 0) {
result = -1;
} else {
result = dividend / divisor;
result = result & 0x00000000FFFFFFFF;
}
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.DIVU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_REM() const {
int rd, rs1, rs2;
std::int32_t divisor, dividend;
std::int32_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
dividend = static_cast<std::int32_t>(regs->getValue(rs1));
divisor = static_cast<std::int32_t>(regs->getValue(rs2));
if (divisor == 0) {
result = dividend;
} else if ((divisor == -1) && (dividend == static_cast<std::int32_t>(0x80000000)) ) {
result = 0;
} else {
result = dividend % divisor;
}
regs->setValue(rd, result);
logger->debug("{} ns. PC: 0x{:x}. M.REM: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::Exec_M_REMU() const {
int rd, rs1, rs2;
std::uint32_t divisor, dividend;
std::uint32_t result;
rd = get_rd();
rs1 = get_rs1();
rs2 = get_rs2();
dividend = static_cast<std::int32_t>(regs->getValue(rs1));
divisor = static_cast<std::int32_t>(regs->getValue(rs2));
if (divisor == 0) {
result = dividend;
} else {
result = dividend % divisor;
}
regs->setValue(rd, static_cast<std::int32_t>(result));
logger->debug("{} ns. PC: 0x{:x}. M.REMU: x{:d} / x{:d} -> x{:d}({:d})", sc_core::sc_time_stamp().value(), regs->getPC(),
rs1, rs2, rd, result);
return true;
}
bool M_extension::process_instruction(Instruction &inst) {
bool PC_not_affected = true;
setInstr(inst.getInstr());
switch (decode()) {
case OP_M_MUL:
Exec_M_MUL();
break;
case OP_M_MULH:
Exec_M_MULH();
break;
case OP_M_MULHSU:
Exec_M_MULHSU();
break;
case OP_M_MULHU:
Exec_M_MULHU();
break;
case OP_M_DIV:
Exec_M_DIV();
break;
case OP_M_DIVU:
Exec_M_DIVU();
break;
case OP_M_REM:
Exec_M_REM();
break;
case OP_M_REMU:
Exec_M_REMU();
break;
[[unlikely]] default:
std::cout << "M instruction not implemented yet" << "\n";
inst.dump();
//NOP(inst);
sc_core::sc_stop();
break;
}
return PC_not_affected;
}

353
src/Memory.cpp
View File

@ -8,194 +8,199 @@
#include "Memory.h"
SC_HAS_PROCESS(Memory);
Memory::Memory(sc_core::sc_module_name const &name, std::string const &filename) :
sc_module(name), socket("socket"), LATENCY(sc_core::SC_ZERO_TIME) {
// Register callbacks for incoming interface method calls
socket.register_b_transport(this, &Memory::b_transport);
socket.register_get_direct_mem_ptr(this, &Memory::get_direct_mem_ptr);
socket.register_transport_dbg(this, &Memory::transport_dbg);
namespace riscv_tlm {
dmi_allowed = false;
program_counter = 0;
readHexFile(filename);
SC_HAS_PROCESS(Memory);
logger = spdlog::get("my_logger");
logger->debug("Using file {}", filename);
}
Memory::Memory(sc_core::sc_module_name const &name, std::string const &filename) :
sc_module(name), socket("socket"), LATENCY(sc_core::SC_ZERO_TIME) {
// Register callbacks for incoming interface method calls
socket.register_b_transport(this, &Memory::b_transport);
socket.register_get_direct_mem_ptr(this, &Memory::get_direct_mem_ptr);
socket.register_transport_dbg(this, &Memory::transport_dbg);
Memory::Memory(sc_core::sc_module_name const& name) :
sc_module(name), socket("socket"), LATENCY(sc_core::SC_ZERO_TIME) {
socket.register_b_transport(this, &Memory::b_transport);
socket.register_get_direct_mem_ptr(this, &Memory::get_direct_mem_ptr);
socket.register_transport_dbg(this, &Memory::transport_dbg);
dmi_allowed = false;
program_counter = 0;
readHexFile(filename);
program_counter = 0;
logger = spdlog::get("my_logger");
logger->debug("Memory instantiated wihtout file");
}
Memory::~Memory() = default;
std::uint32_t Memory::getPCfromHEX() {
return program_counter;
}
void Memory::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
unsigned char *byt = trans.get_byte_enable_ptr();
unsigned int wid = trans.get_streaming_width();
// *********************************************
// Generate the appropriate error response
// *********************************************
if (adr >= sc_dt::uint64(Memory::SIZE)) {
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return;
}
if (byt != nullptr) {
trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
return;
}
if (len > 4 || wid < len) {
trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE);
return;
}
// Obliged to implement read and write commands
if (cmd == tlm::TLM_READ_COMMAND) {
std::copy_n(mem.cbegin() + adr, len, ptr);
} else if (cmd == tlm::TLM_WRITE_COMMAND) {
std::copy_n(ptr, len, mem.begin() + adr);
logger = spdlog::get("my_logger");
logger->debug("Using file {}", filename);
}
// Illustrates that b_transport may block
//sc_core::wait(delay);
Memory::Memory(sc_core::sc_module_name const &name) :
sc_module(name), socket("socket"), LATENCY(sc_core::SC_ZERO_TIME) {
socket.register_b_transport(this, &Memory::b_transport);
socket.register_get_direct_mem_ptr(this, &Memory::get_direct_mem_ptr);
socket.register_transport_dbg(this, &Memory::transport_dbg);
// Reset timing annotation after waiting
delay = sc_core::SC_ZERO_TIME;
program_counter = 0;
// *********************************************
// Set DMI hint to indicated that DMI is supported
// *********************************************
trans.set_dmi_allowed(dmi_allowed);
// Obliged to set response status to indicate successful completion
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
bool Memory::get_direct_mem_ptr(tlm::tlm_generic_payload &trans,
tlm::tlm_dmi &dmi_data) {
(void) trans;
if (!dmi_allowed) {
return false;
}
// Permit read and write access
dmi_data.allow_read_write();
// Set other details of DMI region
dmi_data.set_dmi_ptr(reinterpret_cast<unsigned char*>(&mem[0]));
dmi_data.set_start_address(0);
dmi_data.set_end_address(Memory::SIZE * 4 - 1);
dmi_data.set_read_latency(LATENCY);
dmi_data.set_write_latency(LATENCY);
return true;
}
unsigned int Memory::transport_dbg(tlm::tlm_generic_payload &trans) {
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
if (adr >= sc_dt::uint64(Memory::SIZE)) {
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return 0;
}
// Calculate the number of bytes to be actually copied
unsigned int num_bytes = (len < (Memory::SIZE - adr) * 4) ? len : (Memory::SIZE - adr) * 4;
if (cmd == tlm::TLM_READ_COMMAND) {
std::copy_n(mem.cbegin() + adr, len, ptr);
} else if (cmd == tlm::TLM_WRITE_COMMAND) {
std::copy_n(ptr, len, mem.begin() + adr);
logger = spdlog::get("my_logger");
logger->debug("Memory instantiated wihtout file");
}
return num_bytes;
}
Memory::~Memory() = default;
void Memory::readHexFile(std::string const& filename) {
std::ifstream hexfile;
std::string line;
std::uint32_t memory_offset = 0;
std::uint32_t Memory::getPCfromHEX() {
return program_counter;
hexfile.open(filename);
}
if (hexfile.is_open()) {
std::uint32_t extended_address = 0;
void Memory::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
unsigned char *byt = trans.get_byte_enable_ptr();
unsigned int wid = trans.get_streaming_width();
while (getline(hexfile, line)) {
if (line[0] == ':') {
if (line.substr(7, 2) == "00") {
/* Data */
int byte_count;
std::uint32_t address;
byte_count = std::stoi(line.substr(1, 2), nullptr, 16);
address = std::stoi(line.substr(3, 4), nullptr, 16);
address = address + extended_address + memory_offset;
for (int i = 0; i < byte_count; i++) {
mem[address + i] = stol(line.substr(9 + (i * 2), 2),
nullptr, 16);
}
} else if (line.substr(7, 2) == "02") {
/* Extended segment address */
extended_address = stol(line.substr(9, 4), nullptr, 16)
* 16;
std::cout << "02 extended address 0x" << std::hex
<< extended_address << std::dec << std::endl;
} else if (line.substr(7, 2) == "03") {
/* Start segment address */
std::uint32_t code_segment;
code_segment = stol(line.substr(9, 4), nullptr, 16) * 16; /* ? */
program_counter = stol(line.substr(13, 4), nullptr, 16);
program_counter = program_counter + code_segment;
std::cout << "03 PC set to 0x" << std::hex
<< program_counter << std::dec << std::endl;
} else if (line.substr(7, 2) == "04") {
/* Start segment address */
memory_offset = stol(line.substr(9, 4), nullptr, 16) << 16;
extended_address = 0;
std::cout << "04 address set to 0x" << std::hex
<< extended_address << std::dec << std::endl;
std::cout << "04 offset set to 0x" << std::hex
<< memory_offset << std::dec << std::endl;
} else if (line.substr(7, 2) == "05") {
program_counter = stol(line.substr(9, 8), nullptr, 16);
std::cout << "05 PC set to 0x" << std::hex
<< program_counter << std::dec << std::endl;
}
}
}
hexfile.close();
if (memory_offset != 0) {
dmi_allowed = false;
} else {
dmi_allowed = true;
// *********************************************
// Generate the appropriate error response
// *********************************************
if (adr >= sc_dt::uint64(Memory::SIZE)) {
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return;
}
if (byt != nullptr) {
trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
return;
}
if (len > 4 || wid < len) {
trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE);
return;
}
} else {
SC_REPORT_ERROR("Memory", "Open file error");
}
// Obliged to implement read and write commands
if (cmd == tlm::TLM_READ_COMMAND) {
std::copy_n(mem.cbegin() + adr, len, ptr);
} else if (cmd == tlm::TLM_WRITE_COMMAND) {
std::copy_n(ptr, len, mem.begin() + adr);
}
// Illustrates that b_transport may block
//sc_core::wait(delay);
// Reset timing annotation after waiting
delay = sc_core::SC_ZERO_TIME;
// *********************************************
// Set DMI hint to indicated that DMI is supported
// *********************************************
trans.set_dmi_allowed(dmi_allowed);
// Obliged to set response status to indicate successful completion
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
bool Memory::get_direct_mem_ptr(tlm::tlm_generic_payload &trans,
tlm::tlm_dmi &dmi_data) {
(void) trans;
if (!dmi_allowed) {
return false;
}
// Permit read and write access
dmi_data.allow_read_write();
// Set other details of DMI region
dmi_data.set_dmi_ptr(reinterpret_cast<unsigned char *>(&mem[0]));
dmi_data.set_start_address(0);
dmi_data.set_end_address(Memory::SIZE * 4 - 1);
dmi_data.set_read_latency(LATENCY);
dmi_data.set_write_latency(LATENCY);
return true;
}
unsigned int Memory::transport_dbg(tlm::tlm_generic_payload &trans) {
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
if (adr >= sc_dt::uint64(Memory::SIZE)) {
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return 0;
}
// Calculate the number of bytes to be actually copied
unsigned int num_bytes = (len < (Memory::SIZE - adr) * 4) ? len : (Memory::SIZE - adr) * 4;
if (cmd == tlm::TLM_READ_COMMAND) {
std::copy_n(mem.cbegin() + adr, len, ptr);
} else if (cmd == tlm::TLM_WRITE_COMMAND) {
std::copy_n(ptr, len, mem.begin() + adr);
}
return num_bytes;
}
void Memory::readHexFile(std::string const &filename) {
std::ifstream hexfile;
std::string line;
std::uint32_t memory_offset = 0;
hexfile.open(filename);
if (hexfile.is_open()) {
std::uint32_t extended_address = 0;
while (getline(hexfile, line)) {
if (line[0] == ':') {
if (line.substr(7, 2) == "00") {
/* Data */
int byte_count;
std::uint32_t address;
byte_count = std::stoi(line.substr(1, 2), nullptr, 16);
address = std::stoi(line.substr(3, 4), nullptr, 16);
address = address + extended_address + memory_offset;
for (int i = 0; i < byte_count; i++) {
mem[address + i] = stol(line.substr(9 + (i * 2), 2),
nullptr, 16);
}
} else if (line.substr(7, 2) == "02") {
/* Extended segment address */
extended_address = stol(line.substr(9, 4), nullptr, 16)
* 16;
std::cout << "02 extended address 0x" << std::hex
<< extended_address << std::dec << std::endl;
} else if (line.substr(7, 2) == "03") {
/* Start segment address */
std::uint32_t code_segment;
code_segment = stol(line.substr(9, 4), nullptr, 16) * 16; /* ? */
program_counter = stol(line.substr(13, 4), nullptr, 16);
program_counter = program_counter + code_segment;
std::cout << "03 PC set to 0x" << std::hex
<< program_counter << std::dec << std::endl;
} else if (line.substr(7, 2) == "04") {
/* Start segment address */
memory_offset = stol(line.substr(9, 4), nullptr, 16) << 16;
extended_address = 0;
std::cout << "04 address set to 0x" << std::hex
<< extended_address << std::dec << std::endl;
std::cout << "04 offset set to 0x" << std::hex
<< memory_offset << std::dec << std::endl;
} else if (line.substr(7, 2) == "05") {
program_counter = stol(line.substr(9, 8), nullptr, 16);
std::cout << "05 PC set to 0x" << std::hex
<< program_counter << std::dec << std::endl;
}
}
}
hexfile.close();
if (memory_offset != 0) {
dmi_allowed = false;
} else {
dmi_allowed = true;
}
} else {
SC_REPORT_ERROR("Memory", "Open file error");
}
}
}

66
src/MemoryInterface.cpp
View File

@ -8,9 +8,10 @@
#include "MemoryInterface.h"
namespace riscv_tlm {
MemoryInterface::MemoryInterface() :
data_bus("data_bus") {}
MemoryInterface::MemoryInterface() :
data_bus("data_bus") {}
/**
* Access data memory to get data
@ -18,27 +19,27 @@ MemoryInterface::MemoryInterface() :
* @param size size of the data to read in bytes
* @return data value read
*/
std::uint32_t MemoryInterface::readDataMem(std::uint32_t addr, int size) {
std::uint32_t data;
tlm::tlm_generic_payload trans;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
std::uint32_t MemoryInterface::readDataMem(std::uint32_t addr, int size) {
std::uint32_t data;
tlm::tlm_generic_payload trans;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
trans.set_command(tlm::TLM_READ_COMMAND);
trans.set_data_ptr(reinterpret_cast<unsigned char*>(&data));
trans.set_data_length(size);
trans.set_streaming_width(4); // = data_length to indicate no streaming
trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
trans.set_dmi_allowed(false); // Mandatory initial value
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
trans.set_address(addr);
trans.set_command(tlm::TLM_READ_COMMAND);
trans.set_data_ptr(reinterpret_cast<unsigned char *>(&data));
trans.set_data_length(size);
trans.set_streaming_width(4); // = data_length to indicate no streaming
trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
trans.set_dmi_allowed(false); // Mandatory initial value
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
trans.set_address(addr);
data_bus->b_transport(trans, delay);
data_bus->b_transport(trans, delay);
if (trans.is_response_error()) {
SC_REPORT_ERROR("Memory", "Read memory");
}
return data;
}
if (trans.is_response_error()) {
SC_REPORT_ERROR("Memory", "Read memory");
}
return data;
}
/**
* Acces data memory to write data
@ -47,18 +48,19 @@ std::uint32_t MemoryInterface::readDataMem(std::uint32_t addr, int size) {
* @param data data to write
* @param size size of the data to write in bytes
*/
void MemoryInterface::writeDataMem(std::uint32_t addr, std::uint32_t data, int size) {
tlm::tlm_generic_payload trans;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
void MemoryInterface::writeDataMem(std::uint32_t addr, std::uint32_t data, int size) {
tlm::tlm_generic_payload trans;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
trans.set_command(tlm::TLM_WRITE_COMMAND);
trans.set_data_ptr(reinterpret_cast<unsigned char*>(&data));
trans.set_data_length(size);
trans.set_streaming_width(4); // = data_length to indicate no streaming
trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
trans.set_dmi_allowed(false); // Mandatory initial value
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
trans.set_address(addr);
trans.set_command(tlm::TLM_WRITE_COMMAND);
trans.set_data_ptr(reinterpret_cast<unsigned char *>(&data));
trans.set_data_length(size);
trans.set_streaming_width(4); // = data_length to indicate no streaming
trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
trans.set_dmi_allowed(false); // Mandatory initial value
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
trans.set_address(addr);
data_bus->b_transport(trans, delay);
data_bus->b_transport(trans, delay);
}
}

325
src/Registers.cpp
View File

@ -8,166 +8,169 @@
#include "Registers.h"
Registers::Registers() {
perf = Performance::getInstance();
namespace riscv_tlm {
initCSR();
register_bank[sp] = Memory::SIZE - 4; // default stack at the end of the memory
register_PC = 0x80000000; // default _start address
}
void Registers::dump() {
std::cout << "************************************" << std::endl;
std::cout << "Registers dump" << std::dec << std::endl;
std::cout << std::setfill('0') << std::uppercase;
std::cout << "x0 (zero): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[0];
std::cout << " x1 (ra): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[1];
std::cout << " x2 (sp): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[2];
std::cout << " x3 (gp): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[3] << std::endl;
std::cout << "x4 (tp): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[4];
std::cout << " x5 (t0): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[5];
std::cout << " x6 (t1): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[6];
std::cout << " x7 (t2): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[7] << std::endl;
std::cout << "x8 (s0/fp): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[8];
std::cout << " x9 (s1): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[9];
std::cout << " x10 (a0): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[10];
std::cout << " x11 (a1): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[11] << std::endl;
std::cout << "x12 (a2): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[12];
std::cout << " x13 (a3): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[13];
std::cout << " x14 (a4): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[14];
std::cout << " x15 (a5): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[15] << std::endl;
std::cout << "x16 (a6): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[16];
std::cout << " x17 (a7): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[17];
std::cout << " x18 (s2): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[18];
std::cout << " x19 (s3): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[19] << std::endl;
std::cout << "x20 (s4): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[20];
std::cout << " x21 (s5): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[21];
std::cout << " x22 (s6): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[22];
std::cout << " x23 (s7): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[23] << std::endl;
std::cout << "x24 (s8): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[24];
std::cout << " x25 (s9): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[25];
std::cout << " x26 (s10): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[26];
std::cout << " x27 (s11): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[27] << std::endl;
std::cout << "x28 (t3): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[28];
std::cout << " x29 (t4): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[29];
std::cout << " x30 (t5): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[30];
std::cout << " x31 (t6): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[31] << std::endl;
std::cout << "PC: 0x" << std::setw(8) << std::hex << register_PC << std::dec << std::endl;
std::cout << "************************************" << std::endl;
}
void Registers::setValue(int reg_num, std::int32_t value) {
if ((reg_num != 0) && (reg_num < 32)) {
register_bank[reg_num] = value;
perf->registerWrite();
}
}
std::uint32_t Registers::getValue(int reg_num) const {
if ((reg_num >= 0) && (reg_num < 32)) {
perf->registerRead();
return register_bank[reg_num];
} else {
return static_cast<std::int32_t>(0xFFFFFFFF);
}
}
std::uint32_t Registers::getPC() const {
return register_PC;
}
void Registers::setPC(std::uint32_t new_pc) {
register_PC = new_pc;
}
std::uint32_t Registers::getCSR(const int csr) {
std::uint32_t ret_value;
switch (csr) {
case CSR_CYCLE:
case CSR_MCYCLE:
ret_value = static_cast<std::uint64_t>(sc_core::sc_time(
sc_core::sc_time_stamp()
- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
& 0x00000000FFFFFFFF;
break;
case CSR_CYCLEH:
case CSR_MCYCLEH:
ret_value = static_cast<std::uint32_t>((std::uint64_t) (sc_core::sc_time(
sc_core::sc_time_stamp()
- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
>> 32 & 0x00000000FFFFFFFF);
break;
case CSR_TIME:
ret_value = static_cast<std::uint64_t>(sc_core::sc_time(
sc_core::sc_time_stamp()
- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
& 0x00000000FFFFFFFF;
break;
case CSR_TIMEH:
ret_value = static_cast<std::uint32_t>((std::uint64_t) (sc_core::sc_time(
sc_core::sc_time_stamp()
- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
>> 32 & 0x00000000FFFFFFFF);
break;
[[likely]] default:
ret_value = CSR[csr];
break;
}
return ret_value;
}
void Registers::setCSR(int csr, std::uint32_t value) {
/* @FIXME: rv32mi-p-ma_fetch tests doesn't allow MISA to be writable,
* but Volume II: Privileged Architecture v1.10 says MISA is writable (?)
*/
if (csr != CSR_MISA) {
CSR[csr] = value;
}
}
void Registers::initCSR() {
CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
| MISA_A_EXTENSION | MISA_I_BASE;
CSR[CSR_MSTATUS] = MISA_MXL;
Registers::Registers() {
perf = Performance::getInstance();
initCSR();
register_bank[sp] = Memory::SIZE - 4; // default stack at the end of the memory
register_PC = 0x80000000; // default _start address
}
void Registers::dump() {
std::cout << "************************************" << std::endl;
std::cout << "Registers dump" << std::dec << std::endl;
std::cout << std::setfill('0') << std::uppercase;
std::cout << "x0 (zero): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[0];
std::cout << " x1 (ra): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[1];
std::cout << " x2 (sp): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[2];
std::cout << " x3 (gp): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[3] << std::endl;
std::cout << "x4 (tp): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[4];
std::cout << " x5 (t0): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[5];
std::cout << " x6 (t1): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[6];
std::cout << " x7 (t2): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[7] << std::endl;
std::cout << "x8 (s0/fp): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[8];
std::cout << " x9 (s1): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[9];
std::cout << " x10 (a0): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[10];
std::cout << " x11 (a1): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[11] << std::endl;
std::cout << "x12 (a2): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[12];
std::cout << " x13 (a3): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[13];
std::cout << " x14 (a4): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[14];
std::cout << " x15 (a5): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[15] << std::endl;
std::cout << "x16 (a6): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[16];
std::cout << " x17 (a7): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[17];
std::cout << " x18 (s2): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[18];
std::cout << " x19 (s3): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[19] << std::endl;
std::cout << "x20 (s4): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[20];
std::cout << " x21 (s5): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[21];
std::cout << " x22 (s6): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[22];
std::cout << " x23 (s7): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[23] << std::endl;
std::cout << "x24 (s8): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[24];
std::cout << " x25 (s9): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[25];
std::cout << " x26 (s10): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[26];
std::cout << " x27 (s11): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[27] << std::endl;
std::cout << "x28 (t3): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[28];
std::cout << " x29 (t4): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[29];
std::cout << " x30 (t5): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[30];
std::cout << " x31 (t6): 0x" << std::right << std::setw(8)
<< std::hex << register_bank[31] << std::endl;
std::cout << "PC: 0x" << std::setw(8) << std::hex << register_PC << std::dec << std::endl;
std::cout << "************************************" << std::endl;
}
void Registers::setValue(int reg_num, std::int32_t value) {
if ((reg_num != 0) && (reg_num < 32)) {
register_bank[reg_num] = value;
perf->registerWrite();
}
}
std::uint32_t Registers::getValue(int reg_num) const {
if ((reg_num >= 0) && (reg_num < 32)) {
perf->registerRead();
return register_bank[reg_num];
} else {
return static_cast<std::int32_t>(0xFFFFFFFF);
}
}
std::uint32_t Registers::getPC() const {
return register_PC;
}
void Registers::setPC(std::uint32_t new_pc) {
register_PC = new_pc;
}
std::uint32_t Registers::getCSR(const int csr) {
std::uint32_t ret_value;
switch (csr) {
case CSR_CYCLE:
case CSR_MCYCLE:
ret_value = static_cast<std::uint64_t>(sc_core::sc_time(
sc_core::sc_time_stamp()
- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
& 0x00000000FFFFFFFF;
break;
case CSR_CYCLEH:
case CSR_MCYCLEH:
ret_value = static_cast<std::uint32_t>((std::uint64_t) (sc_core::sc_time(
sc_core::sc_time_stamp()
- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
>> 32 & 0x00000000FFFFFFFF);
break;
case CSR_TIME:
ret_value = static_cast<std::uint64_t>(sc_core::sc_time(
sc_core::sc_time_stamp()
- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
& 0x00000000FFFFFFFF;
break;
case CSR_TIMEH:
ret_value = static_cast<std::uint32_t>((std::uint64_t) (sc_core::sc_time(
sc_core::sc_time_stamp()
- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
>> 32 & 0x00000000FFFFFFFF);
break;
[[likely]] default:
ret_value = CSR[csr];
break;
}
return ret_value;
}
void Registers::setCSR(int csr, std::uint32_t value) {
/* @FIXME: rv32mi-p-ma_fetch tests doesn't allow MISA to be writable,
* but Volume II: Privileged Architecture v1.10 says MISA is writable (?)
*/
if (csr != CSR_MISA) {
CSR[csr] = value;
}
}
void Registers::initCSR() {
CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
| MISA_A_EXTENSION | MISA_I_BASE;
CSR[CSR_MSTATUS] = MISA_MXL;
}
}

22
src/Simulator.cpp
View File

@ -39,23 +39,23 @@ uint32_t dump_addr_end = 0;
*/
class Simulator : sc_core::sc_module {
public:
CPU *cpu;
Memory *MainMemory;
BusCtrl *Bus;
Trace *trace;
Timer *timer;
riscv_tlm::CPU *cpu;
riscv_tlm::Memory *MainMemory;
riscv_tlm::BusCtrl *Bus;
riscv_tlm::peripherals::Trace *trace;
riscv_tlm::peripherals::Timer *timer;
explicit Simulator(sc_core::sc_module_name const &name): sc_module(name) {
std::uint32_t start_PC;
MainMemory = new Memory("Main_Memory", filename);
MainMemory = new riscv_tlm::Memory("Main_Memory", filename);
start_PC = MainMemory->getPCfromHEX();
cpu = new CPU("cpu", start_PC, debug_session);
cpu = new riscv_tlm::CPU("cpu", start_PC, debug_session);
Bus = new BusCtrl("BusCtrl");
trace = new Trace("Trace");
timer = new Timer("Timer");
Bus = new riscv_tlm::BusCtrl("BusCtrl");
trace = new riscv_tlm::peripherals::Trace("Trace");
timer = new riscv_tlm::peripherals::Timer("Timer");
cpu->instr_bus.bind(Bus->cpu_instr_socket);
cpu->mem_intf->data_bus.bind(Bus->cpu_data_socket);
@ -67,7 +67,7 @@ public:
timer->irq_line.bind(cpu->irq_line_socket);
if (debug_session) {
Debug debug(cpu, MainMemory);
riscv_tlm::Debug debug(cpu, MainMemory);
}
}

178
src/Timer.cpp
View File

@ -9,93 +9,97 @@
#include <cstdint>
#include "Timer.h"
SC_HAS_PROCESS(Timer);
Timer::Timer(sc_core::sc_module_name const &name) :
sc_module(name), socket("timer_socket"), m_mtime(0), m_mtimecmp(0) {
namespace riscv_tlm::peripherals {
SC_HAS_PROCESS(Timer);
socket.register_b_transport(this, &Timer::b_transport);
Timer::Timer(sc_core::sc_module_name const &name) :
sc_module(name), socket("timer_socket"), m_mtime(0), m_mtimecmp(0) {
socket.register_b_transport(this, &Timer::b_transport);
SC_THREAD(run);
}
[[noreturn]] void Timer::run() {
auto *irq_trans = new tlm::tlm_generic_payload;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
std::uint32_t cause = 1 << 31 | 0x07; // Machine timer interrupt
irq_trans->set_command(tlm::TLM_WRITE_COMMAND);
irq_trans->set_data_ptr(reinterpret_cast<unsigned char *>(&cause));
irq_trans->set_data_length(4);
irq_trans->set_streaming_width(4);
irq_trans->set_byte_enable_ptr(nullptr);
irq_trans->set_dmi_allowed(false);
irq_trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
irq_trans->set_address(0);
while (true) {
wait(timer_event);
irq_line->b_transport(*irq_trans, delay);
}
}
void Timer::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 addr = trans.get_address();
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
delay = sc_core::SC_ZERO_TIME;
std::uint32_t aux_value = 0;
if (cmd == tlm::TLM_WRITE_COMMAND) {
memcpy(&aux_value, ptr, len);
switch (addr) {
case TIMER_MEMORY_ADDRESS_LO:
m_mtime.range(31, 0) = aux_value;
break;
case TIMER_MEMORY_ADDRESS_HI:
m_mtime.range(63, 32) = aux_value;
break;
case TIMERCMP_MEMORY_ADDRESS_LO:
m_mtimecmp.range(31, 0) = aux_value;
break;
case TIMERCMP_MEMORY_ADDRESS_HI:
m_mtimecmp.range(63, 32) = aux_value;
std::uint64_t notify_time;
// notify needs relative time, mtimecmp works in absolute time
notify_time = m_mtimecmp - m_mtime;
timer_event.notify(sc_core::sc_time(notify_time, sc_core::SC_NS));
break;
default:
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return;
}
} else { // TLM_READ_COMMAND
switch (addr) {
case TIMER_MEMORY_ADDRESS_LO:
m_mtime = sc_core::sc_time_stamp().value();
aux_value = m_mtime.range(31, 0);
break;
case TIMER_MEMORY_ADDRESS_HI:
aux_value = m_mtime.range(63, 32);
break;
case TIMERCMP_MEMORY_ADDRESS_LO:
aux_value = m_mtimecmp.range(31, 0);
break;
case TIMERCMP_MEMORY_ADDRESS_HI:
aux_value = m_mtimecmp.range(63, 32);
break;
default:
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return;
}
memcpy(ptr, &aux_value, len);
}
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
SC_THREAD(run);
}
[[noreturn]] void Timer::run() {
auto *irq_trans = new tlm::tlm_generic_payload;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
std::uint32_t cause = 1 << 31 | 0x07; // Machine timer interrupt
irq_trans->set_command(tlm::TLM_WRITE_COMMAND);
irq_trans->set_data_ptr(reinterpret_cast<unsigned char*>(&cause));
irq_trans->set_data_length(4);
irq_trans->set_streaming_width(4);
irq_trans->set_byte_enable_ptr(nullptr);
irq_trans->set_dmi_allowed(false);
irq_trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
irq_trans->set_address(0);
while (true) {
wait(timer_event);
irq_line->b_transport(*irq_trans, delay);
}
}
void Timer::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
tlm::tlm_command cmd = trans.get_command();
sc_dt::uint64 addr = trans.get_address();
unsigned char *ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
delay = sc_core::SC_ZERO_TIME;
std::uint32_t aux_value = 0;
if (cmd == tlm::TLM_WRITE_COMMAND) {
memcpy(&aux_value, ptr, len);
switch (addr) {
case TIMER_MEMORY_ADDRESS_LO:
m_mtime.range(31, 0) = aux_value;
break;
case TIMER_MEMORY_ADDRESS_HI:
m_mtime.range(63, 32) = aux_value;
break;
case TIMERCMP_MEMORY_ADDRESS_LO:
m_mtimecmp.range(31, 0) = aux_value;
break;
case TIMERCMP_MEMORY_ADDRESS_HI:
m_mtimecmp.range(63, 32) = aux_value;
std::uint64_t notify_time;
// notify needs relative time, mtimecmp works in absolute time
notify_time = m_mtimecmp - m_mtime;
timer_event.notify(sc_core::sc_time(notify_time, sc_core::SC_NS));
break;
default:
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return;
}
} else { // TLM_READ_COMMAND
switch (addr) {
case TIMER_MEMORY_ADDRESS_LO:
m_mtime = sc_core::sc_time_stamp().value();
aux_value = m_mtime.range(31, 0);
break;
case TIMER_MEMORY_ADDRESS_HI:
aux_value = m_mtime.range(63, 32);
break;
case TIMERCMP_MEMORY_ADDRESS_LO:
aux_value = m_mtimecmp.range(31, 0);
break;
case TIMERCMP_MEMORY_ADDRESS_HI:
aux_value = m_mtimecmp.range(63, 32);
break;
default:
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return;
}
memcpy(ptr, &aux_value, len);
}
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}

175
src/Trace.cpp
View File

@ -20,92 +20,97 @@
#include "Trace.h"
void Trace::xtermLaunch(char *slaveName) const {
char *arg;
char *fin = &(slaveName[strlen(slaveName) - 2]);
namespace riscv_tlm::peripherals {
if ( nullptr == strchr(fin, '/')) {
arg = new char[2 + 1 + 1 + 20 + 1];
sprintf(arg, "-S%c%c%d", fin[0], fin[1], ptMaster);
} else {
char *slaveBase = ::basename(slaveName);
arg = new char[2 + strlen(slaveBase) + 1 + 20 + 1];
sprintf(arg, "-S%s/%d", slaveBase, ptMaster);
}
void Trace::xtermLaunch(char *slaveName) const {
char *arg;
char *fin = &(slaveName[strlen(slaveName) - 2]);
char *argv[3];
argv[0] = (char*) ("xterm");
argv[1] = arg;
argv[2] = nullptr;
if (nullptr == strchr(fin, '/')) {
arg = new char[2 + 1 + 1 + 20 + 1];
sprintf(arg, "-S%c%c%d", fin[0], fin[1], ptMaster);
} else {
char *slaveBase = ::basename(slaveName);
arg = new char[2 + strlen(slaveBase) + 1 + 20 + 1];
sprintf(arg, "-S%s/%d", slaveBase, ptMaster);
}
char *argv[3];
argv[0] = (char *) ("xterm");
argv[1] = arg;
argv[2] = nullptr;
execvp("xterm", argv);
}
void Trace::xtermKill() {
if (-1 != ptSlave) { // Close down the slave
close(ptSlave); // Close the FD
ptSlave = -1;
}
if (-1 != ptMaster) { // Close down the master
close(ptMaster);
ptMaster = -1;
}
if (xtermPid > 0) { // Kill the terminal
kill(xtermPid, SIGKILL);
waitpid(xtermPid, nullptr, 0);
}
}
void Trace::xtermSetup() {
ptMaster = open("/dev/ptmx", O_RDWR);
if (ptMaster != -1) {
grantpt(ptMaster);
unlockpt(ptMaster);
char *ptSlaveName = ptsname(ptMaster);
ptSlave = open(ptSlaveName, O_RDWR); // In and out are the same
struct termios termInfo{};
tcgetattr(ptSlave, &termInfo);
termInfo.c_lflag &= ~ECHO;
termInfo.c_lflag &= ~ICANON;
tcsetattr(ptSlave, TCSADRAIN, &termInfo);
xtermPid = fork();
if (xtermPid == 0) {
xtermLaunch(ptSlaveName);
}
}
}
SC_HAS_PROCESS(Trace);
Trace::Trace(sc_core::sc_module_name const &name) :
sc_module(name), socket("socket") {
socket.register_b_transport(this, &Trace::b_transport);
xtermSetup();
}
Trace::~Trace() {
xtermKill();
}
void Trace::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
unsigned char *ptr = trans.get_data_ptr();
delay = sc_core::SC_ZERO_TIME;
ssize_t a = write(ptSlave, ptr, 1);
(void) a;
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
execvp("xterm", argv);
}
void Trace::xtermKill() {
if (-1 != ptSlave) { // Close down the slave
close(ptSlave); // Close the FD
ptSlave = -1;
}
if (-1 != ptMaster) { // Close down the master
close(ptMaster);
ptMaster = -1;
}
if (xtermPid > 0) { // Kill the terminal
kill(xtermPid, SIGKILL);
waitpid(xtermPid, nullptr, 0);
}
}
void Trace::xtermSetup() {
ptMaster = open("/dev/ptmx", O_RDWR);
if (ptMaster != -1) {
grantpt(ptMaster);
unlockpt(ptMaster);
char *ptSlaveName = ptsname(ptMaster);
ptSlave = open(ptSlaveName, O_RDWR); // In and out are the same
struct termios termInfo{};
tcgetattr(ptSlave, &termInfo);
termInfo.c_lflag &= ~ECHO;
termInfo.c_lflag &= ~ICANON;
tcsetattr(ptSlave, TCSADRAIN, &termInfo);
xtermPid = fork();
if (xtermPid == 0) {
xtermLaunch(ptSlaveName);
}
}
}
SC_HAS_PROCESS(Trace);
Trace::Trace(sc_core::sc_module_name const &name) :
sc_module(name), socket("socket") {
socket.register_b_transport(this, &Trace::b_transport);
xtermSetup();
}
Trace::~Trace() {
xtermKill();
}
void Trace::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &delay) {
unsigned char *ptr = trans.get_data_ptr();
delay = sc_core::SC_ZERO_TIME;
ssize_t a = write(ptSlave, ptr, 1);
(void) a;
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}

99
src/extension_base.cpp
View File

@ -8,53 +8,56 @@
#include "extension_base.h"
extension_base::extension_base(const sc_dt::sc_uint<32> & instr,
Registers *register_bank, MemoryInterface *mem_interface) :
m_instr(instr), regs(register_bank), mem_intf(mem_interface) {
namespace riscv_tlm {
perf = Performance::getInstance();
logger = spdlog::get("my_logger");
}
extension_base::~extension_base() =default;
void extension_base::setInstr(std::uint32_t p_instr) {
m_instr = sc_dt::sc_uint<32>(p_instr);
}
void extension_base::dump() const {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
}
void extension_base::RaiseException(std::uint32_t cause, std::uint32_t inst) {
std::uint32_t new_pc, current_pc, m_cause;
current_pc = regs->getPC();
m_cause = regs->getCSR(CSR_MSTATUS);
m_cause |= cause;
new_pc = regs->getCSR(CSR_MTVEC);
regs->setCSR(CSR_MEPC, current_pc);
if (cause == EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION) {
regs->setCSR(CSR_MTVAL, inst);
} else {
regs->setCSR(CSR_MTVAL, current_pc);
}
regs->setCSR(CSR_MCAUSE, cause);
regs->setCSR(CSR_MSTATUS, m_cause);
regs->setPC(new_pc);
logger->debug("{} ns. PC: 0x{:x}. Exception! new PC 0x{:x} ", sc_core::sc_time_stamp().value(), regs->getPC(),
new_pc);
}
bool extension_base::NOP() {
logger->debug("{} ns. PC: 0x{:x}. NOP! new PC 0x{:x} ", sc_core::sc_time_stamp().value(), regs->getPC());
sc_core::sc_stop();
return true;
extension_base::extension_base(const sc_dt::sc_uint<32> &instr,
Registers *register_bank, MemoryInterface *mem_interface) :
m_instr(instr), regs(register_bank), mem_intf(mem_interface) {
perf = Performance::getInstance();
logger = spdlog::get("my_logger");
}
extension_base::~extension_base() = default;
void extension_base::setInstr(std::uint32_t p_instr) {
m_instr = sc_dt::sc_uint<32>(p_instr);
}
void extension_base::dump() const {
std::cout << std::hex << "0x" << m_instr << std::dec << std::endl;
}
void extension_base::RaiseException(std::uint32_t cause, std::uint32_t inst) {
std::uint32_t new_pc, current_pc, m_cause;
current_pc = regs->getPC();
m_cause = regs->getCSR(CSR_MSTATUS);
m_cause |= cause;
new_pc = regs->getCSR(CSR_MTVEC);
regs->setCSR(CSR_MEPC, current_pc);
if (cause == EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION) {
regs->setCSR(CSR_MTVAL, inst);
} else {
regs->setCSR(CSR_MTVAL, current_pc);
}
regs->setCSR(CSR_MCAUSE, cause);
regs->setCSR(CSR_MSTATUS, m_cause);
regs->setPC(new_pc);
logger->debug("{} ns. PC: 0x{:x}. Exception! new PC 0x{:x} ", sc_core::sc_time_stamp().value(), regs->getPC(),
new_pc);
}
bool extension_base::NOP() {
logger->debug("{} ns. PC: 0x{:x}. NOP! new PC 0x{:x} ", sc_core::sc_time_stamp().value(), regs->getPC());
sc_core::sc_stop();
return true;
}
}